Prediction on read margin in 1D1R crossbar array

Chapter 3 Ti/TiO 2 /Pt Oxide Diode for 1D1R Resistive-Switching Memory

3.3.4 Prediction on read margin in 1D1R crossbar array

In this section, the prediction on the read margin of 1D1R crossbar array is explained using the device parameters extracted from the standalone 1D1R cell in Fig. 3.9. Figure 3.11 depicts the equivalent circuit of an N × N crossbar memory array in the scenario of read interference where all unselected cells are in LRS [21, 39]. Considering a one bit line pull-up (One-BLPU) read scheme [21], the sneak current can flow through the unselected cells, represented by the parallel resistor networks of R₁, R₂, and R₃ in Fig. 3.11, which leads to read error when the selected cell is in HRS (Rselected

= R

HRS). In the 1D1R crossbar array as shown in Fig. 3.12, R₂ contributed by all unselected cells at unselected word/bit lines in parallel is considerably larger than the sum of R1 and R3 because of the reverse biased diodes.

Therefore, the resistance in the sneak current path can be approximated by R_{LRS_R}/(N-1)², where RLRS_R is the resistance of the standalone 1D1R cell in LRS dominated by the reverse biased diode at the negative read voltage –V_read, as shown in Fig. 3.12. R_{LRS_F} and R_{HRS_F} are also defined as the resistances of the standalone 1D1R cell in LRS and HRS, respectively, when read at V_read. When R_{LRS_R}/(N-1)² decreases as N increases and eventually becomes comparable to RLRS_F

of the selected bit, the sneak current begins to interfere with the read

process in the large 1D1R array. Thus, the ratio of R_{LRS_R} to R_{LRS_F} is a good measure of the maximum crossbar array size with a tolerable read margin. The readout voltage on the pull-up resistor R_pu can be calculated when R_selected= R_{LRS_F} and R_selected= R_{HRS_F}, using an equivalent circuit method similar to that applied for a complementary resistive switch (CRS) crossbar array [39]. When R1 and R3 are omitted in Fig. 3.12, the readout voltage swing V

voltage divider equation as follows:

where Rpu is the resistance of the pulled-up resistor that is set to RLRS_F for maximum read margin. For a 10% readout margin, Figure 3.13 shows that the maximum allowed word lines in a square crossbar array increased dramatically from 2 in a passive array to 750, i.e.

equivalent to about 512 Kb, in a 1D1R array utilizing the parameters extracted from Fig. 3.9.

The 1D1R array can be further scaled up to 1 G-bit with an improved RLRS_R/RLRS_F ratio of 10⁹.

3.4 Summary

A rectifying Ti/TiO₂/Pt oxide diode and a unipolar RS Ni/HfO₂/Pt memory element have been fabricated on a flexible PI substrate with excellent characteristics using only room-temperature processes. No significant device degradation was found at bending states.

Additionally, the impact of IRESET on the programming margin of unipolar RS has been discussed. The heterogeneous TiO₂-HfO₂ 1D1R cell not only demonstrates more stable unipolar RS compared to a monolithic TiO2 1D1R cell because of the lower IRESET in the HfO₂ memory element, but also effectively suppresses the sneak current. The maximum allowed array size with at least 10% read margin is predicted to exceed 512 Kb based on a simple equivalent circuit model. Therefore, the proposed 1D1R cell is extremely attractive for implementing high-density nonvolatile memory in future low-cost flexible electronics.

(Eq. 3.1)

Ar 100sccm

(a)

(b)

R

Fig. 3.2 (a) Photograph of a fabricated flexible device under bending. Insert shows the microscope image of patterned devices on the PI substrate. (b) Measurement setup using a concave stage with a radius of 30 mm to characterize devices at the bending state.

-2 -1 0 1 2

Fig. 3.3 (a) 100 successive cycling of ± 2 V dc sweeps, and (b) cumulative plot of forward/reverse resistances at +1V/-1V of the flexible Ti/TiO2/Pt diodes at both flat and bending states.

0 1 2 3 4

Fig. 3.4 Typical unipolar RS characteristics of the Pt/TiO2/Pt memory element with IRESET over 10 mA.

-1 0 1 2 3 4

Fig. 3.5 Unstable unipolar RS in the monolithic TiO2 1D1R cell because of the small programming margin.

10

^-4

10

^-3

10

^-2

Fig. 3.6 (a) Programming margin of a 1D1R cell as a function of IRESET. The diode on-current was fixed at 10 mA. A RHRS/RLRS ratio of 100, VRESET of 0.5 V and VSET between 2 to 4 V considering cycling variations were assumed for the RS element. (b) Simulated 1D1R unipolar switching curves for RS elements with IRESET of 0.1 mA and 10 mA, respectively.

10

^-8

Fig. 3.7 (a) 100 successive unipolar RS cycles with IRESET less than 1 mA, and (b) cumulative plot of HRS/LRS resistance at 0.2 V of the flexible Ni/HfO2/Pt memory element at both flat and bending states.

10 ² 10 ³ 10 ⁴

Retention time (s)

10 ¹ 10 ² 10 ³ 10 ³

10 ⁴ 10 ⁵ 10 ⁶

Resistan ce (  )

Stress time (s) HRS

V _stress @0.2V LRS V _read @0.2V

HRS

LRS bending

flat

bending flat

Fig. 3.8 Read disturb and retention characteristics of the flexible Ni/HfO2/Pt memory element at both flat and bending states.

-2 -1 0 1 2 3 4

Fig. 3.9 More than 200 successive unipolar RS cycles with a high rectifying ratio at ±1 V in the heterogonous TiO2-HfO2 1D1R cell.

Fig. 3.10 (a) TEM image and schematic structure of a vertically stacked Ti/TiO2/Pt/Ni/HfO2/Pt 1D1R cell and (b) unipolar RS I-V with a high rectifying ratio of the vertically stacked 1D1R cell.

Fig. 3.11 Schematic of an N × N crossbar memory array and its equivalent circuit at the worse-case read scenario where all unselected cells are at LRS. The sneak current through R1, R2 and R3 results in severe read interference.

-V

_read

V

_read

Fig. 3.12 Equivalent circuit of a 1D1R crossbar array at read. The total resistance of the sneak current path is dominant by R2 because of the reverse-biased diodes.

2

⁵

2

⁷

2

⁹

2

¹¹

2

¹³

2

¹⁵

2

¹⁷

2

¹⁹

Fig. 3.13 Normalized readout margin V/Vpu as a function of the number of word/bit line in an N

× N crossbar array. The maximum allowed array size with at least 10 % readout margin can be dramatically increased in 1D1R arrays compared to 1R passive arrays.

Chapter 4 Bipolar Nonlinear Ni/TiO ₂ /Ni Selector for 1S1R Crossbar Array Applications

4.1 Introduction

Compatible with the 4F² crossbar array, the stacking one diode-one resistor (1D1R) structure appears as one of the most attractive candidate. Their superior unipolar RS properties have been discussed in previous chapters. However, diodes with sufficient high forward current density and stable unipolar RS elements are still under investigation.

Considering a bipolar RS element, a selection device should be able to exhibit a bidirectional current to allow the bipolar switching and nonlinear I-V characteristics to cut-off the sneak current. Although complementary resistive switching (CRS) using two bipolar RS elements connected in anti-series has been considered a soultion to reduce the sneak current [39, 41, 69], the inherent destructive read process imposes severe penalties on the design complexity, operational speed and power consumption. On the other hand, a cell structure, consisting of one bipolar nonlinear selector and one bipolar RS element (1S1R), can best utilize the stable bipolar RS properties while the read process is nondestructive [68]. However, the reported bipolar selector had limited nonlinearity only sufficient for a small array. Significant improvements on the selector characteristics are needed for the high-density 1S1R crossbar array. Moreover, the endurance of 1S1R cells has not yet been verified, but remains a great concern because the selector may suffer dielectric breakdown at high voltage [68].

In this chapter, we fabricated a Ni/TiO2/Ni metal–insulator–metal (MIM) by a very simple low-temperature process. Excellent bipolar nonlinear characteristics, including current difference of 6 orders of magnitude for a voltage swing from 0 to ±2 V and

breakdown voltage larger than 4 V, are realized by Schottky emission over the Ni/TiO2

barriers. By connecting the bipolar selector to a HfO2 RS element in series, we report very reproducible bipolar RS with highly nonlinear I-V characteristics applicable for large megabit (Mb)-size crossbar arrays. In addition, the tradeoff between the maximum array size and the power consumption, which is important for the high-density array design, is also discussed.

4.2 Comparison of 1D1R and 1S1R Crossbar Arrays

For simplicity, the sneak current path at read and an equivalent circuit of a data pattern where all unselected bits were at low resistance state (LRS) are illustrated in Fig. 4.1(a). The simplified equivalent circuit of crossbar array using one bit-line pull-up (One-BLPU) read scheme [21, 46] is shown in Fig. 4.1(b). Note that the interconnect resistances of WLs/BLs are not included in our discussion. In order to ensure sufficient read margin in high-density arrays, a unipolar diode (or a bipolar selector) may be connected with a unipolar (or a bipolar) RS element in series to increase the nonlinearity of the LRS resistance, as shown in Fig. 4.2.

The nonlinearity factor



was defined differently for 1D1R and 1S1R because approximately a full read voltage (Vread) would drop across the cells on unselected WLs/BLs subjected to a reverse bias (RII in Fig. 4.2(a)) in 1D1R, while only Vread/2 would drop across the unselected cells on the selected WLs/BLs (RI and RIII in Fig. 4.2(b)) in 1S1R. It can be shown that the maximum allowed number of word lines N in a square array scaled proportionally to



^0.5 for 1D1R but to



for 1S1R in a first approximation. Figure 4.3 shows the calculated read margin using the equivalent circuits in Fig. 4.2.



of 10⁶ and 10⁹ were required for a megabit and a gigabit 1D1R array, respectively. The best 1D1R cell ever reported had



less than 10⁵ [68]. In contrast, 1S1R deserves serious consideration in high-density crossbar arrays because of much relaxed requirement on



, 3×10² and 10⁴, for a megabit and a gigabit array.

Furthermore, programming margin between set voltage (VSET) and reset voltage (VRESET) in 1S1R is inherently larger because of the bipolar RS nature, favorable for stable memory operations with minimal soft error.

4.3 Device Fabrication Process

To fabricate the Ni/TiO2/Ni selector (S1), the TiO2 films of 15 nm were deposited on Ni/SiO2/Si substrates by reactive sputtering at 200 ^oC using a Ti target (99.5%) in a mixture of Ar and O2. Ni top electrodes were then deposited by sputtering and patterned by standard lithography process with cell size from 0.36 m² to 10⁴ m². As for the RS element, Ni/HfO2/Pt structures were deposited on a Ti/SiO2/Si substrate by sputtering at room temperature. After initial forming, reproducible bipolar RS with RESET current of 100 μA [see R1 in Fig. 4.4(a)] to 1 mA [see R2 in Fig. 4.4(a)] was obtained by adjusting the compliance current at SET. The RS in Ni/HfO2/Pt was attributed to the electromigration of Ni from the top electrode, which is similar to what we have discussed in the Ni/HfO2/Si structures [71]. The series 1S1R measurements were carried out by connecting the Ni/TiO2/Ni and Ni/HfO2/Pt devices externally, where the voltage was applied on the Ni top electrode of the Ni/TiO2/Ni device, and the Pt bottom electrode of the Ni/HfO2/Pt device was grounded.

4.4 Results and Discussion

4.4.1 I–V characteristics of bipolar Ni/TiO

/Ni selector

Figure 4.4(a) illustrates the current–voltage (I–V) characteristics of the Ni/TiO2/Ni MIM selector with an exponential current increase over six orders of magnitude for a voltage swing from 0 to ±2 V. No dielectric breakdown occurred within ±4 V. The TEM images of Ni/TiO2/Ni structure and the Ni/TiO2 interfaces are illustrated in Figs. 4.4(b) and 4.4(c),

respectively. The nonlinearity in I–V with direct-current cycling up to 1000 times neither degraded nor reduced were observed as we show in Fig. 4.5(a), implying the stable operation property of bipolar selector. Figure 4.5(b) shows Schottky emission fitting of log (I) versus

V

^1/2. The observed highly nonlinear I–V curves were mainly dominated by the Schottky emission over the Ni/TiO2 barriers at low voltage, whereas an additional current component, which is likely related to other defect assisted transport mechanisms, led to the slight current increase at high negative bias. Note that the maximum current was eventually limited by a parasitic series resistance estimated about 50 Ω. Figure 4.5 (c) exhibits the field-dependent Schottky barrier height Φb extracted from temperature-dependent fitting of log (I/T²) versus 1/T measured from 25 to 125 ^oC at low voltage regime. The Φb of both the top and bottom Ni/TiO2 interfaces were extrapolated to be 0.58 eV at 0 V. The value was between that of Ti/TiO2 (0.13 eV) and that of Pt/TiO2 (0.85 eV) and desirable for high nonlinearity within the interesting range of voltage swing. The strong dependence on the electrode materials further supported that the Schottky emission instead of the Poole–Frenkel emission assisted by TiO2

bulk traps was mainly responsible for current conduction. Figure 4.6 further shows the I-V characteristics of Ni/TiO2/Ni bipolar selectors with various device areas fabricated by conventional lithography. Current density more than 10⁵ A/cm² with device area scaling down to 0.36 m² can be achieved, indicating the applicability of driving a sub-20 nm bipolar RRAM with RESET current (IRESET) below sub-A [24].

4.4.2 Bipolar 1S1R resistive switching

Figure 4.7(a) shows the I–V characteristics of S1 in series with R1, where more than 200 successive bipolar switching cycles were plotted. The I–V characteristics were determined by the superposition of S1 and R1, dominated by S1 and R1 at low and high voltage regimes, respectively. As a result, the resistance was highly nonlinear and bias

reliable programming, in contrast to the smaller separation at the same polarity for the unipolar RS. Moreover, very tight distribution of SET/RESET voltages and SET-state/RESET-state resistance was clearly observed. The SET and RESET voltages in the 1S1R device were higher, as compared to those of the single R1 due to the additional voltage drop on S1. Figure 4.7(b) shows excellent immunity to read disturb at +2 V and −2 V for the high- and low-resistance states, respectively. To read the 1S1R crossbar array, a full read voltage Vread was applied to read the selected cell, while only half of Vread drop on the unselected cells. As apparent in Fig. 4.7(a), for a Vread of 4V, sneak current at 1/2 Vread, i.e. 2V, was low enough to prevent read disturb.

4.4.3 Read margin analysis

To read from the 1S1R array, one read scheme, One-BLPU was considered [21, 46].

Only one bit line was pulled up, and all other bit lines were floating when each word line was selected. Thus, a specific data pattern was assumed, where all unselected cells were simultaneously at the low-resistance state with resistance of RLRS or high-resistance state with resistance of RHRS. The simplified equivalent circuit of a square N × N 1S1R array with negligible line resistances is depicted in Fig. 4.1(b). RI, RII and RIII are the equivalent resistance of region I, II and III in Fig. 4.1(a), respectively. The voltage on the pull-up resistor (Rpu) connected to the selected bit line was evaluated to measure voltage swing (Vpu) when reading the selected cell (Rselected). For a large array, the read voltage (Vread) along the sneak current path across the parallel resistor network of the unselected WLs/BLs (RII=RLRS/(N−1)²) in Fig. 4.2(b)] can be analytically ignored and was shared by the RI and RII. In other words, only half of the voltage (Vread/2) would drop on RI and RII, respectively. To a first approximation, 2RLRS/(N−1) at Vread/2 through the sneak path should not be less than

R

LRS at Vcell to ensure a sufficient read margin between the high- and low-resistance states of the selected cell. In other words, the nonlinearity factor α of the low-resistance state in 1S1R

cells, i.e., the ratio of RLRS at Vread/2 to RLRS at Vread, was the primary factor of determining the maximum array size instead of the resistance ratio between the high/low-resistance states (RHRS/RLRS), which plays an important role in the optimization of the passive crossbar array [21]. A more quantitative assessment on the read margin ΔV normalized to the pull-up voltage Vpu can be calculated by solving the Kirchhoff equation

(Eq. 4.1) where Rpu is the resistance of the pulled-up resistor, set to RLRS at Vread for maximum read margin [21]. We used a sensing criterion of a minimal 10 %V/Vpu to determine the maximum crossbar array size [39]. The calculated maximum array size with at least 10%

read margin increased from N = 5 (R1 only) to N = 501 (S1 + R1), as shown in Fig. 4.7, where Vread of 2 V was chosen not only to maximize



but also to guarantee a sufficient margin of the read disturb. The superposed nature of 1S1R provided additional freedom in engineering nonlinearity by tuning the resistance of the RS element. That means that we can independently modulate the current-voltage behaviors of LRS at high/low voltage regions to get the benefit of nonlinearity. On the other hand, R1 can be replaced by R2 with lower RLRS

to further improve α. The maximum array size can be further scaled up to N > 3k with Vread

of 2.5 V or nearly 10 Mb, among the largest of all existing projections on the bipolar crossbar array based on the xperimental results [41, 68]. However, this also unavoidably increased the RESET power mainly due to the larger RESET current. The RESET voltage also increased from 3.7 to 4.6 V. Therefore, design optimization in choosing the appropriate RS element is required to tradeoff array size, operational voltages, and power for a given nonlinear selector. Finally, Table I summarizes the extracted parameters and the calculated maximum array size from the 1S1R cells measured in this study.

4.5 Summary

A Ni/TiO2/Ni MIM with highly nonlinear I-V characteristics has been proposed as the bipolar selector for high-density 1S1R crossbar arrays. The nonlinearity is attributed to the Schottky barriers at the Ni/TiO2 interface. The selector in series with an HfO2 RS element exhibits robust and stable bipolar RS, and can effectively suppress the sneak current to allow large Mb-size array implementation. The results demonstrate the significant potential of 1S1R crossbar array architectures for the future high-density memories and reconfigurable logic circuits.

Table 4.1 Extracted parameters from the 1S1R cells measured in this chapter.

…

Fig. 4.1 Sneak current path at read in a square crossbar array where all bits except the selected one are at LRS, and (b) the equivalent circuit can be represented by RI, RII, and RIII of parallel resistor networks in region 1 (bits on selected BL), region 2 (bits on unselected WL and BL), and region 3 (bits on selected WL).

selected

Fig. 4.2 RS I-V curves for (a) 1D1R and (b) 1S1R RRAM cells, and their nonlinearity factor



and equivalent circuits in a crossbar array. RII subjected to a reverse bias is much larger than RI and RIII in 1D1R, while RII scaled with (N-1)² is much smaller than RI and RIII

scaled with (N-1) in 1S1R.

10

Fig. 4.3 Calculated read margin as a function of



for both 1D1R and 1S1R using the equivalent circuits in Fig. 4.1 and RHRS/RLRS = 10³.

Fig. 4.4 (a) I–V characteristics of the bipolar Ni/TiO2/Ni MIM selector (S1) and bipolar Ni/HfO2/Pt RS elements (R1 and R2). (b)(c) TEM cross-section images of the Ni/TiO2/Ni selector.

Fig. 4.5 (a) Endurance I-V of Ni/TiO2/Ni selector over 1000 cycles. (b) Schottky emission fitting of log (I) versus V^1/2 at both voltage polarities of S1. (c) Extracted Schottky barrier height Φb by temperature-dependent fitting from the low voltage regime of S1.

10

^-2

10

⁰

10

⁴

10

⁴

10

⁵

J (A/cm

)

Area (  m

) at -4 V

-4 -3 -2 -1 0 1 2 3 4 10 ^-10

10 ^-8 10 ^-6 10 ^-4

10 ² /1/0.36

 m ²

Current (A)

Voltage (V)

10 ⁴  m ²

Fig. 4.6 I-V characteristics of Ni/TiO2/Ni bipolar selectors with various device areas fabricated by conventional lithography on Si substrates. Insert shows that current density higher than 10⁵ A/cm² with device area scaling down to 0.36 m² can be achieved.

Fig. 4.7 (a) More than 200 successive bipolar switching cycles of S1 and R1 connected in series with 100 μA compliance current and (b) read disturb for the HRS stressed at +2 V and the LRS stressed at –2 V.

10

⁴

0 10 20 30 40 50

R1

R2+S1

Re ad mari gn (% of  V / V pu )

Number of word lines (N) R1+S1

Fig. 4.8 Read margin V/Vpu as a function of N in various crossbar configurations calculated from (Eq. 4.1) based on the equivalent circuit shown in Fig. 4.2(b).

Chapter 5 1S1R Crossbar Array for Low-cost Flexible Electronic Applications

5.1 Introduction

Low-cost flexible electronics on plastic substrates are excellent complements to present Silicon electronics built by costly fabrication technology on rigid substrates in multi-billion-dollar fabs [72]. Their success depends strongly on the development of novel devices fabricated at a very low temperature process. In Chapter 3, unipolar 1D1R cells, consisting of a Ti/TiO₂/Pt diode and Ni/HfO₂/Pt RS memory elements have been proposed and examined on plastic substrates for flexible nonvolatile memory applications [73]. In contrast to unipolar RS, bipolar RS due to its inherently distinguishable programming margin should be greatly emphasized. In Chapter 4, we have proposed a Ni/TiO2/Ni structure with highly nonlinear I-V characteristics and demonstrated the meaningful potential of effectively suppressing the sneak current to build large array size. Additionally, the combined bipolar Ni/TiO₂/Ni selector and Ni/HfO₂/Pt RS element displayed a robust and stable 1S1R bipolar RS on Si substrates [70]. Because those devices are low-temperature process available, it is of great interest to evaluate their novel applications not only on rigid substrates but also on plastics substrates. However, previous studies were limited to only one component, and their integration on high-density crossbar arrays had never been realized [68, 70], even though 1S1R exploits more favorable bipolar switching. On the other hand, although solution-based process, such as sol-gel coating, has advantages of low cost and simple processing to achieve low-temperature fabrication, an additional annealing process is required for densified films and additionally, cell-to-cell uniformity has not yet been confirmed [47].

In this chapter, we use a low-temperature and simple sputtering process to fabricate a high-performance Ni/TiO2/Ni bipolar selector and a reproducible RS Ni/HfO2/Pt memory element on plastic substrates. Furthermore, by a simple 5-mask process, we report for the first time a vertically stacked Ni/TiO2/Ni/HfO2/Pt 8×8 1S1R array completely fabricated at room temperature, nevertheless showing promise of realizing unprecedented G-bit NVM in

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