Read margin analysis

To read from the 1S1R array, one read scheme, One-BLPU was considered [21, 46].

Only one bit line was pulled up, and all other bit lines were floating when each word line was selected. Thus, a specific data pattern was assumed, where all unselected cells were simultaneously at the low-resistance state with resistance of RLRS or high-resistance state with resistance of RHRS. The simplified equivalent circuit of a square N × N 1S1R array with negligible line resistances is depicted in Fig. 4.1(b). RI, RII and RIII are the equivalent resistance of region I, II and III in Fig. 4.1(a), respectively. The voltage on the pull-up resistor (Rpu) connected to the selected bit line was evaluated to measure voltage swing (Vpu) when reading the selected cell (Rselected). For a large array, the read voltage (Vread) along the sneak current path across the parallel resistor network of the unselected WLs/BLs (RII=RLRS/(N−1)²) in Fig. 4.2(b)] can be analytically ignored and was shared by the RI and RII. In other words, only half of the voltage (Vread/2) would drop on RI and RII, respectively. To a first approximation, 2RLRS/(N−1) at Vread/2 through the sneak path should not be less than

R

LRS at Vcell to ensure a sufficient read margin between the high- and low-resistance states of the selected cell. In other words, the nonlinearity factor α of the low-resistance state in 1S1R

cells, i.e., the ratio of RLRS at Vread/2 to RLRS at Vread, was the primary factor of determining the maximum array size instead of the resistance ratio between the high/low-resistance states (RHRS/RLRS), which plays an important role in the optimization of the passive crossbar array [21]. A more quantitative assessment on the read margin ΔV normalized to the pull-up voltage Vpu can be calculated by solving the Kirchhoff equation

(Eq. 4.1) where Rpu is the resistance of the pulled-up resistor, set to RLRS at Vread for maximum read margin [21]. We used a sensing criterion of a minimal 10 %V/Vpu to determine the maximum crossbar array size [39]. The calculated maximum array size with at least 10%

read margin increased from N = 5 (R1 only) to N = 501 (S1 + R1), as shown in Fig. 4.7, where Vread of 2 V was chosen not only to maximize



but also to guarantee a sufficient margin of the read disturb. The superposed nature of 1S1R provided additional freedom in engineering nonlinearity by tuning the resistance of the RS element. That means that we can independently modulate the current-voltage behaviors of LRS at high/low voltage regions to get the benefit of nonlinearity. On the other hand, R1 can be replaced by R2 with lower RLRS

to further improve α. The maximum array size can be further scaled up to N > 3k with Vread

of 2.5 V or nearly 10 Mb, among the largest of all existing projections on the bipolar crossbar array based on the xperimental results [41, 68]. However, this also unavoidably increased the RESET power mainly due to the larger RESET current. The RESET voltage also increased from 3.7 to 4.6 V. Therefore, design optimization in choosing the appropriate RS element is required to tradeoff array size, operational voltages, and power for a given nonlinear selector. Finally, Table I summarizes the extracted parameters and the calculated maximum array size from the 1S1R cells measured in this study.

4.5 Summary

A Ni/TiO2/Ni MIM with highly nonlinear I-V characteristics has been proposed as the bipolar selector for high-density 1S1R crossbar arrays. The nonlinearity is attributed to the Schottky barriers at the Ni/TiO2 interface. The selector in series with an HfO2 RS element exhibits robust and stable bipolar RS, and can effectively suppress the sneak current to allow large Mb-size array implementation. The results demonstrate the significant potential of 1S1R crossbar array architectures for the future high-density memories and reconfigurable logic circuits.

Table 4.1 Extracted parameters from the 1S1R cells measured in this chapter.

…

Fig. 4.1 Sneak current path at read in a square crossbar array where all bits except the selected one are at LRS, and (b) the equivalent circuit can be represented by RI, RII, and RIII of parallel resistor networks in region 1 (bits on selected BL), region 2 (bits on unselected WL and BL), and region 3 (bits on selected WL).

selected

Fig. 4.2 RS I-V curves for (a) 1D1R and (b) 1S1R RRAM cells, and their nonlinearity factor



and equivalent circuits in a crossbar array. RII subjected to a reverse bias is much larger than RI and RIII in 1D1R, while RII scaled with (N-1)² is much smaller than RI and RIII

scaled with (N-1) in 1S1R.

10

Fig. 4.3 Calculated read margin as a function of



for both 1D1R and 1S1R using the equivalent circuits in Fig. 4.1 and RHRS/RLRS = 10³.

Fig. 4.4 (a) I–V characteristics of the bipolar Ni/TiO2/Ni MIM selector (S1) and bipolar Ni/HfO2/Pt RS elements (R1 and R2). (b)(c) TEM cross-section images of the Ni/TiO2/Ni selector.

Fig. 4.5 (a) Endurance I-V of Ni/TiO2/Ni selector over 1000 cycles. (b) Schottky emission fitting of log (I) versus V^1/2 at both voltage polarities of S1. (c) Extracted Schottky barrier height Φb by temperature-dependent fitting from the low voltage regime of S1.

10

^-2

10

⁰

10

²

10

⁴

10

¹

10

²

10

³

10

⁴

10

⁵

J (A/cm

2

)

Area (  m

²

) at -4 V

-4 -3 -2 -1 0 1 2 3 4 10 ^-10

10 ^-8 10 ^-6 10 ^-4

10 ² /1/0.36

 m ²

Current (A)

Voltage (V)

10 ⁴  m ²

Fig. 4.6 I-V characteristics of Ni/TiO2/Ni bipolar selectors with various device areas fabricated by conventional lithography on Si substrates. Insert shows that current density higher than 10⁵ A/cm² with device area scaling down to 0.36 m² can be achieved.

Fig. 4.7 (a) More than 200 successive bipolar switching cycles of S1 and R1 connected in series with 100 μA compliance current and (b) read disturb for the HRS stressed at +2 V and the LRS stressed at –2 V.

10

¹

10

²

10

³

10

⁴

0

10 20 30 40 50

R1

R2+S1

Re ad mari gn (% of  V / V pu )

Number of word lines (N) R1+S1

Fig. 4.8 Read margin V/Vpu as a function of N in various crossbar configurations calculated from (Eq. 4.1) based on the equivalent circuit shown in Fig. 4.2(b).

Chapter 5

1S1R Crossbar Array for Low-cost Flexible Electronic Applications

5.1 Introduction

Low-cost flexible electronics on plastic substrates are excellent complements to present Silicon electronics built by costly fabrication technology on rigid substrates in multi-billion-dollar fabs [72]. Their success depends strongly on the development of novel devices fabricated at a very low temperature process. In Chapter 3, unipolar 1D1R cells, consisting of a Ti/TiO₂/Pt diode and Ni/HfO₂/Pt RS memory elements have been proposed and examined on plastic substrates for flexible nonvolatile memory applications [73]. In contrast to unipolar RS, bipolar RS due to its inherently distinguishable programming margin should be greatly emphasized. In Chapter 4, we have proposed a Ni/TiO2/Ni structure with highly nonlinear I-V characteristics and demonstrated the meaningful potential of effectively suppressing the sneak current to build large array size. Additionally, the combined bipolar Ni/TiO₂/Ni selector and Ni/HfO₂/Pt RS element displayed a robust and stable 1S1R bipolar RS on Si substrates [70]. Because those devices are low-temperature process available, it is of great interest to evaluate their novel applications not only on rigid substrates but also on plastics substrates. However, previous studies were limited to only one component, and their integration on high-density crossbar arrays had never been realized [68, 70], even though 1S1R exploits more favorable bipolar switching. On the other hand, although solution-based process, such as sol-gel coating, has advantages of low cost and simple processing to achieve low-temperature fabrication, an additional annealing process is required for densified films and additionally, cell-to-cell uniformity has not yet been confirmed [47].

In this chapter, we use a low-temperature and simple sputtering process to fabricate a high-performance Ni/TiO2/Ni bipolar selector and a reproducible RS Ni/HfO2/Pt memory element on plastic substrates. Furthermore, by a simple 5-mask process, we report for the first time a vertically stacked Ni/TiO2/Ni/HfO2/Pt 8×8 1S1R array completely fabricated at room temperature, nevertheless showing promise of realizing unprecedented G-bit NVM in extremely low-cost flexible electronics.

5.2 Experimental Procedure

Prior to the device fabrication, 75-m-thick Kapton^○R polyimide (PI) substrates were cut and ultrasonically cleaned in acetone for 10 min to remove particles and contamination, followed by a 100^oC baking for 30 min. The cleaned PI substrates were then electrostatically attached to silicon wafers. Then, a buffer layer of SiO₂ with a thickness of 300 nm was deposited on PI substrates by plasma-enhanced chemical vapor deposition (PECVD). To fabricate the 1S1R crossbar array, a Ni/TiO₂/Ni/HfO₂/Pt 8×8 crossbar array was fabricated by reactive sputtering system using a 5-mask shadow-mask process on a flexible polyimide substrate. As illustrated in Fig. 5.1, mask 1 was used to define Pt/Ti bottom electrodes with width of 220 m. HfO2 switching layer were then deposited through mask 2, followed by Ni top electrodes of memory elements (or bottom electrodes of selector elements) deposition through mask 3, where electrical properties of the single element could be separately measured through the metal contact by mask 3. Next, TiO₂ active layer and Ni top electrodes of selector elements were defined sequentially by mask 4 and mask 5.

Among which, the active layers, HfO₂ with thickness of 80 nm and TiO₂ with thickness of 60 nm were prepared by dc magnetron reactive sputtering using Hf target (99.5%) and Ti target (99.5%) in a mixture of Ar and O₂, respsctively. The chamber working pressure was 5 mTorr. In addition, a single element, Ni/TiO2/Ni metal-insulator-metal (selector element) and

a Ni/HfO₂/Pt (memory element) were fabricated at the same time by a simple shadow-mask process. All devices reported in this study were fabricated completely at room temperature without any additional thermal treatment. Figures 5.2(a) depicts a 8 × 8 1S1R crossbar array and the cross-section view of fabricated Ni/TiO2/Ni/HfO2/Pt stack. The top-view photograph of a flexible 8 × 8 1S1R array under a curly bending and the image inspected by the optical microscope are shown in Figs. 5.2 (d) and (c), respectively. In our electrical measurement setup, a bending vehicle with a radius of 10 mm was used to characterize flexible devices as shown in Fig. 5.3.

5.3 Results and Discussion

5.3.1 Flexible Ni/TiO

2

/Ni and Ni/HfO

2

/Pt

Figure 5.4 shows the bipolar I–V characteristics of the flexible Ni/TiO₂/Ni selector, where the highly nonlinear and symmetric I–V characteristics of at both polarities were determined through Schottky emission over the Ni/TiO₂ barriers of 0.58 eV as we have evaluated in Chapter 4. The barriers at the Ni/TiO2 interfaces significantly affect the nonlinearity of current conduction. Therefore, to further modulate the interfaces is necessary to obtain a high nonlinearity and symmetric I–V characteristics of the Ni/TiO2/Ni selector. It is particularly important for selectors used in flexible electronics that the bipolar I-V characteristics are not affected by the bending condition of the plastic substrate. Figure 5.5(a) shows excellent cycling endurance at both flat and bending states, where data more than 1000 cycles under ±4 V sweep were collected. Even though fabricated on the flexible substrate, Ni/TiO2/Ni selector exhibits a superior stability with nonlinearity factor



of ~10³ at Vread of 1.2 V. The selector current increased at the bending state, but can be recovered after removing the strain as evidenced in Fig. 5.5(b). It is possible due to the distribution of localized defects induced by the local fields of bending strain, as reflected in an increasing

shift of conduction current [74, 75].

As for the memory element, it is also particularly important for devices used in flexible electronics that the RS characteristics are not affected by the flexing of the devices. Figure 5.6(a) displays extremely reproducible bipolar RS in both flat and bending devices with a resistance ratio of at least 10³. During 100 endurance cycles, tight distributions on high resistance state (HRS) resistance, LRS resistance, VSET, and VRESET in both flat and bending devices retain their values without significant change at the reading voltage, as shown in Fig.

5.6(b). Note that the bipolar RS was attributed to the connection/rupture of Ni filaments in HfO₂ though electromigration [71]. Read disturb and retention tests were conducted in order to investigate the reliability of the flexible RRAM. Figure 5.7 (a) and (b) show superior immunity to read disturb and retention characteristics at a reading voltage of 0.5 V for both flat and bending devices. The bipolar RRAM on the flexible substrate shows good retention characteristics up to 10⁴ s without electrical degradation in both LRS and HRS under flat and bending devices, indicating the applicability of flexible RRAM in flexible electronics. A fast bipolar RS transient by a set pulse (+4 V, 100 ns) pulse and reset pulse (–4 V, 100 ns) is exhibited in Fig. 5.8(a), in which a read pulse (1 V, 400 ns) was applied to determine the resistance state. We can further identify the robust endurance of Ni/HfO₂/Pt memory element without degradation up to 10⁶ pulse cycles by the condition of 100 ns at ±4 V in Fig. 5.8(b).

After 10⁶ cycles, each memory cell exhibited two resistance states with LRS/HRS ratio >

10³.

Overall, the bipolar selector and bipolar memory element represent an extremely promising solution of potentially flexible memories. The stacked bipolar selector and RRAM were further constructed together to examine the 1S1R electrical characteristics with the plastic substrate used.

5.3.2 Flexible and vertically stacked 1S1R array

Figure 5.9 shows reproducible nonlinear bipolar RS curves in the stacked Ni/TiO₂/Ni/HO₂/Pt cell, where high nonlinearity at low voltage regime was dominated by the bipolar selector, and resistive-switching at high voltage regime was dominated by the memory element. VSET/VRESET below ±4 V, IRESET less than 150



A, and

 of 10

³ at 1.2 V

V

_read were realized. As we have discussed in Chapter 4 (Fig. 4.3), this reported

 is sufficient

to implement a high-density array of 10 Mb, the largest ever reported for a 1D1R or 1S1R crossbar array. A gigabit memory chip partitioned into 16 banks would require a single array (bank) size of 64 Mb [76]. In order to evaluate the 8 × 8 1S1R crossbar array, all unselected cells were firstly programmed to LRS except the selected cell as shown in the equivalent circuit in Fig. 5. 10. To read the selected bit (as marked in red square), a voltage V_pu was applied between the selected top electrode and bottom electrode, while all unselected top/bottom lines were floating. As displayed in Fig. 5. 10, the read current with respect to the LRS/HRS of the selected cell in 8 × 8 crossbar arrays can be compared. With an Rpu load line was plotted, we can estimate the voltage swing (V) between the 1S1R and 1R only crossbar arrays. Though device uniformity has not yet been optimized in the 8 × 8 1S1R array, successfully read margin of 0.82 V can be performed even when all unselected bits were at LRS, in sharp contrast to the collapsed read margin in an 8×8 1R array.

Moreover, program disturb in crossbar arrays is also a serious issue. To reduce disturbs to neighboring cells in the 1S1R array, the Vdd/2 write scheme, a much severe condition as compared to the V_dd/3 scheme, was used to evaluate the 1S1R write operation as illustrated in Fig. 5.11(a). In this scheme, a full VSET or VRESET was applied to the selected cell, but only those unselected cells along the selected word line or bit line endured one half of V_SET or

V

RESET. Figure 5.11(b) shows the excellent immunity of both LRS and HRS to program disturb at 1/2 V_SET and 1/2 V_RESET. In this case, stress voltages of +2 V for HRS and –2 V for LRS were applied to perform the immunity of SET/RESET disturbance of stacked

Ni/TiO₂/Ni/HfO₂/Pt. Finally, we conclude three possible architectures, 1S1R, 1D1R and CRS in Fig. 5.12. Based on the analytical calculation used in Chapter 4, the maximum allowed array number with the corresponding architectures as a function of nonlinear factor (



) can be plotted. Note that we redefined the R_HRS/R_LRS ratio of memory elements in CRS from the reported data [39] as the nonlinear factor. From the best reported CRS data [41], nonlinearity ~10² can only be utilized up to 16K-bit for CRS array. In comparison with our reported data, 512K-bit for 1D1R and 10M-bit for 1S1R have been demonstrated and realized on flexible substrates, showing their potential applications for future flexible electronics.

5.4 Summary

In this chapter, we demonstrate the bipolar I–V characteristics of flexible Ni/TiO₂/Ni selector with high nonlinearity and the stable RS characteristics of Ni/HfO2/Pt. The flexible Ni/TiO₂/Ni and Ni/HfO₂/Pt elements also had excellent mechanical stability upon harsh bending. Furthermore, a vertically stacked 8 × 8 1S1R array with superior read margin, endurance, immunity to read/program disturbs and retention has been realized. The simple cell structure and room-temperature process are particularly attractive for implementing high-density NVM in future low-cost flexible electronics and three-dimensional integrated circuits.

Fig. 5.1 (a) Polyimide (PI) substrates were prepared and ultrasonically cleaned in acetone. (b) Pt/Ti bottom electrodes deposition through mask 1.

Fig. 5.1 (c) HfO₂ deposition through mask 2 and (d) Ni metal layer deposition through mask 3.

Fig. 5.1 (e) TiO₂ deposition through mask 4 and (f) Ni top electrode deposition through mask 5.

Fig. 5.2 (a) Cross-sectional view and (b) photograph of a flexible 8×8 1S1R memory array with a curly bending, and (c) optical microscope image of a vertically stacked Ni/TiO2/Ni/HfO2/Pt cell.

Fig. 5.3 Photograph of a flexible device with a bending radius of 10 mm under electrical testing.

-4 -2 0 2 4

Fig. 5.4 Highly nonlinear and reproducible I-V curves of Ni/TiO2/Ni bipolar selector (1000 successive cycles) by Schottky emission over Ni/TiO₂ barriers.

10

³

10

⁴

10

⁵

10

⁶

10

⁷

10

⁸

Fig. 5.5 (a) Endurance of the flat and bending Ni/TiO₂/Ni bipolar selectors under ±3 V DC cycling and (b) measured resistance of Ni/TiO2/Ni bipolar selector at alternate flat and bending states.

(a)

(b)

-3 -2 -1 0 1 2 3

Fig. 5.6 (a) 100 successive bipolar RS I-V curves and (b) cumulative distribution of SET voltage and RESET voltage for both flat and bending Ni/HfO2/Pt memory elements.

(a)

(b)

10

⁰

10

¹

10

²

10

³

Fig. 5.7 (a) Read disturbance measurement stressed at 0.2 V and (b) retention measurement of flat and bending Ni/HfO₂/Pt memory elements.

(a)

(b)

0.0 0.5 1.0 1.5 2.0 2.5

-4 -3 -2 -1 0 1 2 3 4 10 ^-9

10 ^-7 10 ^-5 10 ^-3

Current (A)

Voltage (V)

2

V

read ^read

V

~ 10 ³

Fig. 5.9 Bipolar I-V RS cycles of vertically stacked Ni/TiO2/Ni/HfO2/Pt with



of 10³ at Vread of 1.2 V.

Fig. 5.10 Read margin between LRS and HRS in an 8 × 8 1R array and 1S1R array where all unselected bits were at LRS (See equivalent circuits in Fig. 4.1 & 4.2).

V

Fig. 5.11 (a) Vdd/2 SET/RESET scheme where only the unselected bits on the activated WL and BL are subjected to disturb voltage of V/2 and (b) SET/RESET disturbance measurement at 1/2 VSET/VRESET on vertically stacked Ni/TiO2/Ni/HfO2/Pt. HRS was stressed at +2 V while LRS was stressed at -2 V.

(a)

(b)

10

¹

10

²

10

³

10

⁴

10

⁵

10

⁶

10

⁷

Fig. 5.12 Comparison of the maximum allowed array number based on the reported 1S1R [77, 79], 1D1R [73] and CRS [41, 78] architectures.

Chapter 6

Conclusion and Further Recommendation

6.1 Conclusion

Two TiO2-based selection devices were proposed to reduce the sneak current in this dissertation. The unipolar Ti/TiO₂/Pt diode shows superior capability of conducting unipolar 1D1R switching by externally connecting a Ni/HfO2/Pt memory element. Meanwhile, a bipolar Ni/TiO₂/Ni selector was investigated to perform the stable bipolar 1S1R switching with a bipolar RS element connected. Finally, an 8 × 8 1S1R array on the flexible substrate was successfully realized. The main results of these studies are summarized below.

In Chapter 2, we report the transition of stable rectification to resistive-switching behaviors in a Ti/TiO₂/Pt MIM. The oxygen migration and localized conductive filaments play important roles in not only the resistive-switching of RRAM devices but also the rectification of oxide diodes. When the current flows through the oxygen-deficient TiO₂ filaments, current behaviors were limited by the interfaces of Schottky barrier, resulting in the diode rectifying properties. After forming at higher voltage, much stronger filaments destroy the interface Schottky barrier, giving rise to the reproducible resistive-switching. The rectification properties are stable up to 125 °C and 10³ cycles under ±3 V sweep without interference with the resistive-switching. Moreover, the current density of TiO2 MIM diodes more than 10⁴ A/cm² can be achieved, showing the satisfactory requirement of TiO₂ MIM diodes for future 1D1R RRAM applications.

In Chapter 3, a rectifying Ti/TiO₂/Pt oxide diode and a unipolar Ni/HfO₂/Pt memory element have been fabricated on flexible PI substrates using only room-temperature

processes. No significant device degradation was found at bending states. Additionally, the impact of IRESET on the programming margin of unipolar RS has been discussed. The heterogeneous TiO₂-HfO₂ 1D1R cell not only demonstrates more stable unipolar RS compared to the monolithic TiO2 1D1R cell because of the lower IRESET of the HfO2 memory element, but also effectively suppresses the sneak current. The maximum allowed array size with at least 10% read margin was predicted to exceed 512 Kb based on a simple equivalent circuit model.

In Chapter 4, a Ni/TiO₂/Ni MIM with highly nonlinear I-V characteristics has been proposed by a very simple low-temperature process. Excellent bipolar nonlinear characteristics, including current difference of 6 orders of magnitude for a voltage swing from 0 to ±2 V and a breakdown voltage larger than 4 V are demonstrated. The nonlinearity was attributed to the Schottky emission over the Ni/TiO₂ barriers. By connecting the bipolar selector and a HfO2 memory element, 1S1R exhibits robust and stable bipolar RS, and can

In Chapter 4, a Ni/TiO₂/Ni MIM with highly nonlinear I-V characteristics has been proposed by a very simple low-temperature process. Excellent bipolar nonlinear characteristics, including current difference of 6 orders of magnitude for a voltage swing from 0 to ±2 V and a breakdown voltage larger than 4 V are demonstrated. The nonlinearity was attributed to the Schottky emission over the Ni/TiO₂ barriers. By connecting the bipolar selector and a HfO2 memory element, 1S1R exhibits robust and stable bipolar RS, and can

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