The summary of the simulation results of the programmable SSCG is shown in Table 4.3. We realize the circuit with the various modulation frequencies from 30 kHz to 300 kHz and the various spread ratios from 2500 ppm to 50000 ppm. The peak-to-peak jitter at non-SSC mode is 5.6 ps. The power dissipation is 18 mW.
Table 4.3 Summary with simulation results of the programmable SSCG This work
Technology TSMC 0.13um RF
Supply Voltage 1.2V
Modulation Profile Triangle
Modulation Type Down-Spread
Output Frequency
(non-SSC) 1.25 GHz
Spread Ratios 2500 ~ 50000 ppm
Modulation Frequency 30 ~ 300 kHz Peak-to-Peak Jitter
(non-SSC) (TT) 5.6 ps
Peak Reduction 20 dB @ 30 kHz, 5000 ppm spread
Power Dissipation 18 mW
Chip Layout Area 750um×750um
Chapter 5 Conclusion
In this thesis, we realize a programmable SSCG. The circuit consists of a conventional PLL generating 1.25GHz, 8-phase clocks, a programmable triangle generator, a digital Σ∆ modulator, a MUX controller, and a programmable divider.
It is based on the fractional-N technique by using the Σ∆ modulator. The programmable SSCG achieves the spread spectrum function with triangular waveform modulation. It generates the clock with the various modulation frequencies from 30 kHz to 300 kHz and the various spread ratios from 2500 ppm to 50000 ppm. In addition, it has a variable loop bandwidth for different triangle profiles. Through modulating the multiphase output, it avoids large frequency jump in the feedback divider.
Finally, the programmable SSCG is implemented in TSMC 0.13 um 1P8M RF technology. The simulation results show that the non spreading clock has a peak-to-peak jitter of 5.6 ps, the reduction of peak energy is 20 dB at 30 kHz 5000 ppm spread, the power dissipation is 18 mW and the chip size is
750µm×750µm. This architecture does achieve various spread spectrum profiles as expected.
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