SSCG is utilized in many systems to reduce the radiated emissions. Theses systems are composed of microprocessors, ASICs, RAM, and other logic circuits.
They are usually designed to complete some operations within one clock cycle.
Because of the throughput requirement, a general method is to increase the internal or core frequency through the clock multiplication. It is often implemented by using frequency multiplying PLL. In addition, it is necessary to minimize the timing difference between the system clock and the I/O signals in the system. This is because that an excessive delay in the operation significantly reduces a system’s throughput.
One of the SSCG concerns is the clock skew [13]. If the input signal is a SSC clock and its frequency migrates from fo to (1−δ)fo, the PLL does not identically track the input clock and instantaneously update the output clock. The accumulation from the period difference results in a significant amount of the phase error. This phase error is defined as the PLL tracking skew between the input clock and its output clock. The tracking skew decreases the setup and hold margins in the corresponding interfaces. It affects the device timing margins in reading or writing data.
In General, SSC has triangle modulation profiles and contains higher-order harmonic contents than the carrier frequency. The maximum frequency change happens when the triangle profile changes the polarity of the slew rate at the corners.
Thus, in order to accurately track the SSC signal in the PLL, the closed-loop bandwidth must be large enough to pass the sufficient number of high-order harmonic contents. This closed-loop bandwidth is determined by the PLL transfer function.
With a second-order loop filter, this transfer function is defined as ( ) out( ) in( )
H s =θ s θ s and written as
2
3 2 1 2
1
1 2 1 1 2
1 ( ) ( )
( )
out CP VCO
CP VCO CP VCO
in FB
s I K s R C
H s s N C s s C C s I K I K
R C C N C R C C
θ θ
⋅ + ⋅
= = ⋅
⋅ ⋅
⋅ + ⋅ + + ⋅ +
⋅ ⋅ ⋅ ⋅ ⋅
,
(1.15) where ICP is the charge pump current, KVCO is the VCO’s gain, NFB is the divider division ratio, and C1, C2, and R are the values of the loop filter components.
However, a larger bandwidth results in diminishing the PLL stability and raises susceptibility to noise. Therefore, the bandwidth considerations of the downstream PLL must be made to accommodate the spread spectrum clock to minimize the timing problems in the system.
Chapter 2
Fractional-N Phase-Locked Loop with Σ∆ Modulator
In traditional PLL based on frequency synthesizers, division ratios in the feedback path are restricted to the integers. When a finer frequency resolution is required, the lower reference frequency results in narrow bandwidth and low switching speed. The larger division ratio also causes larger noise amplification from the reference to the synthesizer output. Recently, fractional-N synthesis techniques are widely adopted in the wireless applications. This technique overcomes the shortcomings of traditional PLL frequency synthesizers. Sigma-delta modulator (Σ∆
modulator) is the most suitable scheme for the fractional-N synthesis technique. In this chapter, we will discuss the fundamental theory of PLLs and the fractional-N mechanism.
2.1 Phase-Locked Loop Fundamentals
Today’s phase-locked loops (PLL) are preferred choices for generating stable, low-noise, and particularly tunable oscillation frequency in the communications. A basic PLL architecture we discuss is shown in Figure 2.1. It consists of a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop Filter (LF), a Voltage Controlled Oscillator (VCO), and a divider.
PFD CP LF VCO
Divider 1N Fref
Fdiv
Fout
Vctrl
Figure 2.1 Block diagram of a typical PLL
After a locking process, all the signals in the loop finally reach a steady state and the PLL operates as follows. The internal feedback signal Fdiv from the divider is compared to the external reference signal Fref by PFD. PFD serves as an error amplifier in the loop and attempts to reduce the input phase difference. It generates two messages to CP, Lead/Lag message and the phase difference between Fref and Fdiv. CP charges and discharges the loop filter according to the input phase difference and produces a control voltage Vctrl to vary VCO output frequency. VCO oscillates at a frequency that is equal to the N times the internal feedback frequency Fdiv. Finally, Fdiv is adjusted according to the synchronous input signal. Fout is
N×Fref in the steady state.
Figure 2.2 displays a block diagram of the linear model. We use mathematical analysis to determine the parameters [14]. It also provides the overall s-domain transfer function. PFD and CP have a gain of KPFD. It is the charge pump current divided by 2π . LF transfer function in the s-domain is represented as ZLF( )s . It is
usually designed as a second-order or a third-order filter. KVCO is the VCO’s gain for the phase expression. Since integration is a linear operation on the VCO’s output frequency, the output phase is also divided by a factor of N in the frequency
Figure 2.2 Block diagram of a PLL linear model
The forward gain is therefore derived as
( ) KPFD LFZ ( )s KVCO
G s = s . (2.1)
The feedback gain is
( ) 1
H s = N . (2.2)
Then, the close loop transfer function is expressed as ( ) consider a linear model charge-pump PLL and the loop filter transfer function as
( ) 1 ZLF s R
= +sC . (2.4)
We rewrite the close loop transfer function as
The natural frequencyωnand damping factorζ of the system can be derived as ,
2.2 Types of Noise Sources in PLL
By the above mathematical analysis, we now will discuss noise effects and its influence in PLL. Shown in Figure 2.3 is the PLL model with three noise sources being added. Vn1( )s is associated with PFD and CP. It is also known as the input reference noise. Vn2( )s is introduced by the loop filter. Vn3( )s is the phase noise generated by the VCO.
KVCO
Figure 2.3 Linear model of PLL with the noise sources
The equations representing the noise transfer function of Vn1( )s , Vn2( )s , low-pass property. If the input reference noise varies rapidly, the output phase will not fully track the variations. In other words, only the slowly varying input reference noise can propagate to the output. Second, the noise effect of Vn2( )s has the same property as Vn1( )s . Finally, VCO tends to accumulate its noise fluctuations and passes them to the output. Figure 2.4 shows the summary of the noise responses. In order to receive suppressed noise fluctuations in the output, a moderate loop bandwidth should be chosen. This is because that there exists a trade-off between the VCO’s noise and the input reference noise [15].
1
Figure 2.4 Frequency response of noise sources
2.3 Fractional-N Frequency Synthesis
The fractional-N frequency synthesis technique has an advantage of synthesizing non-integer multiplications between the output frequency and the reference signal. It improves the phase noise and the switching speed. Using this technique has no limited loop bandwidth as integer frequency synthesizers.
In general, the fractional-N PLL is classified into two types. One is based on the integer divider. It achieves fractional-N synthesis through averaging the divider division ratio in a long time. By switching the division ratio among two or more values, the divider divides by a non-integer number. The other is using the Σ∆
modulation concept [16]. It results in a beneficial noise shaping of the phase noise introduced by the fractional-N division. Thus, the technique provides the low phase noise and the reduced spurious impacts compared to the first type.
Figure 2.5 shows a dual-modulus prescaler introduced in the PLL [17]. It divides VCO’s output frequency by either N or N+ . Together, two synchronous counters 1 are combined to construct a variable frequency divider.
PFD CP LF VCO
Fref
Fout
A Counter
1
÷N N+ M
Counter
Figure 2.5 PLL with the dual-modulus prescaler
1
÷ +N ÷N ÷ +N 1
÷N
÷M ÷M
÷A ÷A
Figure 2.6 Dual-modulus prescaler operation mechanism
Figure 2.6 is a timing diagram of a dual-modulus prescaler. Initially, both A counter and M counter start at the same time. PLL tracks the frequency and locks at a division of N+ until A counter is ended. Then, A counter is disabled and the 1 divider jumps to N before the M counter is overflow. The process is repeated periodically. Finally, the average division ratio is obtained as
( 1) ( )
Therefore, using the PLL frequency synthesizer with the dual-modulus prescaler can obtain an average division ratio between the two dividers. However, there is a serious problem in this structure. It results in spurious frequencies in the output spectrum. Shown in Figure 2.7, a periodically sawtooth phase error is produced in PFD. The phase error from the difference of the input signals accumulates and goes back to zero. It presents a periodic behavior and generates the fractional spurs in the output spectrum. Figure 2.7 Sawtooth phase error
Figure 2.8 shows the resulting fractional spur which are typically only 20 or 30 dB below center frequency. It seriously degrades the signal purity in the output spectrum [18]. Thus, how to constrain the fractional spur is a serious subject. For this, the sigma-delta modulator (Σ∆ modulator) technique can overcome this problem. It is most suitable for the fractional-N frequency synthesis.
Center Frequency
Fractional Spurs Center
Frequency
Fractional Spurs
Figure 2.8 Spurious noise in the PLL output spectrum
2.4 Sigma-Delta Modulator
A Σ∆ modulator technique is widely used for ADC and DAC application [19].
This technique pushes the quantization noise to a higher frequency, suppresses the in-band quantization noise, and increases the signal to noise ratio (SNR).
As shown in Figure 2.9, a Σ∆ modulator has an integrator at the input and a differentiator behind a quantizer. In conventional Σ∆ modulator application, the output is followed by a low-pass filter in order to remove the high-frequency quantization noise. Because there exists a low-pass characteristic in the PLL, the out-of-band quantization noise is suppressed by higher order poles.
G
F G
F
Differentiator Quantizer
Integrator
Input Output
F F F F
Figure 2.9 Fundamental theory of Σ∆ modulator
A 1-order Σ∆ modulator is shown in Figure 2.10. Both the integrator and the differentiator are first-order and complementary. However, the 1-order Σ∆
modulator encounters an overflow problem due to the high dc gain of the integrator.
In order to solve the problem, the subtraction section in the differentiator is moved to the front of the integrator as a negative feedback system. But the transfer function is not changed. Figure 2.11 shows the improved 1-order Σ∆ modulator.
Quantizer
z−1 z−1
Integrator Differentiator
Input Output
Figure 2.10 Original structure of first-order Σ∆ modulator
Quantizer
Figure 2.11 Modified structure of first-order Σ∆ modulator
A first-order Σ∆ modulator in its digital implementation is illustrated in Figure 2.12 (a). The equivalent circuit diagram is shown in Figure 2.12 (b), where [ ]e n is the quantization noise added at the quantizer. The input signal [ ]k n is integrated to produces the signal [ ]v n . A 1-bit quantization process is accomplished by taking the most significant bit (MSB) of [ ]v n . It is represented as the accumulator overflow.
Besides the MSB of [ ]v n , the residue signal is the negative quantization error. It is then stored in the register. Therefore, the modulator with error feedback can be fully implemented with digital circuit.
z−1
Figure 2.12 First-order SDM implementation
In z-domain [20], the transfer function is written as
B z( )=K z( ) (1+ −z−1) ( )E z , (2.11) where the (1−z−1) term is a zero in the origin referred as the noise transfer function (NTF). It is known that an additional zero in the origin in the transfer function produces a slope shaper by 20 dB dec. More zeros in the origin push the quantization noise to a higher frequency. The higher-order NTF is written as (1−z−1)m , where m is the order of the modulator. In addition, from (2.11), the power spectral density (PSD) is rewritten as
Assume that 1-bit quantizer has an uniform quantization error and the power is spread over a bandwidth of f . Consequently, the PSD of the quantization error is s 1 (12fs). Thus, the second term is also represented by a general formula and written as
2.5 MASH 1-1 Sigma-Delta Modulator
For today’s fractional-N frequency synthesizers with the Σ∆ modulators, it is implemented by using the multi-stage-noise-shaping (MASH) architecture. This is because that the MASH architecture is unconditionally stable and easy for the digital implementation. In general, the second-order and the third-order Σ∆ modulator are usually adopted. Fourth-order or even higher order Σ∆ modulator are rarely adopted
oppositely. This is because the output phase noise is difficult to suppress at high frequency by a finite order of the loop filter.
As shown in Figure 2.13, a second-order MASH 1-1 modulator is formed by cascading two first-order Σ∆ modulators [21], [22]. In order to reduce the quantization noise, the quantization error from the first stage is fed into the second stage. Then, through the error cancellation mechanism, the quantization noise from the first stage is cancelled in the output. The quantization noise from the second stage is remained and shaped to a high frequency.
z−1
Figure 2.13 Second-order MASH 1-1 Σ∆ modulator
The equations of the individual first-order modulator are written as
1 1 1 noise in two stages respectively. Therefore, the output of the Σ∆ modulator is
1 1 1
Considering a PLL with a second-order MASH 1-1 Σ∆ modulator, the inherent division ratio Ndiv of the divider is
1 2 2
( ) (1 ) ( )
Ndiv =Nf z + −z− ⋅E z , (2.16) where the first term is the wanted division ratio determined by the Σ∆ modulator.
Figure 2.14 shows the digital circuit implementation. The total divider division ratio Ndiv is summed with the nominal number N and the Σ∆ modulator output
Figure 2.14 MASH 1-1 Σ∆ modulator implementation
In order to determine the effect of the Σ∆ quantization noise in the out-of-band, we consider the PLL whose divider is controlled by the Σ∆ modulator. From (2.16), we derive the PLL output frequency Fout( )z as
1 2 2
( ) ( ) (1 ) ( ) ( )
out ref ref
F z =Nf z ⋅f + −z− ⋅E z ⋅f ⋅T z , (2.17)
where the second term consists of the frequency fluctuations due to the Σ∆
quantization noise, which crosses over the closed loop transfer function of PLL, T(z).
For E2( )z being 1 (12fs), the PSD of the frequency fluctuations is calculated
To receive the phase fluctuations, we convert the frequency fluctuations to the phase fluctuations.
( )t f dtE
φ =∫ . (2.19) Employing a simple rectangular integration to represent
∫
dt in the z-domain,1
With (2.20), we obtain
2 12 2
quantization noise is plotted with second-order, third-order, and fourth-order structures respectively. Their shapes are clearly observed there.
104 105 106 107
Figure 2.15 Quantization noise of second to fourth-order Σ∆ modulator
2.6 Design Consideration for PLL Loop Bandwidth
As the prior description, the quantization noise shaped by the Σ∆ modulator is concentrated at high frequency. Here, we discuss a third-order PLL with the MASH 1-1 Σ∆ modulator. Due to the low-pass characteristics in a PLL, there exists an in-band phase noise with a positive 20 dB dec slope and an out-of-band phase noise with a negative 40 dB dec slope. So it is necessary to choose the narrow loop bandwidth in order to reduce the output phase noise. According to [23], the dynamic range of the L th-order Σ∆ modulator must be higher than the dynamic range of the synthesizer.
where fc and θrms are the noise bandwidth and the in-band phase error of the frequency synthesizer respectively. So the approximated upper bound of the loop bandwidth is obtained as
(1 2 1) 2
2
3 2 1
8 (2 )
L
c rms L PFD
f θ L f
π
+ −
< ⋅ ⋅ ⋅
, (2.24)
where θrms is the in-band phase error.
In addition, considering the SSCG based on the fractional-N technique by using the Σ∆ modulator, the PLL loop bandwidth must be wide enough. This is because that there are some distortions on the triangle modulation profile under such a narrow loop bandwidth. Therefore, to make sure that the triangle modulation profile can be preserved, the loop bandwidth must be at least one order of magnitude higher than the modulation frequency [24]. According to this rule, we can obtain the desired loop bandwidth.
Chapter 3
Programmable Spread Spectrum Clock Generator Implementation
3.1 Architecture of the Proposed Programmable SSCG
Figure 3.1 shows the block diagram of the proposed programmable SSCG. The circuit consists of an integer-N 1.25GHz 8-phase PLL, a programmable triangle generator, a Σ∆ modulator, a multiplexer (MUX) controller, and a programmable divider. Basically, the design is based on the fractional-N and the Σ∆ modulation technique. But it is different in the way that the programmable SSCG generates various spread spectrum clocks through modulating the multi-phase of the PLL output [25]. The divider in the feedback loop combining with the phase selection of the VCO output attains to a smaller division ratio. It also leads to a less frequency jump in the
output. The approach has an advantage of the low-jitter compared to the direct division modulation.
Fref
Fout
Σ∆
12 116
Pro_ fm
Pro_ S R. .
Figure 3.1 Architecture of the proposed programmable SSCG
The programmable divider produces a different clock frequency which is then fed into the programmable triangle generator. Its division ratio is related to the modulation frequency. The programmable triangle generator creates various triangle profiles. It is used to determine the modulation frequencies from 30 kHz to 300 kHz and the spread ratios from 2500 ppm to 50000 ppm. The Σ∆ modulator shapes the noise to a higher frequency. Furthermore, the smoothing effect of the PLL loop results in a continuous frequency modulation from the discrete staircase output of the programmable triangle generator. The MUX controller receives the modulation signal from the Σ∆ modulator and controls the MUX to select a suitable clock phase for the divider. In addition, it is necessary to have a tunable loop bandwidth according to the different modulation frequency in the programmable SSCG.
Phase Frequency Detector
Figure 3.2 (a) is a phase frequency detector (PFD). It is composed of two D flip-flops (DFFs) and a NOR gate. The DFFs are true single phase clock (TSPC) type DFFs as shown in Figure 3.2(b) [26]. Compared with the conventional PFD, the PFD with TSPC DFFs overcomes the speed limitation and reduces the dead zone.
CLK Figure 3.2 Circuit schematic of (a) PFD, (b) TSPC DFF
Figure 3.3 shows the timing diagram. If the input clocks, Fref and Fdiv, are in-phase, both UP and DOWN pulses are produced in a same short period of time. If there is a phase difference between the input clocks, the difference between the widths of UP and DN pulses is proportional to the input phase difference.
Fref
Figure 3.3 PFD timing diagram
Programmable Charge Pump
The proposed programmable charge pump is illustrated in Figure 3.4. The biasing current mirror based on a digital-to-analog converter (DAC) technique is illustrated in Figure 3.5 [27]. The programmable charge pump converts the phase difference of the input clocks to a voltage signal to control VCO. It is composed of two current sources, four switches, a unit-gain buffer, and a programmable biasing circuit. The charged and discharged currents are programmed by a 2-bit control word.
The unit-gain buffer is used to clamp the terminal voltage of the current sources when there is no current pumping into the loop filter. In such way, the voltage glitch due to charge sharing is eliminated.
Vctrl
Figure 3.4 Programmable charge pump circuit
UPb
b1 DN b0
1 2
Vctrl
Figure 3.5 Programmable biasing current mirror
Programmable Loop Filter
According to the prior chapter, it is known that using a narrow loop bandwidth reduces the output phase noise generated from the Σ∆ modulator. But there occurs some distortions on the triangle modulation profile. To compromise both requirements, one must be careful in determining the loop bandwidth of the system. Here, in order to achieve a finer triangle modulation profile and a smaller output phase noise from the Σ∆ modulator, we design a programmable loop bandwidth. Figure 3.6 shows a second-order loop filter where R2 is programmed by a 2-bit control word.
Icp
Vctrl
C1 C2
R2
Figure 3.6 Schematic of the second-order loop filter
This transfer function is written as
Figure 3.7 shows the Bode plot of the open loop gain in PLL with a second-order loop filter. Here, we must design the sufficient phase margin φp to ensure the maximum stability.
1
Figure 3.7 Bode plot of PLL with the second-order loop filter
According to [28], we calculate the equations to recide the passive component VCO’s gain, and the divider division ratio respectively.
In addition, in order to effectively suppress the out-of-band quantization noise from the Σ∆ modulator at higher frequency, a third pole composed of R3 and C3 is added to the loop filter. Figure 3.8 shows this circuit schematic diagram.
Icp
Figure 3.8 Schematic of the third-order loop filter
Figure 3.8 Schematic of the third-order loop filter