As the prior description, the quantization noise shaped by the Σ∆ modulator is concentrated at high frequency. Here, we discuss a third-order PLL with the MASH 1-1 Σ∆ modulator. Due to the low-pass characteristics in a PLL, there exists an in-band phase noise with a positive 20 dB dec slope and an out-of-band phase noise with a negative 40 dB dec slope. So it is necessary to choose the narrow loop bandwidth in order to reduce the output phase noise. According to [23], the dynamic range of the L th-order Σ∆ modulator must be higher than the dynamic range of the synthesizer.
where fc and θrms are the noise bandwidth and the in-band phase error of the frequency synthesizer respectively. So the approximated upper bound of the loop bandwidth is obtained as
(1 2 1) 2
2
3 2 1
8 (2 )
L
c rms L PFD
f θ L f
π
+ −
< ⋅ ⋅ ⋅
, (2.24)
where θrms is the in-band phase error.
In addition, considering the SSCG based on the fractional-N technique by using the Σ∆ modulator, the PLL loop bandwidth must be wide enough. This is because that there are some distortions on the triangle modulation profile under such a narrow loop bandwidth. Therefore, to make sure that the triangle modulation profile can be preserved, the loop bandwidth must be at least one order of magnitude higher than the modulation frequency [24]. According to this rule, we can obtain the desired loop bandwidth.
Chapter 3
Programmable Spread Spectrum Clock Generator Implementation
3.1 Architecture of the Proposed Programmable SSCG
Figure 3.1 shows the block diagram of the proposed programmable SSCG. The circuit consists of an integer-N 1.25GHz 8-phase PLL, a programmable triangle generator, a Σ∆ modulator, a multiplexer (MUX) controller, and a programmable divider. Basically, the design is based on the fractional-N and the Σ∆ modulation technique. But it is different in the way that the programmable SSCG generates various spread spectrum clocks through modulating the multi-phase of the PLL output [25]. The divider in the feedback loop combining with the phase selection of the VCO output attains to a smaller division ratio. It also leads to a less frequency jump in the
output. The approach has an advantage of the low-jitter compared to the direct division modulation.
Fref
Fout
Σ∆
12 116
Pro_ fm
Pro_ S R. .
Figure 3.1 Architecture of the proposed programmable SSCG
The programmable divider produces a different clock frequency which is then fed into the programmable triangle generator. Its division ratio is related to the modulation frequency. The programmable triangle generator creates various triangle profiles. It is used to determine the modulation frequencies from 30 kHz to 300 kHz and the spread ratios from 2500 ppm to 50000 ppm. The Σ∆ modulator shapes the noise to a higher frequency. Furthermore, the smoothing effect of the PLL loop results in a continuous frequency modulation from the discrete staircase output of the programmable triangle generator. The MUX controller receives the modulation signal from the Σ∆ modulator and controls the MUX to select a suitable clock phase for the divider. In addition, it is necessary to have a tunable loop bandwidth according to the different modulation frequency in the programmable SSCG.
Phase Frequency Detector
Figure 3.2 (a) is a phase frequency detector (PFD). It is composed of two D flip-flops (DFFs) and a NOR gate. The DFFs are true single phase clock (TSPC) type DFFs as shown in Figure 3.2(b) [26]. Compared with the conventional PFD, the PFD with TSPC DFFs overcomes the speed limitation and reduces the dead zone.
CLK Figure 3.2 Circuit schematic of (a) PFD, (b) TSPC DFF
Figure 3.3 shows the timing diagram. If the input clocks, Fref and Fdiv, are in-phase, both UP and DOWN pulses are produced in a same short period of time. If there is a phase difference between the input clocks, the difference between the widths of UP and DN pulses is proportional to the input phase difference.
Fref
Figure 3.3 PFD timing diagram
Programmable Charge Pump
The proposed programmable charge pump is illustrated in Figure 3.4. The biasing current mirror based on a digital-to-analog converter (DAC) technique is illustrated in Figure 3.5 [27]. The programmable charge pump converts the phase difference of the input clocks to a voltage signal to control VCO. It is composed of two current sources, four switches, a unit-gain buffer, and a programmable biasing circuit. The charged and discharged currents are programmed by a 2-bit control word.
The unit-gain buffer is used to clamp the terminal voltage of the current sources when there is no current pumping into the loop filter. In such way, the voltage glitch due to charge sharing is eliminated.
Vctrl
Figure 3.4 Programmable charge pump circuit
UPb
b1 DN b0
1 2
Vctrl
Figure 3.5 Programmable biasing current mirror
Programmable Loop Filter
According to the prior chapter, it is known that using a narrow loop bandwidth reduces the output phase noise generated from the Σ∆ modulator. But there occurs some distortions on the triangle modulation profile. To compromise both requirements, one must be careful in determining the loop bandwidth of the system. Here, in order to achieve a finer triangle modulation profile and a smaller output phase noise from the Σ∆ modulator, we design a programmable loop bandwidth. Figure 3.6 shows a second-order loop filter where R2 is programmed by a 2-bit control word.
Icp
Vctrl
C1 C2
R2
Figure 3.6 Schematic of the second-order loop filter
This transfer function is written as
Figure 3.7 shows the Bode plot of the open loop gain in PLL with a second-order loop filter. Here, we must design the sufficient phase margin φp to ensure the maximum stability.
1
Figure 3.7 Bode plot of PLL with the second-order loop filter
According to [28], we calculate the equations to recide the passive component VCO’s gain, and the divider division ratio respectively.
In addition, in order to effectively suppress the out-of-band quantization noise from the Σ∆ modulator at higher frequency, a third pole composed of R3 and C3 is added to the loop filter. Figure 3.8 shows this circuit schematic diagram.
Icp
Figure 3.8 Schematic of the third-order loop filter
Thus, the transfer function is
2
We analyze the relationship between the third pole and the added attenuation. It is used as the design criterion in determining the third pole.
2
Voltage Controlled Oscillator
In a conventional ring oscillator, the oscillation frequency is decided by a delay time of the delay element. The delay time can not be smaller than a single inverter delay. Therefore, the maximum frequency of the VCO is limited. To solve this frequency limitation problem, a technique using a negative skewed delay scheme has
been proposed. Figure 3.9 shows the VCO structure. It is composed of four-stage fully differential delay cells and dual-delay paths. With the negative skewed delay scheme, it decreases the unit delay time. As a result, a higher operation frequency is obtained [29].
Figure 3.9 Four-stage ring oscillator with dual-delay paths
Figure 3.10 is a four-input differential delay element. When Vctrl is low, the latch becomes weak and the output driving current from the PMOS increases.
Therefore, the state is changed easily and the delay time is reduced. Oppositely, when Vctrl is high, the latch becomes strong. It resists the voltage switching in the differential delay cell and the delay time increases. Consequently, with the normal delay paths and the negative skewed delay paths simultaneously, it achieves a higher oscillation frequency and obtains a wider tuning range.
vctrl
in1 in1
in2 in2
out out
Figure 3.10 Four-input differential delay cell
Programmable Triangle Generator
The programmable triangle generator is designed to create a different triangle profiles. It determines the modulation frequencies from 30 kHz to 300 kHz and the spread ratios from 2500 ppm to 50000 ppm. Figure 3.11 is the proposed programmable triangle generator including an accumulator and a counter. It generates the triangle waveform with discrete staircases for the Σ∆ modulator. Through the different clock frequency of CLK_tri from the programmable divider, it generates different clock cycles of Sel at a fixed count number of the counter. Thus, the various modulation frequencies are produced and illustrated in Figure 3.12 (a). In addition, the programming signal Pro_S R. . decides the frequency deviation. As illustrated in Figure 3.12 (b), it is accumulated increasingly or decreasingly along with
_tri
CLK until Sel changes state. Therefore, by programming CLK_tri and _S R. .
Pro , we obtain the desired triangle profile.
_S R. .
Pro
_tri CLK Sel
Figure 3.11 Scheme of the programmable triangle generator
_S R. . 1 Figure 3.12 Difference discrete staircases of the triangle profile
MASH 1-1 Sigma-Delta Modulator
As described in Chapter 3, the Σ∆ modulator implemented in the PLL provides the low phase noise and reduces the spurious impact. It overcomes the shortcomings in traditional PLL frequency synthesizers. In addition, the MASH architecture is unconditionally stable and easy for the digital implementation.
Shown in Figure 3.13 is the digital implementation of a modified second-order
Figure 3.13 Digital implementation of MASH 1-1 Σ∆ modulator
The transfer function is written as
2 1 2
( ) ( ) (1 ) 2( )
Y z = f z ⋅z− + −z− ⋅E z , (3.7) where f z is the wanted output frequency and ( ) E2( )z is the quantization noise from the second stage. (3.7) shows that the first term includes the delay of z−2 and the second term is the same as (2.15). It has the output signal delays for two clock cycles. However, it does not influence the noise-shaping behavior of the Σ∆
quantization noise.
Multiplexer Controller
Figure 3.14 shows the multiplexer (MUX) controller. It includes an accumulator and a decoder. The MUX controller is placed between the MASH 1-1 Σ∆ modulator and the MUX. It receives the modulation signals from the Σ∆ modulator and transfers them to one-hot code. Then, MUX controller controls the MUX for the phase selection. Table 3.1 shows the output state of the Σ∆ modulator and the corresponding behavior with the phase selection. It executes to rotate right or left one phase in the MUX.
SDM
output Mux
Control 2
Decoder 3
Accumulator
D Q
+
Figure 3.14 Scheme of the multiplexer controller
Table 3.1 Output state table of the Σ∆ modulator SDM
Output
Shift
Phase Shift Type 11 1 Shift right 1 phase
00 0 Hold
01 -1 Shift left 1 phase 10 -2 Shift left 2 phase
Through the transformation of the decoder, the output signal of the accumulator is decoded to an one-hot code. Shown in Table 3.2 is the relationship between the 3-bit output signal of the accumulator and the MUX control signals. The MUX control signals correspond to the multiphase output of the VCO respectively.
According to the different signal from the Σ∆ modulator, we obtain the desired MUX control signal and the suitable phase clock in the MUX.
Table 3.2 Relationship between accumulator output and MUX control signals
Mux Control Signals Accumulator
Output
S1 S2 S3 S4 S5 S6 S7 S8
000 1 0 0 0 0 0 0 0
001 0 1 0 0 0 0 0 0
010 0 0 1 0 0 0 0 0
011 0 0 0 1 0 0 0 0
100 0 0 0 0 1 0 0 0
101 0 0 0 0 0 1 0 0
110 0 0 0 0 0 0 1 0
111 0 0 0 0 0 0 0 1
Multiplexer
Through receiving the modulation signals from the Σ∆ modulator, the MUX selects the suitable phase clock for the divider. Here, the 8-to-1 MUX in our design is composed of two 4-to-1 MUX and a 2-to-1 MUX and shown in Figure 3.15 [26]. The extra PMOS transistors in the phase clock input is to precharge the internal node to a high level when the phase clock is low. Therefore, it has a benefit of reducing the charge sharing effect and alleviating the clock jitter.
Furthermore, with different phase selection sequences, it realizes different frequency division ratios in PLL. Moreover, the spreading clock is obtained by modulating the multiphase clock output in the programmable SSCG.
S1
Out
P1
S4
P4
S3
P3
S2
P2
S1
Out
P1
S2
P2
(a) 4-to-1 MUX (b) 2-to-1 MUX Figure 3.15 Circuit scheme of the (a) 4-to-1 MUX, (b) 2-to-1 MUX
Programmable Divider
The programmable divider produces clocks of different frequency to be fed into the programmable triangle generator. Its division ratio is determined by an assigned program to determine the modulation frequency. Shown in Figure 3.16 is the architecture of the 6-bit programmable frequency divider. It includes a 6-bit counter, an end-of-count (EOC) detector, and a reload circuit [30].
Reload Circuit
Figure 3.16 Architecture of the 6-bit programmable frequency divider
The circuit principle is assumed as a countdown counter. First, a certain preset number is loaded in the counter and the counter starts counting. Once the counter reaches the terminal count state 000010 , the EOC detector delivers a Reload signal to the reload circuit. Then, the counter is commanded to set the initial value N and starts counting again. Therefore, the relationship between the input clock frequency and the output clock frequency is ftri = fin N. With 6 counter stages, the frequency division ratio N can be varied from 2 to 26− . 1
Chapter 4
Simulation Results and Layout
The programmable SSCG implementation is based on a fractional-N technique by using a Σ∆ modulation. There are some design issues to be considered such as the system stability problem, the PLL responses, and the loop bandwidth design, etc.
In this chapter, we verify the spread spectrum clocking behavior by MATLAB simulation tool and the circuit simulation by HSPICE simulation tool. Finally, we show the global chip layout and the test environment.
4.1 Programmable SSCG Behavior Simulation
In order to verify the behavior and the function of the programmable SSCG, we
use the MATLAB simulation tool to analyze. Figure 4.1 shows the SIMULINK model.
It is based on a charge-pump PLL with a third-order filter. The programmable triangle generator, MASH 1-1 Σ∆ modulation, and MUX controller are also added to modulate the output clocks. We obtain the various triangle modulation clocks through the 6-bit programming modulation frequency and the 5-bit programming spread ratio.
This system is simulated as far as the circuit-level is concerned.
[0 : 5]
Pro_ fm
[0 : 4]
Pro_ S R. .
[0 : 5]
Pro_ fm
[0 : 4]
Pro_ S R. .
Figure 4.1 SIMULINK model of the programmable SSCG
In addition, we extract from the post-layout simulation results of each fundamental element with corner model variations and arrange them in Table 4.1.
Including the data of an inverter delay, a NOR delay, and a DFF delay, etc, are added in this SIMULINK model. Thus, the more precise results can be obtained by the
Table 4.1 Post-layout simulation delay time of each fundamental element
SS TT FF
Inverter, NAND, NOR… 50ps 40ps 32ps
XOR 30ps 27ps 25ps
DFF 160ps 125ps 115ps
SUM 1160ps 930ps 750ps
Full Adder
(12bit) CARRY OUT 1230ps 990ps 800ps
Half Adder SUM 23ps 19ps 16ps
According to Table 4.1, the behavior simulation results with similar corner model variations in time-domain are respectively shown in Figure 4.2 (a), (b), (c).
They all exhibit the cases that the frequency is down spreading with a spread ratio of 5000 ppm and a modulation frequency of 30 kHz.
SSC with 5000ppm 30kHz triangle profile TT Corner
Time
Frequency
SSC with 5000ppm 30kHz triangle profile TT Corner
SSC with 5000ppm 30kHz triangle profile SSC with 5000ppm
30kHz triangle profile TT Corner
Time
Frequency
(a) TT corner
SSC with 5000ppm
Figure 4.2 Behavior simulation of SSC at the difference corners
We analyze this design in FFT with the spread ratio of 5000 ppm and the modulation frequency of 30 kHz. The compared results between SSC mode and non-SSC mode are shown Figure 4.3. The results display that there is about 20 dB reduction of the peak energy.
Attenuation Attenuation
Figure 4.3 FFT of the programmable SSCG at SSC mode and non-SSC mode
4.2 Programmable SSCG Circuit-Level Simulation
In order to receive the more precise simulation result, we use the HSPICE simulation tool to analyze. Figure 4.4 shows the post-layout simulation result of the VCO with corner model variations. The VCO’s gain is about 680 MHz V at 1.25
GHz .
TT
SS FS SF FF
Control Voltage
Frequency
TT
SS FS TT SF FF
SS FS SF FF
Control Voltage
Frequency
Figure 4.4 Characteristic curves of VCO with corner model variations
The output eye diagram at non-SSC mode with five corner model variations are shown in Figure 4.5 respectively. The simulation results of the jitter are shown in Table 4.2.
(a) TT corner (b) FF corner
(c) FS corner (d) SF corner
(e) SS corner
Figure 4.5 Output eye diagram at non-SSC mode
Table 4.2 Jitter of the Output eye diagram at non-SSC mode
TT SS FF SF FS
Jitter(p-p) 5.6ps 7.75ps 2.9ps 7.2ps 3.6ps
In order to verify the function in SSC mode, we select several cases for the simulation. We can see various frequency-modulation results with triangular waveform in time domain and frequency domain obviously.
First, Figure 4.6 shows the control voltage variation in SSC mode with a spread ratio of 32500 ppm and a modulation frequency of 30 kHz. Figure 4.7 shows its spectrum with spreading.
32500ppm
30kHz 32500ppm
30kHz
Figure 4.6 Control voltage of SSCG with 32500 ppm and 30 kHz spread
32500 ppm 32500 ppm
Figure 4.7 FFT of SSCG with 32500 ppm and 30 kHz spread
Second, Figure 4.8 shows the control voltage variation in SSC mode with a spread ratio of 50000 ppm and a modulation frequency of 30 kHz. Figure 4.9 shows its spectrum with spreading.
50000ppm
30kHz 50000ppm
30kHz
Figure 4.8 Control voltage of SSCG with 50000 ppm and 30 kHz spread
50000 ppm 50000 ppm
Figure 4.9 FFT of SSCG with 50000 ppm and 30 kHz spread
Third, Figure 4.10 shows the control voltage variation in SSC mode with a spread ratio of 5000 ppm and a modulation frequency of 150 kHz. Figure 4.11 shows its spectrum with spreading.
150kHz 5000ppm
150kHz 5000ppm
Figure 4.10 Control voltage of SSCG with 5000 ppm and 150 kHz spread
5000 ppm 5000 ppm
Figure 4.11 FFT of SSCG with 5000 ppm and 150 kHz spread
Finally, Figure 4.12 shows the control voltage variation in SSC mode with a spread ratio of 5000 ppm and a modulation frequency of 300 kHz. Figure 4.13 shows its spectrum with spreading.
300kHz 5000ppm
300kHz 5000ppm
Figure 4.12 Control voltage of SSCG with 5000 ppm and 300 kHz spread
5000 ppm 5000 ppm
Figure 4.13 FFT of SSCG with 5000 ppm and 300 kHz spread
According to the previous simulation results, we illustrate a graph for comparison. Shown in Figure 4.14 is the EMI attenuation versus the different spread ratio and the different modulation frequency. Here, the relationship between EMI attenuation and theses parameters corresponds with (1.4) as expected. However, the simulation curve is under the ideal curve from 1.3 dB to 3 dB. This is because the use of the modulation of PLL feedback loop and the SSCG jitter influence.
Figure 4.14 EMI attenuation versus the spread ratios and the modulation frequency
4.3 Layout and Measurement Setup
A chip layout of the proposed programmable SSCG is shown in Figure 4.15. It consists of a conventional PLL and the proposed programmable triangle modulation circuit. The rest area is filled up with decouple capacitance to bypass power noise.
This chip is implemented in TSMC 0.13um RF 1P8M technology and the chip size is 750µm×750µm.
3dB
Spread Ratios Modulation Frequency
Attenuation
Attenuation
1.3dB 3dB
Spread Ratios Modulation Frequency
Attenuation
Attenuation
1.3dB
SEL Gndd
Figure 4.15 Chip layout of the programmable SSCG
The test environment is shown in Figure 4.16. The power is divided into analog power and digital power in order to avoid interfering with each other. The test pin Sel is probed by a logic analyzer and observed the modulation frequency of SSC. A spectrum analyzer and an oscilloscope are used to obtain some information with the SSCG output signals including the jitter measurement, the spectrum, and the spread ratio, etc. Finally, with programming the 3-bit control word, the programmable SSCG generates eight types of spreading spectrum clocks.
HP E3610A Analog Power Supply
Agilent E4440A Agilent E4440A Spectrum Analyzer
Agilent 86100B Wide Bandwidth Oscilloscope
Agilent 16702B Agilent 16702B Logic analyzer
HP 8133A Pulse Data Generator
HP E3610A Digital Power Supply
Spread Ratio and Modulation Frequency
Programming Spread Ratio and Modulation Frequency
Programming PCB
Figure 4.16 Measurement setup
4.4 Summary and Comparison
The summary of the simulation results of the programmable SSCG is shown in Table 4.3. We realize the circuit with the various modulation frequencies from 30 kHz to 300 kHz and the various spread ratios from 2500 ppm to 50000 ppm. The peak-to-peak jitter at non-SSC mode is 5.6 ps. The power dissipation is 18 mW.
Table 4.3 Summary with simulation results of the programmable SSCG This work
Technology TSMC 0.13um RF
Supply Voltage 1.2V
Modulation Profile Triangle
Modulation Type Down-Spread
Modulation Type Down-Spread