可程式化展頻時脈產生器

國 立 交 通 大 學

電機與控制工程研究所

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可程式化展頻時脈產生器

Programmable Spread Spectrum Clock Generator

研 究 生：程議賢

指導教授：蘇朝琴 教授

可程式化展頻時脈產生器

Programmable Spread Spectrum Clock Generator

研 究 生：程議賢 Student : YiSian Cheng

指導教授：蘇朝琴 教授 Advisor : ChauChin Su

國 立 交 通 大 學

電機與控制工程研究所

碩士論文

A Thesis

Submitted to Department of Electrical and Control Engineering College of Electrical Engineering and Computer Science

National Chiao Tung University in partial Fulfillment of the Requirements

for the Degree of Master

in

Electrical and Control Engineering January 2008

Hsinchu, Taiwan, Republic of China

可程式化展頻時脈產生器

研究生 : 程議賢 指導教授 : 蘇朝琴 教授

國立交通大學電機與控制工程研究所

摘 要

在電子系統中，伴隨著高頻時脈的需要帶來了嚴重的電磁干擾(EMI)效應。而近年來如 展頻時脈技術的發展已經能有效地解決這問題。

本論文提出一個可程式化展頻時脈產生器。它是利用三角積分調變器(Σ∆ modulat modulator) modulat modulator)or)or) 的非整數頻率合成(fractionalfractionalfractionalfractional----N)N)N)N)技術來設計，且達到一三角波調變的展頻功能。此外， 在時脈展頻上它可以產生調變頻率從 30 khz 至 300 khz 之間變化; 展頻比例從 2500 ppm 至 50000 ppm 之間變化。 可程式化展頻時脈產生器是使用台積電 0.13µm 1P8M RF 製程來實現。經模擬結果顯 示非展頻情況下的時脈抖動為 5.6 ps；功率消耗為 18 毫瓦；晶片面積約為750µm×750µm。 而各個時脈展頻皆達到我們所期許的展頻行為。 關鍵字 關鍵字 關鍵字 關鍵字: : : : 鎖相迴路鎖相迴路鎖相迴路鎖相迴路、、、、非整數非整數非整數非整數頻率合成器頻率合成器、頻率合成器頻率合成器、、、展頻時脈產生器展頻時脈產生器展頻時脈產生器展頻時脈產生器、、、、三角積分調變器三角積分調變器三角積分調變器三角積分調變器

Student: Yi Sian Cheng Advisor: Chau Chin Su

Department of Electrical and Control Engineering

National Chiao Tung University

Abstract

In electronic systems, along with a high frequency of clock often comes series

electromagnetic interference (EMI) effects. A technique, referred to as spread spectrum clock generation, is recently proposed to solve effectively.

In this thesis, we propose a programmable spread spectrum clock generator (SSCG). It is based on the fractional-N technique using the Σ∆ modulator. The programmable SSCG achieves the spread spectrum function with triangular waveform modulation. In addition, it generates the clock with the various modulation frequencies from 30 kHz to 300 kHz and the various spread ratios from 2500 ppm to 50000 ppm.

The programmable SSCG is implemented in TSMC 0.13 um 1P8M RF technology. The simulation results show that the non spreading clock has a peak-to-peak jitter of 5.6 ps, the power dissipation is 18 mW and the chip size is 750µm×750µm. This architecture does achieve various spread spectrum profiles as expected.

Keyword: phase-locked loop, fractional-N frequency synthesizer, spread spectrum clock generator, sigma-delta modulator

我首先要感謝我的指導教授 蘇朝琴老師，謝謝老師在學業研究上的指導，讓我這 兩年收穫良多。 另外，實驗室裡的大家也是我碩士生活的支持。鴻文、丸子、仁乾、煜輝、盈杰幾位 學長；小馬、小潘潘、方董、村鑫、教主、祥哥、存遠、忠傑、汝敏等等一起打拚的伙伴 們；還有已畢業的學長及很多實驗室裡學弟妹們，除了對於在專業領域上的討論，還有更 多的是日常生活的互相打氣，在 918 實驗室的研究生活裡，能和你們在一起，總是充滿了 活力。 最後要感謝我的家人，一直以來提供了我無慮的求學環境，也謝謝我的女友美嘉，至 終都能給予最大的體諒與支持，我愛你們。 感謝大家。未來我會繼續加油、繼續努力。 程議賢 2008．1．10

List of Contents

List of Contents ...V

List of Tables...VII

List of Figures... VIII

Chapter 1 ...1

Introduction...1

1.1 MOTIVATION…..………...………...……….………….……1

1.2 SPREAD SPECTRUM FUNDAMENTALS…….……….….………3

1.3EMIATTENUATION FOR SPREAD SPECTRUM CLOCK…….….……..………6

1.4 IMPLEMENTATION OF SSCG………..…..……….………7

1.5 IMPACTS OF SSC ON TIMING…….……….…….………….………9

1.6CONSIDERATIONS FOR USING SPREAD SPECTRUM CLOCKING………12

Chapter 2 ...14

Fractional-N Phase-Locked Loop with

Σ∆

Modulator ...14

2.1 FPHASE-LOCKED LOOP FUNDAMENTALS.……..………15

2.2TYPES OF NOISE SOURCES IN PLL…….……..…….….………17

2.3FRACTIONAL-NFREQUENCY SYNTHESIS……….………..19

2.4SIGMA-DELTA MODULATOR…...………21

2.5MASH1-1SIGMA-DELTA MODULATOR…...………...…….…..24

2.6DESIGN CONSIDERATION FOR PLLLOOP BANDWIDTH…….…………....…….28

Chapter 3 ...30

Programmable Spread Spectrum Clock Generator Implementation30

3.1ARCHITECTURE OF THE PROPOSED PROGRAMMABLE SSCG…….…….……....30

Simulation Results and Layout...44

4.1PROGRAMMABLE SSCGBEHAVIOR SIMULATION………....…………..44

4.2PROGRAMMABLE SSCGCIRCUIT-LEVEL SIMULATION…………....…………..48

4.3LAYOUT AND MEASUREMENT SETUP…….………...…………..53

4.4SUMMARY AND COMPARISON……..………...…………..55

Chapter 5 ...57

Conclusion ...57

List of Tables

Table 3.1 Output state table of the Σ∆ modulator……..……….41 Table 3.2 Relationship between accumulator output and MUX control signals…….41 Table 4.1 Post-layout simulation delay time of each fundamental element….……..46 Table 4.2 Jitter of the Output eye diagram at non-SSC mode……….………50 Table 4.3 Summary with simulation results of the programmable SSCG…….….…56

List of Figures

Figure 1.1: Spread fundamental frequency comparison……..…………..………3

Figure 1.2: Frequency-modulated signal at (a) time domain, (b) frequency domain….4 Figure 1.3:β effects of the frequency-modulated signal...………. 5

Figure 1.4: Decrement of attenuation without/with respect to jitter….………... 7

Figure 1.5: Three types of SSCGs implementation……....………. 9

Figure 1.6: Spread spectrum clock at time domain……..….……….. 9

Figure 1.7: Graphical representation of cycle-to-cycle jitter……….…………. 10

Figure 1.8: Graphical representation of long-term jitter………. 11

Figure 2.1: Block diagram of a typical PLL………15

Figure 2.2: Block diagram of a PLL linear model .………...………16

Figure 2.3: Linear model of PLL with the noise sources……..………..………….. 17

Figure 2.4: Frequency response of noise sources……..……….………. 18

Figure 2.5: PLL with the dual-modulus prescaler………..……….…………... 19

Figure 2.6: Dual-modulus prescaler operation mechanism……...……….…………. 20

Figure 2.7: Sawtooth phase error……….………20

Figure 2.8: Spurious noise in the PLL output spectrum…….……….…………21

Figure 2.9: Fundamental theory of Σ∆ modulator………..…………. 22

Figure 2.10: Original structure of first-order Σ∆ modulator….……..………. 22

Figure 2.11: Modified structure of first-order Σ∆ modulator…….……….. 23

Figure 2.12: First-order SDM implementation………...…...……….. 23

Figure 2.13: Second-order MASH 1-1 Σ∆ modulator…....……….. 25

Figure 2.14: MASH 1-1 Σ∆ modulator implementation………..……..………….. 26

Figure 2.15: Quantization noise of second to fourth-order Σ∆ modulator……….. 28

Figure 3.1: Architecture of the proposed programmable SSCG…………..……….. 31

Figure 3.2: Circuit schematic of (a) PFD, (b) TSPC DFF……….………...……….. 32

Figure 3.3: PFD timing diagram………..………... 32

Figure 3.4: Programmable charge pump circuit...……….. 33

Figure 3.5: Programmable biasing current mirror…….………. 34

Figure 3.6: Schematic of the second-order loop filter…..………. 34

Figure 3.7: Bode plot of PLL with the second-order loop filter.…..…….…………35

Figure 3.8: Schematic of the third-order loop filter…..………... 36

Figure 3.9: Four-stage ring oscillator with dual-delay paths………..……... 37

Figure 3.10: Four-input differential delay cell……….……….. 37

Figure 3.12: Difference discrete staircases of the triangle profile….….………39 Figure 3.13: Digital implementation of MASH 1-1 Σ∆ modulator………. 39 Figure 3.14: Scheme of the multiplexer controller…...………..………... 40 Figure 3.15: Circuit scheme of the (a) 4-to-1 MUX, (b) 2-to-1 MUX……..………. 42 Figure 3.16: Architecture of the 6-bit programmable frequency divider…..….……43 Figure 4.1: SIMULINK model of the programmable SSCG system….………45 Figure 4.2: Behavior simulation of SSC at the difference corners…..…...…………47 Figure 4.3: FFT of the programmable SSCG at SSC mode and non-SSC mode…... 48 Figure 4.4: Characteristic curves of VCO with corner model variations….……..…48 Figure 4.5: Output eye diagram at non-SSC mode….….………. 49 Figure 4.6: Control voltage of SSCG with 32500 ppm and 30 kHz spread…...……50 Figure 4.7: FFT of SSCG with 32500 ppm and 30 kHz spread….…..………. 50 Figure 4.8: Control voltage of SSCG with 50000 ppm and 30 kHz spread…..….…51 Figure 4.9: FFT of SSCG with 50000 ppm and 30 kHz spread….………51 Figure 4.10: Control voltage of SSCG with 5000 ppm and 150 kHz spread….…... 51 Figure 4.11: FFT of SSCG with 5000 ppm and 150 kHz spread….………. 52 Figure 4.12: Control voltage of SSCG with 5000 ppm and 300 kHz spread….……52 Figure 4.13: FFT of SSCG with 5000 ppm and 300 kHz spread…...………... 52 Figure 4.14: EMI attenuation versus the spread ratio and the modulation frequency..53 Figure 4.15: Chip layout of the programmable SSCG…..……..………54 Figure 4.16: Measurement setup…...…..……….………55

Chapter 1

Introduction

1.1 Motivation

In today’s electronic products, a higher operation frequency is required to obtain a greater performance and throughput. For instance, the clock frequency in personal computers (PCs) reaches several gigahertz. However, along with a high frequency often comes series electromagnetic interference (EMI) effects. Clock signals or any signals derived from the clock like data and address buses radiate electromagnetic noise and cause the larger interference for the other devices.

To solve this problem effectively, a lot of EMI reduction techniques have been developed. They are divided into two classifications. One is to enclose the EMI radiations from emission. It includes the use of the Printed Circuit Broads (PCB) layout techniques, metal shielding, and passive components. However, it increases area and cost overhead. The other is to reduce the EMI at the source. It adopts a dithering clock oscillation technique such as Spread Spectrum Clock Generation

(SSCG) [1]. This approach generates a clock signal whose frequency is modulated within a certain frequency range. Similarly, the peak spectral energy of the clock signal in the spectrum is effectively reduced. Therefore, the dithering clock oscillation technique is widely used in electronic systems.

This thesis implements a programmable SSCG using fractional-N technique with sigma-delta modulator. It comprises six chapters summarized as below.

Chapter 1 introduces the motivation and the organization. It also discusses the fundamental theory of spread spectrum clock (SSC). That includes the basic properties, the relationship between the EMI attenuation and various parameters of SSC in the frequency domain, and the timing impacts in the clock signal. In addition, we also take a brief summary with various solutions used for the EMI reduction.

In Chapter 2, a frequency synthesizer is introduced. It includes the PLL theory and the fractional-N mechanism. Furthermore, the sigma-delta modulator concepts are also described here.

In Chapter 3, we realize the programmable spread spectrum clock generator. It controls the multiphase output of the VCO for the frequency modulation. The entire circuit consists of a conventional PLL, a programmable triangle generator, a second-order MASH 1-1 sigma-delta modulator, and a multiplexer controller.

In Chapter 4, we show the simulation results including the behavior simulation and the post-layout circuit-level simulation. Finally, the conclusion is described in Chapter 5.

1.2 Spread Spectrum Fundamentals

Figure 1.1 shows a spectral energy distribution of SSC [2]. Instead of a constant frequency, SSC modulates the clock frequency along a predetermined profile. Through spreading the clock frequency slightly, the spectral energy in the spectrum is spread out. The higher order harmonics have similar characteristics as well. The spread amounts and the attenuations are proportional to the order of the harmonic frequency.

Non-SSC SSC

Non-SSC SSC

Figure 1.1 Spread fundamental frequency comparison

To comprehend the spread spectrum with the frequency modulation, we consider a carrier signal modulated by another sinusoidal signal in frequency modulation as

(

)

[ ]

c c m

m f

A(t)= A cos 2 f t + sin 2 f t f

π ∆ π

⋅ . (1.1)

This is a cosine waveform with an amplitude of A , and a carrier frequency of _c

c

f . Its instantaneous frequency is affected by a modulation frequency, f , and a _m maximum frequency deviation, ∆ . They set the bandwidth over that the spectral f energy is spread. The ratio between ∆ and f f is defined as the modulation index _m

m f f

β = ∆ . (1.2)

The spectral content of a frequency-modulated signal is best described using the Bessel functions or Carson’s Rule. The resulting signal includes a spectral component on the carrier frequency and an infinite number of sidebands. As shown in Figure 1.2, they are the frequency-modulated sinusoidal waveform in time domain and frequency domain.

c f

c m

f − f f_c+ f_m

(a) time domain (b) frequency domain

m f ( ) 0 J

β

( ) 1 J

β

( ) 2 J β 2 f∆ ( ) 1 J

β

( ) 3 J β c f c m f − f f_c+ f_m

(a) time domain (b) frequency domain

m f ( ) 0 J β ( ) 1 J

β

( ) 2 J β 2 f∆ ( ) 1 J

β

( ) 3 J β

Figure 1.2 Frequency-modulated signal at (a) time domain, (b) frequency domain

The amplitudes of sidebands are proportional to the order of J_n( )β and frequency spacing of f . Specifically, _m J_n( )β is negligible for n> + and a β 2 finite number of sidebands is resulted. Therefore, the bandwidth of a frequency-modulated signal is obtained in (1.3). Considering a wideband frequency-modulated signal, β _{≫ , the bandwidth is approximated as 2 f}1 ∆ .

2 _m 2( 1) _m 2( _m) 2

BW = nf = β + f = ∆ +f f ≈ ∆ . (1.3) f Figure 1.3 shows the effects of modulation index on the spectral content. β is increased by increasing ∆ or decreasing f f . As _m β increases, the spectral energy is distributed evenly in the band and resulting in a greater overall amplitude reduction.

c f f 0.2 β = 2 f∆ c f f 1

β

= 2 f∆ c f f 5 β = 2 f∆ c f f 10 β = 2 f∆ c f f 5 β = 2 f∆ c f f 10

β

= 2 f∆ c f f 15 β = 2 f∆ c f f

β

→ ∞ c f f 0.2 β = 2 f∆ c f f 1

β

= 2 f∆ c f f 5 β = 2 f∆ c f f 10 β = c f f 0.2 β = c f_c f f 0.2 β = 2 f∆ c f f 1

β

= 2 f∆ c f f 1

β

= 2 f∆ c f f 5 β = 2 f∆ c f f 5 β = 2 f∆ c f f 10 β = 2 f∆ c f f 10 β = 2 f∆ c f f 5 β = 2 f∆ c f f 10

β

= 2 f∆ c f f 15 β = 2 f∆ c f f

β

→ ∞ 2 f∆ c f f 5 β = 2 f∆ c f f 10

β

= 2 f∆ c f f 10

β

= 2 f∆ c f f 15 β = 2 f∆ c f f 15 β = 2 f∆ c f f

β

→ ∞ 2 f∆ c f f

β

→ ∞

(a) fixed f and varied _m ∆ (b) fixed ff ∆ and varied f _m Figure 1.3 β effects of the frequency-modulated signal

It is also known that a frequency-modulated signal has the spectral energy redistributed in the frequency domain. The shape in the spectrum is determined by the frequency modulation profile in the time domain. There are various modulation profiles for the SSC technique, such as random pulses, sinusoidal, and triangle profiles [3], [4], [5]. Among these profiles, the triangular modulation profile has the most evenly distributed shape in the frequency domain. Thus, the greatest EMI attenuation can be achieved. It easily achieves the emission standards for a given EMI limitations.

1.3 EMI Attenuation for Spread Spectrum

Clock

As the description in prior section, J_n( )β is negligible for a significantly large

n; and the bandwidth is approximated as 2 f∆ . Considering a clock without inherent jitters, the EMI attenuation A_dB is estimated by [6]

( o) dB 10 m n f Attenuation = A 10 log f δ⋅ ⋅ ≈ ⋅ . (1.4)

Where n f⋅ _o is the harmonic frequency, f is the modulation frequency, and _m δ is the spread ratio. δ specifies the total amount of spreading as a relative percentage of the carrier frequency. A_dB is directly proportional to the spread ratio and the harmonic frequency and inversely proportional to the modulation frequency. To achieve the maximum attenuation, the spread ratio has to be increased, and the modulation frequency has to be decreased.

In addition, we consider the effect of the EMI attenuation with the random period jitter δ_JNMC in the spread spectrum clock. (1.5) represents a small decrement of

dB

D between the amplitude with and without jitter [6]. D_dB is described by (1.6).

D1dB

f means that the decrement is 1 dB and is determined by (1.7). f_D1dB is directly proportional to the square root of f and _o f , and inversely proportional to _m

JNMC

δ . Therefore, D_dB is decreased along with the increment of f . Thus, to _m obtain more EMI attenuation with jitter, δ_JNMC must be minimized.

( ) ( )

dB with jitter dB without jitter dB

A =A −D ±1 (1.5) 0.8 o dB D1dB n f D f  ⋅  =_{ }   (1.6)

, 0 m D1dB ₂ JNMC K f f f K 0.5

δ

⋅ ⋅ = = (1.7)

As shown in Figure 1.4, the spread spectrum clock without jitter obtains the maximum EMI attenuation. Oppositely, if there is the jitter disturbance in the spread spectrum clock, the uneven shape of the spectral energy is observed in the frequency domain. The EMI attenuation caused by

δ

_JNMC is decreased.

0 n f⋅ A tt en u at io n (w it h o u t ji tt er ) A tt en u at io n (w it h j it te r) Regular clock Spread spectrum clock without jitter

Spread spectrum clock with jitter

S p ec tr u m Sp ec tr u m 0 n f⋅ Frequency Frequency Regular clock 0 n f⋅ A tt en u at io n (w it h o u t ji tt er ) A tt en u at io n (w it h j it te r) Regular clock Spread spectrum clock without jitter

Spread spectrum clock with jitter

S p ec tr u m Sp ec tr u m 0 n f⋅ Frequency Frequency Regular clock

Figure 1.4 Decrement of attenuation without/with respect to jitter

1.4 Implementation of SSCG

Changing the carrier frequency is a widely adopted technique to reduce the EMI radiation. There are three types of spread spectrum clock generators (SSCGs) for the frequency synthesizer presented in Figure 1.5 (a), (b), and (c).

The circuit shown in Figure 1.5(a) is an analog technique [7]. It is composed of two charge pump. One is to be in the primitive PLL loop, and the other is an inserted charge pump current. Through the integration of a loop filter, the additional current creates the periodical triangular modulation signal at the input node of the VCO. This

technique is usually called “VCO modulation.” It simply achieves a wider modulation bandwidth, so it is used in many applications such as the Bluetooth FM transmitters. However, the approach creates an additional jitter from modulating the VCO. One alternative to the analog modulation is phase interpolation [8]. Shown in Figure 1.5 (b), the modulation signal is applied to the coherent frequency by controlling the output phases in the phase interpolator. However, achieving a reasonable EMI reduction, such as 10 dB, is much difficult. This is because that the integrated phase interpolator does not have accurate phase linearity. Finally, Figure 1.5 (c) shows the circuit that uses the digital modulation in the PLL feedback loop. It is based on the fractional-N technique to attain to the spread spectrum clock at the output. By modulating the feedback loop of PLL, a modulated clock will be generated in the output. Compared with the other modulation technique, it provides a good triangular linearity [9], [10]. PFD CP LF VCO ref F out F Divider

(a) VCO modulation

PFD CP LF VCO ref F out F Divider Phase Interpolator (b) Phase interpolation

PFD CP LF VCO ref F out F Divider (c) Divider modulation

Figure 1.5 Three types of SSCGs implementation

1.5 Impacts of SSC on Timing

For a spread spectrum clock, the frequency varies periodically with time, so does the period. As illustrated in Figure 1.6, the period of modulated signal varies with time and it is changed depending on the modulation profile. Because of the variation of the modulated clock period, the impacts on time are important [11].

1

T T₂ T₃ T_{k 1−} T_k T_{k 1+}

fm T

Figure 1.6 Spread spectrum clock at time domain

A. Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the change in a clock’s output transition from its corresponding position in the previous cycle. Figure 1.7 shows a graphical representation of cycle-to-cycle jitter [12].

1 T T₂ T₃ Clock 1 2 1 2 3 2 Jitter T T Jitter T T = − = −

Figure 1.7 Graphical representation of cycle-to-cycle jitter

The period difference between the maximum and minimum frequencies in a SSC system is 1 1 (1 ) total o o o T f f f

δ

δ

∆ = − ≈ − . (1.8) The number of clock cycles that exist in the time interval that the modulated clock migrates from f_o to (1−

δ

)f_o can be found as

1 1 2 2 avg avg m m f N f f f = ⋅ ⋅ = , (1.9) where f_avg is the average frequency of the spread spectrum clock.

Because the modulation profile is symmetric, we can only consider the f_avg in the middle of the modulation period,

(1 0.5 ) avg o f = −

δ

⋅ f . (1.10) We rewrite (1.10) as (1 0.5 ) 2 2 avg _o m m f _f N f

δ

f = = − ⋅ . (1.11)

Combining (1.8) and (1.11), the cycle-to-cycle period change can be expressed as

2 2 (1 0.5 ) total m c c o T f T N _f

δ

δ

− ∆ ∆ = = ⋅ − . (1.12)

Considering a 1.25GHz spread spectrum clock with the spread ratio of 5000ppm and the modulation frequency of 30kHz, the increase in cycle-to-cycle jitter is

3 16 9 2 2 0.5% 30 10 1.925 10 (1 0.5 0.5%) (1.25 10 ) c c T ₋ ⋅ ⋅ − sec ∆ = ⋅ = ⋅ − ⋅ _⋅ . (1.13) B. Long-Term Jitter

Long-term jitter is defined as the maximum change in a clock’s output transition from its ideal position. Figure 1.8 shows the graphical representation of the long-term jitter [12]. i T Ideal Clock j T i j Jitter=T −T Jitter Clock

Figure 1.8 Graphical representation of long-term jitter

Because there exists the spreading frequency modulation, there are many clock cycles passed by the reference period. The long-term jitter of the spread spectrum modulated signal is tremendous.

1.6 Considerations for Using Spread

Spectrum Clocking

SSCG is utilized in many systems to reduce the radiated emissions. Theses systems are composed of microprocessors, ASICs, RAM, and other logic circuits. They are usually designed to complete some operations within one clock cycle. Because of the throughput requirement, a general method is to increase the internal or core frequency through the clock multiplication. It is often implemented by using frequency multiplying PLL. In addition, it is necessary to minimize the timing difference between the system clock and the I/O signals in the system. This is because that an excessive delay in the operation significantly reduces a system’s throughput.

One of the SSCG concerns is the clock skew [13]. If the input signal is a SSC clock and its frequency migrates from f_o to (1−

δ

)f_o, the PLL does not identically track the input clock and instantaneously update the output clock. The accumulation from the period difference results in a significant amount of the phase error. This phase error is defined as the PLL tracking skew between the input clock and its output clock. The tracking skew decreases the setup and hold margins in the corresponding interfaces. It affects the device timing margins in reading or writing data.

In General, SSC has triangle modulation profiles and contains higher-order harmonic contents than the carrier frequency. The maximum frequency change happens when the triangle profile changes the polarity of the slew rate at the corners. Thus, in order to accurately track the SSC signal in the PLL, the closed-loop bandwidth must be large enough to pass the sufficient number of high-order harmonic contents. This closed-loop bandwidth is determined by the PLL transfer function. With a second-order loop filter, this transfer function is defined as

( ) _out( ) _in( )

2 3 2 1 2 1 1 2 1 1 2 1 ( ) ( ) ( ) out CP VCO CP VCO CP VCO in FB s s I K R C H s I K I K C C s N C _{s s s} R C C N C R C C

θ

θ

+ ⋅ ⋅ = = ⋅ ⋅ ⋅ + ⋅ _{+ ⋅ + ⋅ +} ⋅ ⋅ ⋅ ⋅ ⋅ , (1.15) where I_CP is the charge pump current, K_VCO is the VCO’s gain, N_FB is the divider division ratio, and C₁, C₂, and R are the values of the loop filter components.

However, a larger bandwidth results in diminishing the PLL stability and raises susceptibility to noise. Therefore, the bandwidth considerations of the downstream PLL must be made to accommodate the spread spectrum clock to minimize the timing problems in the system.

Chapter 2

Fractional-N Phase-Locked Loop

with Σ∆ Modulator

In traditional PLL based on frequency synthesizers, division ratios in the feedback path are restricted to the integers. When a finer frequency resolution is required, the lower reference frequency results in narrow bandwidth and low switching speed. The larger division ratio also causes larger noise amplification from the reference to the synthesizer output. Recently, fractional-N synthesis techniques are widely adopted in the wireless applications. This technique overcomes the shortcomings of traditional PLL frequency synthesizers. Sigma-delta modulator (Σ∆ modulator) is the most suitable scheme for the fractional-N synthesis technique. In this chapter, we will discuss the fundamental theory of PLLs and the fractional-N mechanism.

2.1 Phase-Locked Loop Fundamentals

Today’s phase-locked loops (PLL) are preferred choices for generating stable, low-noise, and particularly tunable oscillation frequency in the communications. A basic PLL architecture we discuss is shown in Figure 2.1. It consists of a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop Filter (LF), a Voltage Controlled Oscillator (VCO), and a divider.

PFD CP LF VCO Divider 1 N ref F div F out F ctrl V

Figure 2.1 Block diagram of a typical PLL

After a locking process, all the signals in the loop finally reach a steady state and the PLL operates as follows. The internal feedback signal F_div from the divider is compared to the external reference signal F_ref by PFD. PFD serves as an error amplifier in the loop and attempts to reduce the input phase difference. It generates two messages to CP, Lead/Lag message and the phase difference between F_ref and

div

F . CP charges and discharges the loop filter according to the input phase difference and produces a control voltage V_ctrl to vary VCO output frequency. VCO oscillates at a frequency that is equal to the N times the internal feedback frequency F_div. Finally, F_div is adjusted according to the synchronous input signal. F_out is

ref

N×F in the steady state.

Figure 2.2 displays a block diagram of the linear model. We use mathematical analysis to determine the parameters [14]. It also provides the overall s-domain transfer function. PFD and CP have a gain of K_PFD. It is the charge pump current divided by 2π . LF transfer function in the s-domain is represented as Z_LF( )s . It is

usually designed as a second-order or a third-order filter. K_VCO is the VCO’s gain for the phase expression. Since integration is a linear operation on the VCO’s output frequency, the output phase is also divided by a factor of N in the frequency divider. VCO LF ( ) ref s φ ( ) div s φ ( ) out s φ PFD K KVCO s ( ) LF Z s 1 N

Figure 2.2 Block diagram of a PLL linear model

The forward gain is therefore derived as ( ) ( ) KPFD LFZ s KVCO G s

s

= . (2.1) The feedback gain is

1 ( ) H s

N

= . (2.2) Then, the close loop transfer function is expressed as

( ) ( ) ( ) ( ) ( ) 1 ( ) ( ) 1 PFD LF VCO out PFD LF VCO ref K Z s K s G s _s K Z s K s G s H s s N φ φ = + = ₊ ⋅ . (2.3)

The order of the PLL transfer function is determined by the loop filter. We consider a linear model charge-pump PLL and the loop filter transfer function as

1 ( ) LF Z s R sC = + . (2.4)

We rewrite the close loop transfer function as 2 2 2 ( 1) ( ) ( ) ( ) ( 1) 2 PFD VCO out PFD VCO PFD VCO ref PFD VCO n n K K sRC s _C T s K K K K s s RC s N C NC K K sRC C s s

φ

φ

ζω

ω

+ = = + ⋅ + ⋅ + = + ⋅ + . (2.5)

The natural frequency

ω

_nand damping factor

ζ

of the system can be derived as

, 2 PFD VCO n n K K RC N C

ω

=

ζ

=

ω

⋅ . (2.6)

2.2 Types of Noise Sources in PLL

By the above mathematical analysis, we now will discuss noise effects and its influence in PLL. Shown in Figure 2.3 is the PLL model with three noise sources being added. V_n1( )s is associated with PFD and CP. It is also known as the input reference noise. V_n2( )s is introduced by the loop filter. V_n3( )s is the phase noise generated by the VCO.

VCO K s ( ) LF Z s 1 N PFD K ( ) ref s φ φ_out( )s 1( ) n V s V_n2( )s V_n3( )s

The equations representing the noise transfer function of V_n1( )s , V_n2( )s , 3( ) n V s are 1 ( ) ( ) ( ) ( ) ( ) ( ) ₁ PFD LF VCO out PFD LF VCO PFD LF VCO PFD LF VCO n K Z s K s _s K Z s K K Z s K K Z s K V s _s s N N φ _{= =} + + ⋅ , (2.7) 2 ( ) ( ) ( ) ( ) 1 VCO out VCO PFD LF VCO PFD LF VCO n K s _s K K Z s K K Z s K V s s s N N φ = = + + ⋅ , (2.8) 1 ( ) 1 ( ) ( ) ( ) 1 out PFD LF VCO PFD LF VCO n s s K Z s K K Z s K V s s s N N

φ

_{= =} + + ⋅ . (2.9)

First, considering the input reference noise, the noise transfer function has as a low-pass property. If the input reference noise varies rapidly, the output phase will not fully track the variations. In other words, only the slowly varying input reference noise can propagate to the output. Second, the noise effect of V_n2( )s has the same property as V_n1( )s . Finally, VCO tends to accumulate its noise fluctuations and passes them to the output. Figure 2.4 shows the summary of the noise responses. In order to receive suppressed noise fluctuations in the output, a moderate loop bandwidth should be chosen. This is because that there exists a trade-off between the VCO’s noise and the input reference noise [15].

1 ( ) ( ) out n s V s φ 2 ( ) ( ) out n s V s φ 3 ( ) ( ) out n s V s φ 1 ( ) ( ) out n s V s φ 2 ( ) ( ) out n s V s φ 3 ( ) ( ) out n s V s φ

2.3 Fractional-N Frequency Synthesis

The fractional-N frequency synthesis technique has an advantage of synthesizing non-integer multiplications between the output frequency and the reference signal. It improves the phase noise and the switching speed. Using this technique has no limited loop bandwidth as integer frequency synthesizers.

In general, the fractional-N PLL is classified into two types. One is based on the integer divider. It achieves fractional-N synthesis through averaging the divider division ratio in a long time. By switching the division ratio among two or more values, the divider divides by a non-integer number. The other is using the Σ∆ modulation concept [16]. It results in a beneficial noise shaping of the phase noise introduced by the fractional-N division. Thus, the technique provides the low phase noise and the reduced spurious impacts compared to the first type.

Figure 2.5 shows a dual-modulus prescaler introduced in the PLL [17]. It divides VCO’s output frequency by either N or N+ . Together, two synchronous counters 1 are combined to construct a variable frequency divider.

PFD CP LF VCO ref F out F A Counter 1 N N ÷ + M Counter

1 N ÷ + ÷N ÷ +N 1 N ÷ M ÷ ÷M A ÷ ÷A

Figure 2.6 Dual-modulus prescaler operation mechanism

Figure 2.6 is a timing diagram of a dual-modulus prescaler. Initially, both A counter and M counter start at the same time. PLL tracks the frequency and locks at a division of N+ until A counter is ended. Then, A counter is disabled and the 1 divider jumps to N before the M counter is overflow. The process is repeated periodically. Finally, the average division ratio is obtained as

( 1) ( ) avg N A N M A A N N M M + ⋅ + ⋅ − = = + . (2.10) Therefore, using the PLL frequency synthesizer with the dual-modulus prescaler can obtain an average division ratio between the two dividers. However, there is a serious problem in this structure. It results in spurious frequencies in the output spectrum. Shown in Figure 2.7, a periodically sawtooth phase error is produced in PFD. The phase error from the difference of the input signals accumulates and goes back to zero. It presents a periodic behavior and generates the fractional spurs in the output spectrum. Divider Out Reference Clock Phase Error N ÷ 1 N ÷ + t Divider Out Reference Clock Phase Error N ÷ 1 N ÷ + t Figure 2.7 Sawtooth phase error

Figure 2.8 shows the resulting fractional spur which are typically only 20 or 30 dB below center frequency. It seriously degrades the signal purity in the output spectrum [18]. Thus, how to constrain the fractional spur is a serious subject. For this, the sigma-delta modulator (Σ∆ modulator) technique can overcome this problem. It is most suitable for the fractional-N frequency synthesis.

Center Frequency Fractional Spurs Center Frequency Fractional Spurs

Figure 2.8 Spurious noise in the PLL output spectrum

2.4 Sigma-Delta Modulator

A Σ∆ modulator technique is widely used for ADC and DAC application [19]. This technique pushes the quantization noise to a higher frequency, suppresses the in-band quantization noise, and increases the signal to noise ratio (SNR).

As shown in Figure 2.9, a Σ∆ modulator has an integrator at the input and a differentiator behind a quantizer. In conventional Σ∆ modulator application, the output is followed by a low-pass filter in order to remove the high-frequency quantization noise. Because there exists a low-pass characteristic in the PLL, the out-of-band quantization noise is suppressed by higher order poles.

G F G F Differentiator Quantizer Integrator Input Output F _{F F F}

Figure 2.9 Fundamental theory of Σ∆ modulator

A 1-order Σ∆ modulator is shown in Figure 2.10. Both the integrator and the differentiator are first-order and complementary. However, the 1-order Σ∆ modulator encounters an overflow problem due to the high dc gain of the integrator. In order to solve the problem, the subtraction section in the differentiator is moved to the front of the integrator as a negative feedback system. But the transfer function is not changed. Figure 2.11 shows the improved 1-order Σ∆ modulator.

Quantizer

1

z− z−1

Integrator Differentiator

Input Output

Quantizer 1 z− 1 z− Integrator Differentiator Output

Figure 2.11 Modified structure of first-order Σ∆ modulator

A first-order Σ∆ modulator in its digital implementation is illustrated in Figure 2.12 (a). The equivalent circuit diagram is shown in Figure 2.12 (b), where [ ]e n is the quantization noise added at the quantizer. The input signal [ ]k n is integrated to produces the signal [ ]v n . A 1-bit quantization process is accomplished by taking the most significant bit (MSB) of [ ]v n . It is represented as the accumulator overflow. Besides the MSB of [ ]v n , the residue signal is the negative quantization error. It is then stored in the register. Therefore, the modulator with error feedback can be fully implemented with digital circuit.

1 z− [ ] e n [ ] v n [ ] k n b n[ ] [ ] e n − [ ] k n [ ] b n [ ] e n −

(a) digital implementation (b) equivalent block diagram

In z-domain [20], the transfer function is written as

B z( )=K z( ) (1+ −z−1) ( )E z , (2.11)

where the (1−z−1) term is a zero in the origin referred as the noise transfer function (NTF). It is known that an additional zero in the origin in the transfer function produces a slope shaper by 20 dB dec. More zeros in the origin push the quantization noise to a higher frequency. The higher-order NTF is written as (1−z−1)m , where

m is the order of the modulator. In addition, from (2.11), the power spectral density (PSD) is rewritten as 2 ( ) ( ) ( ) ( ) 2 ( ) B K f K E s S f S f S f f S f sin S f f

π

= +    = +_{  } ⋅     , (2.12)

where f is the sampling frequency. _s

Assume that 1-bit quantizer has an uniform quantization error and the power is spread over a bandwidth of f . Consequently, the PSD of the quantization error is _s 1 (12f_s). Thus, the second term is also represented by a general formula and written as 2 1 ( ) 2 12 m f s s f S f sin f f

π

   = _{⋅   } ⋅ _{  } , (2.13)

2.5 MASH 1-1 Sigma-Delta Modulator

For today’s fractional-N frequency synthesizers with the Σ∆ modulators, it is implemented by using the multi-stage-noise-shaping (MASH) architecture. This is because that the MASH architecture is unconditionally stable and easy for the digital implementation. In general, the second-order and the third-order Σ∆ modulator are usually adopted. Fourth-order or even higher order Σ∆ modulator are rarely adopted

oppositely. This is because the output phase noise is difficult to suppress at high frequency by a finite order of the loop filter.

As shown in Figure 2.13, a second-order MASH 1-1 modulator is formed by cascading two first-order Σ∆ modulators [21], [22]. In order to reduce the quantization noise, the quantization error from the first stage is fed into the second stage. Then, through the error cancellation mechanism, the quantization noise from the first stage is cancelled in the output. The quantization noise from the second stage is remained and shaped to a high frequency.

1 z− 1( ) E z 1( ) B z 1 z− 1 z− 2( ) E z 2( ) B z ( ) f z Y z( )

Figure 2.13 Second-order MASH 1-1 Σ∆ modulator

The equations of the individual first-order modulator are written as

1 1 1 1 2 1 2 ( ) ( ) (1 ) ( ) ( ) ( ) (1 ) ( ) B z f z z E z B z E z z E z − − = + − ⋅ = − + − ⋅ , (2.14)

where f z is the fractional number. ( ) E z₁( ) and E₂( )z represent the quantization noise in two stages respectively. Therefore, the output of the Σ∆ modulator is

1 1 1 1 1 2 1 2 2 ( ) ( ) (1 ) ( ) ( ) (1 ) ( ) (1 ) ( ) (1 ) ( ) Y z f z z E z E z z E z z f z z E z − − − −   = + − ⋅ + −_ + − ⋅ _⋅ − = + − ⋅ . (2.15)

Considering a PLL with a second-order MASH 1-1 Σ∆ modulator, the inherent division ratio N_div of the divider is

1 2 2

( ) (1 ) ( )

div

N =Nf z + −z− ⋅E z , (2.16) where the first term is the wanted division ratio determined by the Σ∆ modulator.

Figure 2.14 shows the digital circuit implementation. The total divider division ratio N_div is summed with the nominal number N and the Σ∆ modulator output

( ) Y z . 1 z− 1 z− 1 z− div N N . ( )f z 1( ) E z − ( ) Y z

Figure 2.14 MASH 1-1 Σ∆ modulator implementation

In order to determine the effect of the Σ∆ quantization noise in the out-of-band, we consider the PLL whose divider is controlled by the Σ∆ modulator. From (2.16), we derive the PLL output frequency F_out( )z as

1 2 2

( ) ( ) (1 ) ( ) ( )

out ref ref

where the second term consists of the frequency fluctuations due to the Σ∆ quantization noise, which crosses over the closed loop transfer function of PLL, T(z).

For E₂( )z being 1 (12f_s), the PSD of the frequency fluctuations is calculated as 2 1 2 4 1 1 ( ) (1 ) 12 (1 ) 12 f_E ref s s S z z f f f z − − = − ⋅ ⋅ = − ⋅ . (2.18)

To receive the phase fluctuations, we convert the frequency fluctuations to the phase fluctuations.

( )t f dt_E

φ

=

_∫

. (2.19) Employing a simple rectangular integration to represent

∫

dt in the z-domain,

1 2 ( ) ( ) (1 ) E ref z F z f z

π

− Φ = − . (2.20) With (2.20), we obtain 2 _{2 2} 1 (2 ) _rad ( ) 1 Hz 12 _ref S z z f

π

− Φ = ⋅ − . (2.21) Generally, 2( 1) 2 ₂ (2 ) _rad ( ) 2 Hz 12 m E ref ref f S f sin f f

π

 

π

 − =  _ _  _{ }   . (2.22)

From (2.22), it reflects that the m th-order Σ∆ modulator provides a

20 (⋅ m−1) dB dec slope characteristic. It shapes the noise to high frequency. Such as the MASH 1-1 Σ∆ modulator also provides the high-frequency noise shape by

20 dB dec. As shown in Figure 2.15, the phase noise generated by the Σ∆ quantization noise is plotted with second-order, third-order, and fourth-order structures respectively. Their shapes are clearly observed there.

104 105 106 107 -260 -240 -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 Second order Third order Fourth order P h a s e N o is e (d B c /H z ) Frequency(Hz)

Figure 2.15 Quantization noise of second to fourth-order Σ∆ modulator

2.6 Design Consideration for PLL Loop

Bandwidth

As the prior description, the quantization noise shaped by the Σ∆ modulator is concentrated at high frequency. Here, we discuss a third-order PLL with the MASH 1-1 Σ∆ modulator. Due to the low-pass characteristics in a PLL, there exists an in-band phase noise with a positive 20 dB dec slope and an out-of-band phase noise with a negative 40 dB dec slope. So it is necessary to choose the narrow loop bandwidth in order to reduce the output phase noise. According to [23], the dynamic range of the L th-order Σ∆ modulator must be higher than the dynamic range of the synthesizer. 2 1 2 2 2 3 2 1 8 2 2 2 L PFD PFD L c _rms c L f f f f

π

θ

+     + ⋅ ⋅_{ } > _{ }     , (2.23)

where f_c and

θ

_rms are the noise bandwidth and the in-band phase error of the frequency synthesizer respectively. So the approximated upper bound of the loop bandwidth is obtained as (1 2 1) 2 2 3 2 1 8 _{(2 )} L c rms _L PFD L f

θ

f

π

−  ₊  < ⋅ ⋅  ⋅     , (2.24)

where

θ

_rms is the in-band phase error.

In addition, considering the SSCG based on the fractional-N technique by using the Σ∆ modulator, the PLL loop bandwidth must be wide enough. This is because that there are some distortions on the triangle modulation profile under such a narrow loop bandwidth. Therefore, to make sure that the triangle modulation profile can be preserved, the loop bandwidth must be at least one order of magnitude higher than the modulation frequency [24]. According to this rule, we can obtain the desired loop bandwidth.

Chapter 3

Programmable Spread Spectrum

Clock Generator Implementation

3.1 Architecture of the Proposed

Programmable SSCG

Figure 3.1 shows the block diagram of the proposed programmable SSCG. The circuit consists of an integer-N 1.25GHz 8-phase PLL, a programmable triangle generator, a Σ∆ modulator, a multiplexer (MUX) controller, and a programmable divider. Basically, the design is based on the fractional-N and the Σ∆ modulation technique. But it is different in the way that the programmable SSCG generates various spread spectrum clocks through modulating the multi-phase of the PLL output

[25]. The divider in the feedback loop combining with the phase selection of the VCO output attains to a smaller division ratio. It also leads to a less frequency jump in the

output. The approach has an advantage of the low-jitter compared to the direct division modulation. ref F out F Σ∆ 1 2 1 16 Pro_ fm . . Pro_ S R

Figure 3.1 Architecture of the proposed programmable SSCG

The programmable divider produces a different clock frequency which is then fed into the programmable triangle generator. Its division ratio is related to the modulation frequency. The programmable triangle generator creates various triangle profiles. It is used to determine the modulation frequencies from 30 kHz to 300 kHz and the spread ratios from 2500 ppm to 50000 ppm. The Σ∆ modulator shapes the noise to a higher frequency. Furthermore, the smoothing effect of the PLL loop results in a continuous frequency modulation from the discrete staircase output of the programmable triangle generator. The MUX controller receives the modulation signal from the Σ∆ modulator and controls the MUX to select a suitable clock phase for the divider. In addition, it is necessary to have a tunable loop bandwidth according to the different modulation frequency in the programmable SSCG.

Phase Frequency Detector

Figure 3.2 (a) is a phase frequency detector (PFD). It is composed of two D flip-flops (DFFs) and a NOR gate. The DFFs are true single phase clock (TSPC) type DFFs as shown in Figure 3.2(b) [26]. Compared with the conventional PFD, the PFD with TSPC DFFs overcomes the speed limitation and reduces the dead zone.

CLK RST D Q CLK RST D Q ref F div F UP DN UPb DNb RST CLK CLK Q (a) PFD (b) TSPC DFF Figure 3.2 Circuit schematic of (a) PFD, (b) TSPC DFF

Figure 3.3 shows the timing diagram. If the input clocks, F_ref and F_div, are in-phase, both UP and DOWN pulses are produced in a same short period of time. If there is a phase difference between the input clocks, the difference between the widths of UP and DN pulses is proportional to the input phase difference.

ref F div F UP DN ref F div F UP DN

Programmable Charge Pump

The proposed programmable charge pump is illustrated in Figure 3.4. The biasing current mirror based on a digital-to-analog converter (DAC) technique is illustrated in Figure 3.5 [27]. The programmable charge pump converts the phase difference of the input clocks to a voltage signal to control VCO. It is composed of two current sources, four switches, a unit-gain buffer, and a programmable biasing circuit. The charged and discharged currents are programmed by a 2-bit control word. The unit-gain buffer is used to clamp the terminal voltage of the current sources when there is no current pumping into the loop filter. In such way, the voltage glitch due to charge sharing is eliminated.

ctrl V

UPb DN b1 b0 2 1 ctrl V

Figure 3.5 Programmable biasing current mirror

Programmable Loop Filter

According to the prior chapter, it is known that using a narrow loop bandwidth reduces the output phase noise generated from the Σ∆ modulator. But there occurs some distortions on the triangle modulation profile. To compromise both requirements, one must be careful in determining the loop bandwidth of the system. Here, in order to achieve a finer triangle modulation profile and a smaller output phase noise from the Σ∆ modulator, we design a programmable loop bandwidth. Figure 3.6 shows a second-order loop filter where R₂ is programmed by a 2-bit control word.

cp I ctrl V 1 C C2 2 R

This transfer function is written as 1 ( ) 1 ( ) ctrl z lf cp p V s LF s K I _{s s}

ω

ω

+ = = ⋅ ⋅ + , (3.1) where 2 2 1 2 lf R C K C C ⋅ = + , _{2 2} 1 1 z z T R C

ω

= = ⋅ , and 1 _{1 2 1 2} 1 1 ( // ) p p T R C C

ω

= = ⋅ .

Figure 3.7 shows the Bode plot of the open loop gain in PLL with a second-order loop filter. Here, we must design the sufficient phase margin

φ

_p to ensure the maximum stability. 1 p

ω

0dB -90 -180 G(s)H(s) Phase G(s)H(s) ∠ Gain p ω z

ω

p φ Frequency 1 p

ω

0dB -90 -180 G(s)H(s) Phase G(s)H(s) ∠ Gain p ω z

ω

p φ Frequency

Figure 3.7 Bode plot of PLL with the second-order loop filter

According to [28], we calculate the equations to recide the passive component values as 2 1 1 _{2 2} 1 1 ( ) 1 ( ) p _{PFD VCO} p z z _{p p p} T _{K K} T C T _{N T} ω ω ω + ⋅ = ⋅ + ⋅ , (3.2) 2 1 1 ( z 1) p T C C T = ⋅ − , (3.3) 2 2 z T R C = , (3.4) where

ω

_p, K_PFD, K_VCO, N are the unit gain bandwidth, the PFD’s gain, the VCO’s gain, and the divider division ratio respectively.

In addition, in order to effectively suppress the out-of-band quantization noise from the Σ∆ modulator at higher frequency, a third pole composed of R₃ and C₃ is added to the loop filter. Figure 3.8 shows this circuit schematic diagram.

cp I ctrl V 1 C 2 C 2 R 3 C 3 R

Figure 3.8 Schematic of the third-order loop filter

Thus, the transfer function is

2 3 2 1 2 1 2 2 2 2 ( ) 1 1 1 1 1 z lf lf lf z p p p p p s LF s K K K s s R R

ω

ω

ω

ω

ω

ω

ω

+ = ⋅      ⋅  + + + ⋅ ⋅ + +_ _ ⋅ _{    } ⋅ _ , (3.5) where ₂ 3 3 1 p R C

ω

= ⋅ .

We analyze the relationship between the third pole and the added attenuation. It is used as the design criterion in determining the third pole.

2 2 10 log ref 1 p Attenuation

ω

ω

_{ }    = ⋅ __ _ + _       . (3.6)

Voltage Controlled Oscillator

In a conventional ring oscillator, the oscillation frequency is decided by a delay time of the delay element. The delay time can not be smaller than a single inverter delay. Therefore, the maximum frequency of the VCO is limited. To solve this frequency limitation problem, a technique using a negative skewed delay scheme has

been proposed. Figure 3.9 shows the VCO structure. It is composed of four-stage fully differential delay cells and dual-delay paths. With the negative skewed delay scheme, it decreases the unit delay time. As a result, a higher operation frequency is obtained

[29]. out out in1 in2 in1 in2 out out in1 in2 in1 in2 out out in1 in2 in1 in2 out out in1 in2 in1 in2

Figure 3.9 Four-stage ring oscillator with dual-delay paths

Figure 3.10 is a four-input differential delay element. When V_ctrl is low, the latch becomes weak and the output driving current from the PMOS increases. Therefore, the state is changed easily and the delay time is reduced. Oppositely, when

ctrl

V is high, the latch becomes strong. It resists the voltage switching in the differential delay cell and the delay time increases. Consequently, with the normal delay paths and the negative skewed delay paths simultaneously, it achieves a higher oscillation frequency and obtains a wider tuning range.

vctrl in1 in1 in2 in2 out out

Programmable Triangle Generator

The programmable triangle generator is designed to create a different triangle profiles. It determines the modulation frequencies from 30 kHz to 300 kHz and the spread ratios from 2500 ppm to 50000 ppm. Figure 3.11 is the proposed programmable triangle generator including an accumulator and a counter. It generates the triangle waveform with discrete staircases for the Σ∆ modulator. Through the different clock frequency of CLK__tri from the programmable divider, it generates different clock cycles of Sel at a fixed count number of the counter. Thus, the various modulation frequencies are produced and illustrated in Figure 3.12 (a). In addition, the programming signal Pro__{S R. .} decides the frequency deviation. As illustrated in Figure 3.12 (b), it is accumulated increasingly or decreasingly along with

__tri

CLK until Sel changes state. Therefore, by programming CLK__tri and

. . __{S R}

Pro , we obtain the desired triangle profile.

. . __{S R} Pro __tri CLK Sel

. . __{S R} 1 Pro = . . __{S R} 3 Pro = . . __{S R} 6 Pro = 30kHz 60kHz 120kHz

(a) Different modulation frequencies (b) Different spread ratios Figure 3.12 Difference discrete staircases of the triangle profile

MASH 1-1 Sigma-Delta Modulator

As described in Chapter 3, the Σ∆ modulator implemented in the PLL provides the low phase noise and reduces the spurious impact. It overcomes the shortcomings in traditional PLL frequency synthesizers. In addition, the MASH architecture is unconditionally stable and easy for the digital implementation.

Shown in Figure 3.13 is the digital implementation of a modified second-order MASH 1-1 Σ∆ modulator. The output ( )Y z is a 2-bit word and fed into the MUX controller.

+

1 z− 1 z− . ( )f z 1( ) E z − ( ) Y z 2( ) E z −

+

1 z−

The transfer function is written as

2 1 2

2

( ) ( ) (1 ) ( )

Y z = f z ⋅z− + −z− ⋅E z , (3.7) where f z is the wanted output frequency and ( ) E₂( )z is the quantization noise from the second stage. (3.7) shows that the first term includes the delay of z−2 and the second term is the same as (2.15). It has the output signal delays for two clock cycles. However, it does not influence the noise-shaping behavior of the Σ∆ quantization noise.

Multiplexer Controller

Figure 3.14 shows the multiplexer (MUX) controller. It includes an accumulator and a decoder. The MUX controller is placed between the MASH 1-1 Σ∆ modulator and the MUX. It receives the modulation signals from the Σ∆ modulator and transfers them to one-hot code. Then, MUX controller controls the MUX for the phase selection. Table 3.1 shows the output state of the Σ∆ modulator and the corresponding behavior with the phase selection. It executes to rotate right or left one phase in the MUX.

SDM output Mux Control 2 Decoder 3 Accumulator D Q

+

Table 3.1 Output state table of the Σ∆ modulator SDM

Output

Shift

Phase Shift Type 11 1 Shift right 1 phase

00 0 Hold

01 -1 Shift left 1 phase 10 -2 Shift left 2 phase

Through the transformation of the decoder, the output signal of the accumulator is decoded to an one-hot code. Shown in Table 3.2 is the relationship between the 3-bit output signal of the accumulator and the MUX control signals. The MUX control signals correspond to the multiphase output of the VCO respectively. According to the different signal from the Σ∆ modulator, we obtain the desired MUX control signal and the suitable phase clock in the MUX.

Table 3.2 Relationship between accumulator output and MUX control signals

Mux Control Signals Accumulator Output S1 S2 S3 S4 S5 S6 S7 S8 000 1 0 0 0 0 0 0 0 001 0 1 0 0 0 0 0 0 010 0 0 1 0 0 0 0 0 011 0 0 0 1 0 0 0 0 100 0 0 0 0 1 0 0 0 101 0 0 0 0 0 1 0 0 110 0 0 0 0 0 0 1 0 111 0 0 0 0 0 0 0 1

Multiplexer

Through receiving the modulation signals from the Σ∆ modulator, the MUX selects the suitable phase clock for the divider. Here, the 8-to-1 MUX in our design is composed of two 4-to-1 MUX and a 2-to-1 MUX and shown in Figure 3.15 [26]. The extra PMOS transistors in the phase clock input is to precharge the internal node to a high level when the phase clock is low. Therefore, it has a benefit of reducing the charge sharing effect and alleviating the clock jitter.

Furthermore, with different phase selection sequences, it realizes different frequency division ratios in PLL. Moreover, the spreading clock is obtained by modulating the multiphase clock output in the programmable SSCG.

1 S Out 1 P 4 S 4 P 3 S 3 P 2 S 2 P 1 S Out 1 P 2 S 2 P

(a) 4-to-1 MUX (b) 2-to-1 MUX Figure 3.15 Circuit scheme of the (a) 4-to-1 MUX, (b) 2-to-1 MUX

Programmable Divider

The programmable divider produces clocks of different frequency to be fed into the programmable triangle generator. Its division ratio is determined by an assigned program to determine the modulation frequency. Shown in Figure 3.16 is the architecture of the 6-bit programmable frequency divider. It includes a 6-bit counter, an end-of-count (EOC) detector, and a reload circuit [30].

Reload Circuit EOC Dectector Reload __tri CLK __fm Pro __in CLK D Q Q S R D Q Q S R D Q Q S R D Q Q S R D Q Q S R D Q Q S R

Figure 3.16 Architecture of the 6-bit programmable frequency divider

The circuit principle is assumed as a countdown counter. First, a certain preset number is loaded in the counter and the counter starts counting. Once the counter reaches the terminal count state 000010 , the EOC detector delivers a Reload signal to the reload circuit. Then, the counter is commanded to set the initial value N and starts counting again. Therefore, the relationship between the input clock frequency and the output clock frequency is f_tri = f_in N. With 6 counter stages, the frequency division ratio N can be varied from 2 to 26− . 1

Chapter 4

Simulation Results and Layout

The programmable SSCG implementation is based on a fractional-N technique by using a Σ∆ modulation. There are some design issues to be considered such as the system stability problem, the PLL responses, and the loop bandwidth design, etc. In this chapter, we verify the spread spectrum clocking behavior by MATLAB simulation tool and the circuit simulation by HSPICE simulation tool. Finally, we show the global chip layout and the test environment.

4.1 Programmable SSCG Behavior

Simulation

use the MATLAB simulation tool to analyze. Figure 4.1 shows the SIMULINK model. It is based on a charge-pump PLL with a third-order filter. The programmable triangle generator, MASH 1-1 Σ∆ modulation, and MUX controller are also added to modulate the output clocks. We obtain the various triangle modulation clocks through the 6-bit programming modulation frequency and the 5-bit programming spread ratio. This system is simulated as far as the circuit-level is concerned.

[0 : 5] Pro_ fm [0 : 4] . . Pro_ S R [0 : 5] Pro_ fm [0 : 4] . . Pro_ S R

Figure 4.1 SIMULINK model of the programmable SSCG

In addition, we extract from the post-layout simulation results of each fundamental element with corner model variations and arrange them in Table 4.1. Including the data of an inverter delay, a NOR delay, and a DFF delay, etc, are added in this SIMULINK model. Thus, the more precise results can be obtained by the

Table 4.1 Post-layout simulation delay time of each fundamental element

SS TT FF

Inverter, NAND, NOR… 50ps 40ps 32ps

XOR 30ps 27ps 25ps

DFF 160ps 125ps 115ps

SUM 1160ps 930ps 750ps

Full Adder

(12bit) _{CARRY OUT 1230ps 990ps 800ps}

Half Adder SUM 23ps 19ps 16ps

According to Table 4.1, the behavior simulation results with similar corner model variations in time-domain are respectively shown in Figure 4.2 (a), (b), (c). They all exhibit the cases that the frequency is down spreading with a spread ratio of 5000 ppm and a modulation frequency of 30 kHz.

SSC with 5000ppm 30kHz triangle profile TT Corner Time F re q u en c y SSC with 5000ppm 30kHz triangle profile TT Corner SSC with 5000ppm 30kHz triangle profile SSC with 5000ppm 30kHz triangle profile TT Corner Time F re q u en c y (a) TT corner

SSC with 5000ppm 30kHz triangle profile FF Corner Time F re q u en c y SSC with 5000ppm 30kHz triangle profile FF Corner SSC with 5000ppm 30kHz triangle profile SSC with 5000ppm 30kHz triangle profile FF Corner Time F re q u en c y (b) FF corner SSC with 5000ppm 30kHz triangle profile SS Corner Time F re q u en c y SSC with 5000ppm 30kHz triangle profile SS Corner SSC with 5000ppm 30kHz triangle profile SSC with 5000ppm 30kHz triangle profile SS Corner Time F re q u en c y (c) SS corner

Figure 4.2 Behavior simulation of SSC at the difference corners

We analyze this design in FFT with the spread ratio of 5000 ppm and the modulation frequency of 30 kHz. The compared results between SSC mode and non-SSC mode are shown Figure 4.3. The results display that there is about 20 dB reduction of the peak energy.

Attenuation Attenuation

Figure 4.3 FFT of the programmable SSCG at SSC mode and non-SSC mode

4.2 Programmable SSCG Circuit-Level

Simulation

In order to receive the more precise simulation result, we use the HSPICE simulation tool to analyze. Figure 4.4 shows the post-layout simulation result of the VCO with corner model variations. The VCO’s gain is about 680 MHz V at 1.25

GHz . TT SS FS SF FF Control Voltage F re q u en c y TT SS FS TT SF FF SS FS SF FF Control Voltage F re q u en c y

The output eye diagram at non-SSC mode with five corner model variations are shown in Figure 4.5 respectively. The simulation results of the jitter are shown in Table 4.2.

(a) TT corner (b) FF corner

(c) FS corner (d) SF corner

(e) SS corner

Table 4.2 Jitter of the Output eye diagram at non-SSC mode

TT SS FF SF FS

Jitter(p-p) 5.6ps 7.75ps 2.9ps 7.2ps 3.6ps

In order to verify the function in SSC mode, we select several cases for the simulation. We can see various frequency-modulation results with triangular waveform in time domain and frequency domain obviously.

First, Figure 4.6 shows the control voltage variation in SSC mode with a spread ratio of 32500 ppm and a modulation frequency of 30 kHz. Figure 4.7 shows its spectrum with spreading.

32500ppm

30kHz 32500ppm

30kHz

Figure 4.6 Control voltage of SSCG with 32500 ppm and 30 kHz spread

32500 ppm 32500 ppm

Figure 4.7 FFT of SSCG with 32500 ppm and 30 kHz spread

Second, Figure 4.8 shows the control voltage variation in SSC mode with a spread ratio of 50000 ppm and a modulation frequency of 30 kHz. Figure 4.9 shows its spectrum with spreading.

50000ppm

30kHz 50000ppm

30kHz

Figure 4.8 Control voltage of SSCG with 50000 ppm and 30 kHz spread

50000 ppm 50000 ppm

Figure 4.9 FFT of SSCG with 50000 ppm and 30 kHz spread

Third, Figure 4.10 shows the control voltage variation in SSC mode with a spread ratio of 5000 ppm and a modulation frequency of 150 kHz. Figure 4.11 shows its spectrum with spreading.

150kHz 5000ppm

150kHz 5000ppm

5000 ppm 5000 ppm

Figure 4.11 FFT of SSCG with 5000 ppm and 150 kHz spread

Finally, Figure 4.12 shows the control voltage variation in SSC mode with a spread ratio of 5000 ppm and a modulation frequency of 300 kHz. Figure 4.13 shows its spectrum with spreading.

300kHz 5000ppm

300kHz 5000ppm

Figure 4.12 Control voltage of SSCG with 5000 ppm and 300 kHz spread

5000 ppm 5000 ppm