Schottky Barrier MOSFET

The concept of Schottky-barrier metal–oxide–semiconductor field-effect transistors (SB-MOSFETs) which replace the heavily impurity-doped silicon in source/drain (S/D) regions with metallic material, typically silicides, was first proposed by Nishi in 1966. Japanese patent on the schottky barrier S/D was issued in 1970 [1].The first SB-MOSFET device was successfully fabricated by Lepselter and Sze in 1968, utilizing PtSi for the S/D regions [2]. Compared with conventional MOSFETs with the PN S/D junctions, the SB-MOSFETs have several favorable advantages such as short-channel effect (SCE) immunity, low extrinsic parasitic resistance, low thermal budget in fabrication, and superior scalability due to the atomically abrupt junctions formed at the silicide–silicon interface [3-4].The silicided junction depth can be narrowly controlled by the deposited metal thickness and annealing conditions (temperature and duration). Table 1-1 summarizes the characteristic comparison between SB-MOSFETs and conventional MOSFETs. In 1983, the SB pMOSFET was verified to eliminate the latch-up effect [5-6]. Nowadays, SB-MOSFETs have attracted much attention as promising candidates in future ultra-large-scale integrated circuit (ULSI) devices [7-8]. Furthermore, since the S/D formation is implemented at low temperature, typically below 600℃, the metal gate and high-k gate dielectric technologies can be viably incorporated in SB-MOSFETs [3].

Nevertheless, SB-MOSFETs usually exhibit an inferior on-state performance and

less steep switching characteristics than conventional MOSFETs. It is found that the Schottky barrier height (SBH) significantly affects the series resistances.For typical SB-MOSFETs, the on current is limited by carriers tunneling through the SB at the source end of the channel.A very low or even a negative SBH at source-side is favorable for the on-current to reach a comparable performance as conventional MOSFETs [9]. Also, SB-MOSFETs show ambipolar behavior if the barrier height for minority carrier at drain-side is not sufficiently high, which yields large and bias-dependent off-state leakage current [10], as shown in Fig. 1-1. The large leakage current attributed to hole (electron) tunneling from the drain side of n-type SB (p-type SB) devices can be a serious issue even with a high driving current. Figure 1-2 shows the band diagrams along the channel of an n-type SB device from source to drain when gate voltage is negatively biased.

In order to deal with the thorny problems of SB-MOSFETs mentioned above, it is desirable to provide some mechanisms to tailor the I-V characteristics, such as optimization of silicide materials and ingenious process designs. Several methods have been proposed to enhance the driving current. To date, PtSi and a rare-earth silicide, such as ErSix or YbSix, provide the lowest known SBHs to p- and n-type SB-MOSFETs, respectively, but their relatively low hole or electron SBH of about 220 meV still limits drastically the driving current [11-12]. Aside from the limited barrier height lowering, the noble metal materials are costly and will encounter difficulty for mass production. Recently, to overcome the aforementioned disadvantages while keeping the benefits of low S/D series resistance and ultra shallow junction, some novel technologies for Schottky harrier height (SBH) engineering are proposed and demonstrated, including dopant segregation technique[13], inserting a thin insulator between metal and silicon [12], and increasing the Si substrate doping [14], where the effective SBH can be significantly

reduced even to about 100 meV, and have the potential to achieve a driving current comparable to that of conventional MOSFETs. However, the serious ambipolar current is still a problem that needs to be resolved.

Previously, our group had proposed a novel Schottky-S/D TFT with a metal field plate or sub-gate lying on top of the passivation oxide used to create a field-induced-drain (FID) region [15]. The structure of the proposed SB device is illustrated in Fig. 1-3.The unique FID region reduces effectively the off-state leakage current (i.e., GIDL behavior), while maintaining a reasonable on-current. Depending on the sub-gate bias polarity, the device can exhibit either n-or p-channel transistor characteristics with either positive or negative sub-gate biases, respectively. In essence, the structure implies that the asymmetric S/D configuration can induce remarkable on-state current from source side and prohibit charge carriers from tunneling the sharp Schottky barrier at the drain side.

1.2 Overview of Nonvolatile Flash Memory

In recent years, the proliferation of portable electronics such as cell phones, palm top computers, and digital cameras has accelerated the adoption of silicon-based solid state storage cards in consumer markets. Semiconductor memories are generally categorized as random access memory (RAM) and read only memory (ROM).

Typically, devices belonging to RAM family are volatile; in other words, the memory cells do not retain the stored information when the power is turned off .On the other hand, the memory devices which retain information once the power supply is switch off are called nonvolatile memories (NVM). Fig. 1-4 shows the detailed subcategories of RAM and ROM families [16].

Of particular interest to us in this study is the subfamily of NVM known as

electrically erasable programmable ROM (EEPROM). Flash memory is a subset of EEPROM devices, since they are programmed and erased electrically but composed by single transistor cell. In flash memory, program operation can be done selectively at byte level but erase is done at block level from 512 bytes to full chip, which is the so-called “flash erase” process [17]. In the classification of flash memory, there have been basically two types of device structures. One is the floating gate (FG) structure and the other is discrete charge-trapping structure. The FG devices store charges in the polycrystalline silicon (poly-Si) FG which provides a continuous distribution of electronic states in energy for electron to be stored, while the discrete charge-trapping devices store charges in isolated deep-level traps contained in the storage medium like nitride or nano dots. Between the two charge storage devices, FG structure is the mainstream of flash memory technology to this date.

1.2.1 Floating Gate Flash Memory

In 1967, Kahng and Sze reported the first FG structure as a mechanism for nonvolatile information storage [18]. Since then, FG transistors have been adopted widely to store information for long periods in structures such as EPROMs, EEPROMs, and flash memories. To date, mass-produced nonvolatile memory devices are FG devices. Fig. 1-5 shows schematic cross-sectional view of a FG cell structure [17]. The FG is completely surrounded by dielectrics and electrically governed by a capacitively coupled control gate (CG). For the cell device,the FG acts as the storing medium in which charges are injected and maintained, allowing a modulation in the threshold voltage of the cell transistor. Integrity and maintenance of this energy barrier formed by the surrounding oxide is a necessary requirement of today’s FG technologies in order to attain non-volatility. Usually the gate dielectric between the transistor channel and the

FG is an oxide in the range of 8–10 nm and is called “tunnel oxide” since electron tunneling occurs through it. The dielectric that separates the FG from the CG is usually formed by a triple layer of oxide–nitride–oxide (ONO) sandwich. However, these devices have faced the dilemma between long-term non-volatility and high operating speed encountered in consecutive scaling down of the cell size. This issue is extremely challenging due to the limitations of scaling the tunnel oxide below 8 nm, cell to cell interference, and loss of control-gate to FG coupling [19-21].To improve program efficiency and reliability of FG-type devices, comprehensive research will be an important topic for next memory generation.

1.2.2 NOR Flash

The Flash memory was commercially introduced in the early 1990s and since that time it has been able to follow the Moore law or keep the scaling rules imposed by the market. Today, two types of flash memory can be considered as industry standard: the common-ground NOR flash and the NAND flash. The two types are distinctive in terms of density, performance, and operating characteristics [22].

While NAND flash memory has become a popular alternative in the implementation of storage systems, NOR flash memory has been widely used in embedded system as a code storage of portable electronic products, such as in cellular phones or notebooks. In general, the NOR cell is a FG-type MOS transistor, programmed by channel hot electrons injection (CHEI) and erased by Fowler–Nordheim (FN) tunneling. The progressive expansion and evolution of mobile applications ask for achieving high density and excellent performance of NOR flash memory. However, the most serious limitation in scaling of NOR flash memory cell utilizing CHEI programming is gate length reduction. As the memory cell is

scaled down and the gate is shorter, the memory cell’s break down voltage is degraded. In other words, NOR flash memory array is vulnerable to drain-to-source punch-through during CHEI programming of a cell in the same bit line. Conventional NOR flash memory requires high drain and gate voltages for the efficient generation and injection of hot electrons into the FG. Moreover, the drain voltage cannot be reduced below a Si- barrier height of 3.1 eV. According to the forecast of International Technology Roadmap of Semiconductors (ITRS) [23], when a conventional NOR flash memory cell is scaled down, the physical limit of the gate length is said to be around 65nm.

1.2.3 Reading Operation

One major requirement for memory is that the threshold voltage distributions for logical states (i.e.,“1” and “0”) must be sufficiently separated to avoid read errors.

The most prevailing way to determine the memory logical state is reading the current driven by the cell at a fixed gate bias. As schematically depicted in Fig. 1-6 [17], the two transfer curves which belong to the same memory cell exhibit different logical states at a fixed gate voltage, that is to say, the threshold voltage shift occurs when electron charge was stored in the FG memory. Furthermore, the threshold voltage shift is proportional to the stored electron charge. Once an acceptable amount of charge is programmed into the charge storage layer, a corresponding threshold voltage shift can effectively suppress the conduction current. Consequently, the current of the logic state “1” is very high, while the current of the logical state “0” is nearly zero, in the microampere scale.

1.3 Motivation

Since conventional NOR flash memory is programmed by the channel hot electron injection (CHEI) mechanism, where electrons must gain enough energy to surmount the oxide–silicon energy barrier, thanks to the electric field in the transistor channel between source and drain. However, the high programming operation voltage will contradict the scaling criterion as a result of inducing irretrievable punch-through effect. Moreover, the concept of green transistors is increasingly important so that a novel device technology that is friendlier to gate voltage as well as drain voltage scaling down should be developed.

Recently, Schottky-barrier transistor has attracted much attention due to its high-efficiency source-side injection characteristic [24]. In this thesis, an experimental investigation was undertaken to explore the source-side injection of hot electrons at low voltage. The large gate current will realize low power CHEI programming operation for the NOR flash.

Nevertheless, Schottky-barrier transistor suffers from inherently ambipolar conduction, thus the determination of memory logical states “1” or “0” will be perturbed. Fig. 1-7 illustrates the read error case when the GIDL current is mistaken for the driving current at a fix gate voltage and thus the logical states can not be unambiguously distinguished. Accordingly, to eliminate the undesirable ambipolar conduction of Schottky-barrier devices, a novel asymmetric S/D configuration is introduced in this thesis.

A novel double patterning technique was employed to fabricate the asymmetric S/D device [25]. The adoption of n⁺-doped drain will facilitate the suppression of reverse drain-side hole tunneling current and thus show unipolar transfer characteristics. For memory devices, the distinctive current read is favorable for determining logical state. Fig. 1-8 illustrates the normal reading operation of memory.

1.4 Thesis Organization

There are four chapters in this thesis. Chapter 1 begins with background on Schottky-barrier MOSFETs and nonvolatile flash memory, especially the FG structure.

In Chapter 2, it briefly describes the process technology related to the device fabrication and the process flow of asymmetrical (AS) SB TFT and ASSB-FG TFT memory, respectively. In Chapter 3, the basic electrical characteristics of the measured data are presented and discussed. Moreover, the preliminary programming results of ASSB-FG TFT memory are presented and analyzed. Finally, we summarize the major observations obtained in this study and give suggestions for future work in Chapter 4.

Table 1-1. Advantage of SB-MOSFFT over Conventional MOSFET

Chapter 2

Process Technology, Device Fabrication, Measurement Setup, and Carrier Transport Mechanisms

In this thesis, we conceive an innovative and advanced concept to realize FG memory with high programming speed and low power consumption. The fabrication of the novel asymmetric Schottky-barrier transistor involves several integrated circuits (ICs) technologies. A brief review of process technologies used in this experiment and the process flow of the proposed devices will be described in the next sections. Also, charge transport trough the tunnel dielectric is the basic mechanisms to achieve flash memory operation. We will discuss the most popular transport mechanisms of FG memory, including channel hot electron injection (CHEI), Fowler-Nordheim (FN) tunneling, and band-to-band tunneling (BTBT).

2.1 Review of Asymmetric Schottky-Barrier Transistors

In the late 1980s, an asymmetric Schottky-barrier MOSFET in which the source is made up of PtSi and the drain BF2+ doped silicon was investigated by Bing-Yue Tsui and Mao-Chieh Chen [26].The cross-sectional view of key process steps and the finished asymmetric structure is shown in Fig. 2-1 [26]. In the design of the proposed device process, the most critical step was the deionized water (DI water) rinsing step, as will be explained in the following. Briefly, after the drain-side implantation, wafers were then rinsed in DI water at 20~23℃ for 10 min. For the heavily doped poly-Si gate and drain regions, a thin native oxide layer would grow on the surface under this

rinse condition. Controlling the rinse time and water temperature carefully could induce a thin native oxide layer only on the heavily-doped gate and drain regions to hinder Pt from interacting with Si later. It should be noted that native oxide also serves as the role of gate sidewall spacer to prevent the bridging effect. In the experiment, an additional mask was used to cover the source region against drain implantation.Alignment of this mask is critical and thereby the proposed asymmetric device is difficult to scale down.

In this thesis, we propose a similar device structure having asymmetric S/D but with a more feasible process scheme. Specifically, we take advantage of a double-patterning technique recently developed by our group which employed twice I-line lithographic step to form asymmetric S/D regions [25]. Thanks to the accurate alignment, the gate length could scale down to nanoscale.

2.2 Double Patterning Technique

A double patterning lithography (DPL) technology using standard I-line lithography has been developed and proposed to shrink the gate length to 100 nm and below. The technique is capable of breaking through the resolution limit of single mask lithography using I-line stepper. DPL involves the partitioning of dense circuit patterns into two separate exposures patterning and is capable of improving the resolution and depth of focus (DOF) [27]. DPL is one of the most likely short-term solutions for keeping the pace of scaling beyond 22 nm node, since the EUV adoption timeline has been delayed [28-29]. Furthermore, DPL could be cleverly employed to fabricate asymmetric S/D device structures. In this study, a novel asymmetric SB transistor structure was designed and demonstrated successfully. To form asymmetric S/D junction, twice lithography steps with G1 mask and G2 mask were adopted as

schematically shown in Fig. 2-2 [25]. When defining the gate region, the first G1 mask covers the right part of active region in order to prevent poly-Si from dry etching and ion implantation. After doping the drain junction, the second G2 mask caps the left part of the active region and protects portion of poly-Si region remained after the previously etching. The overlapped region of the two masks thus defines the gate length.

2.3 Ni-silicide

Ni-monosilicide (NiSi) has been widely chosen and has become the most popular silicide material because of its superior properties over TiSi2 or CoSi2 for advanced integrated circuit technology [30-32], especially 65 nm node and beyond. During the silicidation, silicon consumption of the Ni process is the smallest among Ti, Co and Ni, which facilitates the formation of ultra-shallow S/D junction [33]. Silicon consumption is defined as the distance between the initial silicon/metal interface before the siliciation and the bottom of the silicide after it is formed, as illustrated in Fig. 2-3. There is little possibility for the Ni-silicide to be formed at the sidewall since Ni is the dominant diffusion species during the formation of silicide. Therefore, bridging effect between the gate electrode and S/D hardly occurs for the NiSi due to its reaction mechanism. Moreover, NiSi has wide silisidation range of 350–750℃ and is suitable for sub-100-nm technology node. Ni reacts with Si to form Ni-rich silicide (Ni2Si) at temperatures as low as 200℃, so the NiSi is typically formed by one-step rapid thermal annealing(RTA) at 400℃–700 ℃ for 30–60 s. The residual Ni can be selectively removed by wet etching in a mixture of H2SO4 and H2O2. Although one-step RTA could rapidly form NiSi, excess silicide reactionwas found for short channel device and thin active region [34-35]. When Ni silicidation of the thin S/D

regions is used with excess Ni film, lateral encroachment of Ni silicide under the sidewall spacers towards the channel could occur by means of the diffusion of Ni into silicon area. In view of the possibility of excess silicide encroachment toward the channel region, moderate annealing temperature and time is crucial. To effectively control the lateral growth, in this study we adopted a one-step RTA in vacuum chamber at 500℃ for 30 seconds.

2.4 Device Structure and Process Flow

2.4.1 Process Flow of Asymmetric Schottky-Barrier TFT (ASSB TFT) Devices

Fabrication flow of the ASSB TFT is illustrated in Figs. 2-4(a) ~ (g). Briefly, the process of all devices in this work started on 6-inch silicon wafers capped with a 250nm silicon dioxide layer. First, a 50 nm-thick undoped amorphous Si film was deposited by low pressure chemical vapor deposition (LPCVD) system at 550℃. To crystallize the amorphous Si film, the furnace annealing step was carried out at 600 ℃ for 24 hours in N2 ambient (i.e., solid-phase crystallization, SPC) [Fig. 2-4 (a)]. After patterning active regions by a standard I-line lithography step and a subsequent anisotropic reactive plasma dry etching, a TEOS gate oxide layer was deposited by LPCVD furnace at 700℃, on which a 120 nm-thick in-situ phosphorus-doped n⁺ poly-Si film was then deposited [Fig. 2-4 (b)]. In this experiment, the TEOS gate dielectrics were split into three thickness conditions, i.e., 10 nm, 15nm, and 20nm, respectively. Next, the first gate photolithography of G1 mask and anisotropic dry etching step were employed to define the drain side, and then drain implantation was conducted at an energy of 12keV and dose of 5E15 cm^-2 [Fig. 2-4 (c)]. The photoresist of G1 was then stripped. Subsequently, a 50 nm-thick TEOS oxide serving as hard

mask was deposited to protect the drain side from the following nickle silicidation annealing process [Fig. 2-4 (d)]. Then the second gate photolithography of G2 mask was carried out to define the real gate region. After continuously dry etching the hard mask oxide and poly-Si, the photoresist of G2 was stripped [Fig. 2-4 (e)]. Afterwards, a sidewall spacer was formed by a 20 nm-thick nitride deposition and subsequent dry

mask was deposited to protect the drain side from the following nickle silicidation annealing process [Fig. 2-4 (d)]. Then the second gate photolithography of G2 mask was carried out to define the real gate region. After continuously dry etching the hard mask oxide and poly-Si, the photoresist of G2 was stripped [Fig. 2-4 (e)]. Afterwards, a sidewall spacer was formed by a 20 nm-thick nitride deposition and subsequent dry