Thesis Organization

There are four chapters in this thesis. Chapter 1 begins with background on Schottky-barrier MOSFETs and nonvolatile flash memory, especially the FG structure.

In Chapter 2, it briefly describes the process technology related to the device fabrication and the process flow of asymmetrical (AS) SB TFT and ASSB-FG TFT memory, respectively. In Chapter 3, the basic electrical characteristics of the measured data are presented and discussed. Moreover, the preliminary programming results of ASSB-FG TFT memory are presented and analyzed. Finally, we summarize the major observations obtained in this study and give suggestions for future work in Chapter 4.

Table 1-1. Advantage of SB-MOSFFT over Conventional MOSFET

Chapter 2

Process Technology, Device Fabrication, Measurement Setup, and Carrier Transport Mechanisms

In this thesis, we conceive an innovative and advanced concept to realize FG memory with high programming speed and low power consumption. The fabrication of the novel asymmetric Schottky-barrier transistor involves several integrated circuits (ICs) technologies. A brief review of process technologies used in this experiment and the process flow of the proposed devices will be described in the next sections. Also, charge transport trough the tunnel dielectric is the basic mechanisms to achieve flash memory operation. We will discuss the most popular transport mechanisms of FG memory, including channel hot electron injection (CHEI), Fowler-Nordheim (FN) tunneling, and band-to-band tunneling (BTBT).

2.1 Review of Asymmetric Schottky-Barrier Transistors

In the late 1980s, an asymmetric Schottky-barrier MOSFET in which the source is made up of PtSi and the drain BF2+ doped silicon was investigated by Bing-Yue Tsui and Mao-Chieh Chen [26].The cross-sectional view of key process steps and the finished asymmetric structure is shown in Fig. 2-1 [26]. In the design of the proposed device process, the most critical step was the deionized water (DI water) rinsing step, as will be explained in the following. Briefly, after the drain-side implantation, wafers were then rinsed in DI water at 20~23℃ for 10 min. For the heavily doped poly-Si gate and drain regions, a thin native oxide layer would grow on the surface under this

rinse condition. Controlling the rinse time and water temperature carefully could induce a thin native oxide layer only on the heavily-doped gate and drain regions to hinder Pt from interacting with Si later. It should be noted that native oxide also serves as the role of gate sidewall spacer to prevent the bridging effect. In the experiment, an additional mask was used to cover the source region against drain implantation.Alignment of this mask is critical and thereby the proposed asymmetric device is difficult to scale down.

In this thesis, we propose a similar device structure having asymmetric S/D but with a more feasible process scheme. Specifically, we take advantage of a double-patterning technique recently developed by our group which employed twice I-line lithographic step to form asymmetric S/D regions [25]. Thanks to the accurate alignment, the gate length could scale down to nanoscale.

2.2 Double Patterning Technique

A double patterning lithography (DPL) technology using standard I-line lithography has been developed and proposed to shrink the gate length to 100 nm and below. The technique is capable of breaking through the resolution limit of single mask lithography using I-line stepper. DPL involves the partitioning of dense circuit patterns into two separate exposures patterning and is capable of improving the resolution and depth of focus (DOF) [27]. DPL is one of the most likely short-term solutions for keeping the pace of scaling beyond 22 nm node, since the EUV adoption timeline has been delayed [28-29]. Furthermore, DPL could be cleverly employed to fabricate asymmetric S/D device structures. In this study, a novel asymmetric SB transistor structure was designed and demonstrated successfully. To form asymmetric S/D junction, twice lithography steps with G1 mask and G2 mask were adopted as

schematically shown in Fig. 2-2 [25]. When defining the gate region, the first G1 mask covers the right part of active region in order to prevent poly-Si from dry etching and ion implantation. After doping the drain junction, the second G2 mask caps the left part of the active region and protects portion of poly-Si region remained after the previously etching. The overlapped region of the two masks thus defines the gate length.

2.3 Ni-silicide

Ni-monosilicide (NiSi) has been widely chosen and has become the most popular silicide material because of its superior properties over TiSi2 or CoSi2 for advanced integrated circuit technology [30-32], especially 65 nm node and beyond. During the silicidation, silicon consumption of the Ni process is the smallest among Ti, Co and Ni, which facilitates the formation of ultra-shallow S/D junction [33]. Silicon consumption is defined as the distance between the initial silicon/metal interface before the siliciation and the bottom of the silicide after it is formed, as illustrated in Fig. 2-3. There is little possibility for the Ni-silicide to be formed at the sidewall since Ni is the dominant diffusion species during the formation of silicide. Therefore, bridging effect between the gate electrode and S/D hardly occurs for the NiSi due to its reaction mechanism. Moreover, NiSi has wide silisidation range of 350–750℃ and is suitable for sub-100-nm technology node. Ni reacts with Si to form Ni-rich silicide (Ni2Si) at temperatures as low as 200℃, so the NiSi is typically formed by one-step rapid thermal annealing(RTA) at 400℃–700 ℃ for 30–60 s. The residual Ni can be selectively removed by wet etching in a mixture of H2SO4 and H2O2. Although one-step RTA could rapidly form NiSi, excess silicide reactionwas found for short channel device and thin active region [34-35]. When Ni silicidation of the thin S/D

regions is used with excess Ni film, lateral encroachment of Ni silicide under the sidewall spacers towards the channel could occur by means of the diffusion of Ni into silicon area. In view of the possibility of excess silicide encroachment toward the channel region, moderate annealing temperature and time is crucial. To effectively control the lateral growth, in this study we adopted a one-step RTA in vacuum chamber at 500℃ for 30 seconds.

2.4 Device Structure and Process Flow

2.4.1 Process Flow of Asymmetric Schottky-Barrier TFT (ASSB TFT) Devices

Fabrication flow of the ASSB TFT is illustrated in Figs. 2-4(a) ~ (g). Briefly, the process of all devices in this work started on 6-inch silicon wafers capped with a 250nm silicon dioxide layer. First, a 50 nm-thick undoped amorphous Si film was deposited by low pressure chemical vapor deposition (LPCVD) system at 550℃. To crystallize the amorphous Si film, the furnace annealing step was carried out at 600 ℃ for 24 hours in N2 ambient (i.e., solid-phase crystallization, SPC) [Fig. 2-4 (a)]. After patterning active regions by a standard I-line lithography step and a subsequent anisotropic reactive plasma dry etching, a TEOS gate oxide layer was deposited by LPCVD furnace at 700℃, on which a 120 nm-thick in-situ phosphorus-doped n⁺ poly-Si film was then deposited [Fig. 2-4 (b)]. In this experiment, the TEOS gate dielectrics were split into three thickness conditions, i.e., 10 nm, 15nm, and 20nm, respectively. Next, the first gate photolithography of G1 mask and anisotropic dry etching step were employed to define the drain side, and then drain implantation was conducted at an energy of 12keV and dose of 5E15 cm^-2 [Fig. 2-4 (c)]. The photoresist of G1 was then stripped. Subsequently, a 50 nm-thick TEOS oxide serving as hard

mask was deposited to protect the drain side from the following nickle silicidation annealing process [Fig. 2-4 (d)]. Then the second gate photolithography of G2 mask was carried out to define the real gate region. After continuously dry etching the hard mask oxide and poly-Si, the photoresist of G2 was stripped [Fig. 2-4 (e)]. Afterwards, a sidewall spacer was formed by a 20 nm-thick nitride deposition and subsequent dry etching step [Fig. 2-4 (f)]. The nitride spacers were slim so that S/D silicide reaches the gate edge due to a lateral diffusion of the NiSi under the spacers, which is crucial for the electrical performance improvement. After a diluted HF dip to remove the thin oxide layer on the source side, a 30nm-thick nickel layer was deposited immediately by physical vapor deposition (PVD) system, followed by a rapid thermal annealing (RTA) step at 500 ℃for 30 seconds for forming Ni-silicide (NiSi) metallic junction at the source region. The initial Si film at the source side is fully silicided to form NiSi which encroaches into the gate edge. A wet etching step in a mixture of H2SO4 and H2O2 was then used to remove the unreacted metal [Fig. 2-4 (g)]. It should be noted that no extra drain dopant activation step was necessary since the process temperature of hard mask oxide and nitride spacer was higher than 700℃ and the process time was sufficient for dopant annealing. For comparison, conventional n-type TFTs with phosphorus-doped S/D regions were fabricated using the same process conditions as described previously except that the silicide drain was replaced with ion implantation, as shown in Fig. 2-5. Finally, all devices received a standard back-end processing to completion. A post-metal annealing at 400℃ in forming gas for 30 min was performed before electrical measurements.

2.4.2 Process Flow of ASSB-Floating-Gate (FG) TFT Memory

Devices

Schematic structure of the proposed ASSB-FG TFT device is shown in Fig. 2-6.

The structure and fabrication are nearly identical to those of ASSB TFT except the gate stack composition. In this configuration, a 10 nm-thick TEOS tunnel oxide and 60 nm-thick in-situ phosphorus-doped n⁺ poly-Si FG were deposited sequentially.

Note that since the FG layer is a conductive material, the injected carriers can distribute uniformly in the storage layer. Afterwards, a 15 nm-thick TEOS oxide was deposited for the purpose of preventing charge loss from the FG charge storage layer.

Then a 60 nm-thick in-situ phosphorus-doped n⁺ poly-Si film was deposited serving as the control gate. All deposition processes mentioned above were carried out under LPCVD system. The other process steps were identical to those described in previous sections. The control group of conventional n-type FG TFT memory was also fabricated by doping the S/D junction with phosphorus ions, as shown in Fig. 2-7.

2.5 The Measurement Setup

Electrical characteristics of the fabricated devices in this thesis are mainly characterized by automated measurement setup consisted of HP 4156 semiconductor parameter analyzer, a pulse generator Agilent-8110A, and a Visual Engineering Environment (VEE). These equipments integrated in the system are controlled by the interactive characterization software (ICS) program. In the measurement environment, the humidity is precisely regulated by dehumidifiers, while the temperature is also accurately controlled by a temperature regulated heater to maintain the measurement temperature at 25 .℃

2.6 Charge Transport Mechanisms

Basic operations of program/erase that are most commonly used in actual flash memory will be reviewed, including channel hot electrons injection (CHEI), Fowler-Nordheim (FN) tunneling, band-to-band tunneling (BTBT). The three writing schemes correspond to different physical principles. It is interesting to note that the three mechanisms have been thoroughly investigated in order to avoid severe degradation results in MOSFETs. In flash memory, however, they are exploited to execute program/erase operation effectively. In the following sub-sections we will sketch these charge injection mechanisms, respectively.

2.6.1 Channel Hot Electrons Injection

The CHEI mechanism has been widely used for nonvolatile memory devices. Fig.

2-8(a) shows the mechanisms of hot-carrier injection. When the drain voltage is large enough to induce a high lateral electric field near the drain side, i.e., VD ≧ VDSAT = VG -Vth , pinch-off occurs close to drain region and major voltage drop along the channel occurs in the region between the pinch-off point and the drain junction. The channel electrons can gain energy far greater than the thermal-equilibrium value.

Actually, the electrons energy distribution shows Maxwell-Boltzmann approximation, thus only the tail part of electrons can become sufficiently “hot” to surmount the barrier between oxide and silicon conduction band edges under a sufficiently high gate voltage, which contributes to the gate current, as illustrated in Fig. 2.8(b). Fig.

2-9 shows the electrons energy distribution [36]. Note that, the energy distribution is a function of lateral field. In the meantime, the newly generated hot electrons can ionize other atoms, leading to the so-called “impact ionization” effect. Due to the continuous collisions, a large number of electron-hole pairs can be generated. These generated secondary hot electrons can also be swept to the drain side while the holes will drift

into the substrate in an n-type transistor. In brief, two models have developed to describe the hot electron injection phenomena: the lucky electron model [37] and the energy transport model [38-40].

(1) The lucky electron model: Chenming Hu was first to use the “lucky electron”

concept to empirically explore a gate current. The electrons acquire enough energy from the lateral electric field to surmount the oxide–silicon energy barrier without energy stripping collision in the channel and then be emitted into the gate oxide. In essence, the model is based on the probability that electron is lucky enough to travel several times the mean free path without scattering, eventually crossing the potential barrier. Although this simple model imposes some disagreements between theory and experimental results, it allows a straightforward and quite rough simulation of the gate current.

(2) The energy transport model: The model establishesa more rigorous theory based on a nonlocal relation between the “effective electron temperature (Te)” and the drift field. The nonlocal relationship between Te and the electric-field distribution is given by Takeda [41] as follows:

0

where q is the elementary charge, Exs is the x-component of the electric field, k is Boltzmann's constant,v = 10_s ⁷ cm/s is the saturated electron velocity, and

e= 8x10^-14 s is the energy relaxation time.

The heated electron gas is injected into gate dielectric. Richardson's equation in the following form can now be used to calculate gate current due to hot electrons which is dependent on electron temperature “Te”:

( ) ( )[ ( ) / 2 *] exp[

/ ( )]

g b

J x  qNs x kTe x nm  q  kTe x

Here, N(x) is minority carrier concentration,m* is the effective mass of an electron, and_bis oxide barrier height.

2.6.2 Fowler-Nordheim Tunneling

In classical theory, electrons are completely confined within a potential barrier when carrier energy is lower than the potential barrier height. However, in quantum mechanics, an electron can be represented by a wavefunction, thus there is a finite probability that the charge will penetrate through the potential barrier and appear in the classical forbidden region. This phenomenon is called tunneling and it contradicts classical theory. Tunneling through the oxide can be attributed to diverse carrier injection mechanisms which depend on the oxide thickness and the applied electric field or voltage. Generally, the quantum tunneling mechanism can dominate the carrier transport when the potential barrier is sufficiently thin and it can be mainly categorized into direct tunneling (DT) and Fowler-Nordheim (FN) tunneling. FN tunneling occurs when a large electric field (Eox) is imposed on the tunneling oxide and thus electrons can tunnel through a triangular energy barrier with a width dependent on the applied bias. The FN tunneling phenomenon is given by

ox oxide. The energy band diagram of electrons injection from Si substrate to oxide under FN tunneling is shown in Fig. 2-10 (a). On the other hand, when the electric field built in tunneling oxide is lower than

ox

q t

 , the tunneling barrier is trapezoidal as

illustrated in Fig. 2-10(b) and the electrons will pass through tunneling oxide and inject into the gate directly. If the oxide is ultra thin (i.e., 3nm below), the DT

mechanism dominates over the FN tunneling. Because the reliability issue of silicon-oxide-nitride-oxide-silicon (SONOS) memory is ascribed to the leakage due to DT, the tunneling oxide thickness can not scale below 3nm.

2.6.3 Band-to-Band Tunneling

When a highly negative voltage relative to n⁺drain region is applied to the gate, a deep depletion region occurs underneath the gate-to-drain overlap region. Because of the serious band bending in the deep depletion region induced by a large electric field, electrons may tunnel directly from valance band through a potential barrier into conduction band. Simultaneously, the majority of the holes flow into the substrate due to the lateral field and are observed as the substrate current in bulk MOSFETs. In the course of BTBT, electron-hole pairs are generated and they are “cold” [42]. A part of the created holes will acquire enough energy from the lateral electric field without suffering any collision to surmount the Si-SiO2 energy barrier, thus contributing to the gate leakage current. Note that in this special case, the potential barrier has a triangular shape with the maximum height given by the energy gap. This tunneling process is schematically shown in Fig. 2-11.

2.6.4 Summary

For conventional NOR flash memory, programming is performed by CHEI near the drain side. However, the drain-side hot electrons suffer from the conflict between favorable vertical oxide field and maximum lateral drain field, thus the injection efficiency is very low in highly scaled devices. In order to solve the lower program-efficiency problem, source-side-injection (SSI) scheme was developed for high-speed and low-voltage operation. A FG memory device with high programming

efficiency and low-power consumption is proposed in this study.

Chapter 3

Results and Discussion

3.1 Fundamental Electrical Characteristics

Devices of asymmetric S/D configuration can be operated in two different modes, that is to say, forward and reversed modes, respectively. For the forward mode, the Ni-silicided junction is used as the source while the n⁺-doped junction is used as the drain. On the contrary, the reverse mode measurements were carried out by interchanging the source and drain terminals. Fig. 3-1 illustrates the bias configurations of the ASSB-TFT under forward and reverse operation modes. The experimental transfer characteristics of n-type asymmetric Ni-silicided SB-TFTs are discussed in the following paragraphs.

Figs. 3-2 (a) and (b) show the transfer characteristics of n-type ASSB-TFT devices operated under forward mode with nominal channel length of 0.5 μm and 1 μm, respectively. The drain voltage varies from 0.1V to 1.6V with 0.5V voltage steps.

It is obvious that both devices exhibit a two-step subthreshold swing (SS) (dashed line in Fig. 3-2) with increasingly positive gate voltage (Vg), a feature significantly different from that of conventional MOSFETs, i.e., doped S/D-junctions devices. Such a phenomenon originates from the competition of two different carrier injection

mechanisms, thermionic emission current (J_th) and tunneling current (J_tn) [43], which are conceptually illustrated with the band diagrams shown in Fig. 3-3. As can be seen in the figure, in the subthreshold regions, as the applied Vg is low, thermionic emission current (Jth) dominates the conduction, so only carriers with energy greater than the Schottky barrier height (SBH) contribute to the current, as schematically

displayed in blue in the figure. When Vg is increased to the level Vg = V1, the band of the channel near the source junction becomes flat (dashed line in Fig. 3-3). When Vg

further increases over V1, the current now consists of both the J_th and the J_tn components, represented by the red lines in Fig. 3.3. With a sufficiently high Vg, tunneling current dominates the current flow as the Schottky barrier is thinned.

In brief, when the potential barrier is higher than the SBH at the source side, the thermionic current dominates and thus the SS is nearly a constant. However, when the device is turned on, the main increase in current arises from the tunneling through the SB at the source and is strongly dependent on the shape of the SB which is modulated by Vg. The tunneling current is a function of the SBH between the metal and the semiconductor, the gate dielectric thickness and gate voltage.Fig. 3-4 shows transfer characteristics of devices operated under the forward mode with different gate oxide thicknesses. It can be seen that, with the increase in oxide thickness, the drain current is lowered and thus degrades the device performance. On the other hand, the

In brief, when the potential barrier is higher than the SBH at the source side, the thermionic current dominates and thus the SS is nearly a constant. However, when the device is turned on, the main increase in current arises from the tunneling through the SB at the source and is strongly dependent on the shape of the SB which is modulated by Vg. The tunneling current is a function of the SBH between the metal and the semiconductor, the gate dielectric thickness and gate voltage.Fig. 3-4 shows transfer characteristics of devices operated under the forward mode with different gate oxide thicknesses. It can be seen that, with the increase in oxide thickness, the drain current is lowered and thus degrades the device performance. On the other hand, the