Chapter 4 Conclusions and Future Work
4.2 Future Work
The preliminary investigation of ASSB-TFT and the realization of ASSB-FG memory with source-side injection have been studied in this thesis. In order to further promote the device performance and optimize the material characteristics, more efforts are needed. The following is a list of the suggested future work.
1. In this thesis, we have fabricated our devices on poly-Si channel prepared by solid-phase crystallization (SPC) method. However, the inherent properties (such as the number, location, size, and orientation of the grain boundaries) of the polycrystalline material could have great influences on the device characteristics.
To further improve device performance, the same structure and concept could be extend to single-crystalline silicon channel, including conventional bulk MOS or ultrathin body (ULB) silicon on insulator (SOI) substrates. Moreover, there are still other methods to enlarge grain size and reduce the defect in grain boundaries.
The most promising recrystallization methods, such as excimer laser annealing (ELA) and metal-induced lateral crystallization (MILC) may be integrated with the ASSB structure for producing SOI-like substrate.
2. NiSi was chosen as the silicide material because of its superior properties as described previously. However, NiSi is a mid-gap silicide with an experimental Schottky barrier height (SBH) of 0.65 eV for electrons, the on-current is limited by the tunneling through the Schottky barrier at the source. According to investigation, PtSi for p-type SB devices provide the barrier heights of 0.15 ~ 0.27eV [50]. In this regard, PtSi will be a promising candidate for future ASSB devices. In addition, some optimized silicidation techniques could also be attempted to tune the effective Schottky barrier height, including implantation-to-silicide (ITS) method and dopant segregation (DS) method.
3. Three TEOS oxide thickness was compared and characterized in this work, but the gate oxide thickness is not optimized yet. To induce the most efficient gate current for the future source-side-injection memory, the optimization of EOT for gate oxide is indispensable. However, how to enhance the quality of TEOS oxide is still an important issue that needs to be addressed. On the other hand, the substitution of the gate oxide by high-κ material, such as HfO2, can provide a thin EOT to enhance the vertical electric field across for high injection efficiency.
4. Although the undesirable ambipolar conduction is alleviated, we found that the GIDL still occurs and increases with Vg and Vd. Hence, nanowire (NW) structure is a viable application to our device designs, due to the much reduced cross-sectional area of leakage path. In this regard, a new mask layout is demanded.
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Fig. 1-1 Ambipolar conduction of the Schottky barrier device.
Fig. 1-2 The Band diagrams along the channel of an n-type SB device from source to drain when gate voltage is negatively biased.
Fig. 1-3 Cross-sectional view of the proposed TFT device [15].
Fig. 1-4 Detailed subcategories of RAM and ROM memory families [16].
Fig.1-5 Schematic cross section of a FG memory [18].
Fig.1-6 The reading operation of FG memory [18].
Fig. 1-7Schematic illustration of the logical state which can not be successfully read.
Fig. 1-8 Schematic illustration of the normal reading operation of memory.
Fig. 2-1 The cross-sectional view of the rinsed asymmetric Schottky barrier PMOS process sequence and the finished structure [26].
Fig.2-2 The top view of the double patterning layout. The gate region is determined by the overlapped portion of the two masks [25].
Fig.2-3 Illustration explains silicon consumption.
(a)
(b)
(c) (d)
(e) (f)
(g)
Fig. 2-4 Process flow of ASSB TFT. (a) α-Si layer deposition and SPC on wet oxide. (b) After defining the active region, deposition of TEOS gate oxide and in-situ doped poly gate. (c) G1 mask definition and drain side implantation. (d)
After stripping of PR, deposition of hard mask. (e) Defining the real gate region by G2 mask. (f) Deposition of nitride film and then sidewall spacer formation by RIE. (g) Formation of NiSi at source side.
Fig. 2-5 The cross-sectional view of conventional n-type TFT structure.
Fig. 2-6 The cross-sectional view of ASSB-FG TFT memory.
Fig. 2-7 The cross-sectional view of conventional n-type FG TFT memory.
(a)
(b)
Fig. 2-8 (a) Channel hot electrons caused by strong lateral electrical field in pinch-off region. (b) Hot electrons gain sufficient energy and are injected into gate.
Fig. 2-9 Electrons are “heated” by the high lateral electric field. The energy distribution is a function of lateral field. Each of these functions needs to be specified in each point of the channel [36].
(a) (b)
Fig. 2-10 (a)Fowler-Nordheim tunneling occurs when ox
ox
E q t
( ox ox
ox
E V
t ) (b) Direct tunneling occurs when oxide is thin enough.
(a)
(b)
Fig. 2-11.Band-to-Band Tunneling (BTBT). (a) Deep depletion appears in n+
drain region overlapped by gate. (b) Main tunneling mechanism occurs in deep depletion region.
(a)
(b)
Fig. 3-1 Bias configurations of n-type Ni-silicided ASSB-TFT under (a) forward and (b) reverse operation modes, respectively.
(a)
(b)
Fig. 3-2 Transfer characteristics of ASSB-TFTs under forward operation mode with channel length of (a) 0.5 μm and (b) 1 μm.
Fig. 3-3 Conceptual energy diagrams and transfer characteristics of silicided-source SB-MOSFETs to explain the dominant carrier injection mechanisms.
Fig. 3-4 Transfer characteristics of ASSB-TFTs under forward operation mode with oxide thickness of 10nm, 15nm and 20 nm.
Fig. 3-5 Transfer characteristics of ASSB-TFTs operated in both modes together with those of the conventional n-type TFT structure for comparison.
(b)
Fig. 3-6. Energy band diagrams of conventional SB-MOSFETs at various bias conditions. (a) no voltage is applied to the drain and the gate and thus no any current can tunnel through Schottly barriers. (b) At the on-state (Vgs>0, Vds>0), electrons can easily tunnel through the thinner source-side SB. (c) At the off-state, holes can easily tunnel through the thinner drain-side SB, leading to GIDL-like current.
(a)
(b)
(c)
Fig. 3-7 Energy band diagrams of n-type ASSB-TFT device at various bias conditions.(a) no voltage is applied to the drain and the gate and thus no any current can be observed. (b) At the on-state (Vgs>0, Vds>0), electrons can easily tunnel through the thinner source-side SB. (c) At the off-state, the n+ Si band gap effectively block hole tunneling.
Fig. 3-8The cross-sectional view of p-type ASSB-TFT structure.
Fig. 3-9 Transfer characteristics of p-type ASSB-TFT operated in both modes.
Fig. 3-10 Transfer characteristics of p-type and n-type ASSB-TFT operated in forward modes.
Fig. 3-11 Gate current versus drain voltage characteristics as a function of gate voltage operated in forward mode.
Fig. 3-12 Schematic illustration of the energy band diagram for both the ASSB-TFT device and the conventional device along the channel direction.
Fig. 3-13 Output characteristics of an ASSB-TFT operated under forward mode.
Fig. 3-14 Sub-threshold transfer characteristics of an ASSB-TFT operated in forward modes before and after dynamic electrontrapping.
Fig. 3-15 Gate current versus drain voltage characteristics as a function of gate voltage for an ASSB-TFT operated in reverse mode.
Fig. 3-16 Gate current versus drain voltage characteristics of a conventional device as a function of gate voltage.
Fig. 3-17 Output characteristics of an ASSB-TFT in reverse mode and a conventional control device. The gate length L and width W are 1 and 10 um, respectively.
Fig. 3-18 Output characteristics of an ASSB-TFT in reverse mode. The gate length L and width W are 5 and 10 um, respectively.
Fig. 3-19 Schematic illustrations of the charge injection points for source-side hot electrons (a) and FN tunneling (b).
(a)
(b)
(c)
(d)
(e)
Figs. 3-20 Gate current versus drain voltage characteristics as a function of gate voltage for an ASSB-TFT under forward operation mode with channel lengths of (a) 0.5μm (b) 1μm (c) 2μm (d) 5μm (e) 10μm.
(a)
(b)
(c)
(d)
Figs. 3-21 Gate current versus drain voltage characteristics for ASSB-TFTs with various channel lengths at the Vg of (a) 5V, (b) 6V, (c) 7V, and (d) 8V, respectively.
Fig 3-22. The plot of gate current versus channel length as a function of Vg at Vd = 0V.
Fig. 3-23 Gate current versus drain voltage characteristics of ASSB-TFT devices with oxide thickness of 10nm and 15 nm, respectively.
Fig. 3-24.Comparisons of gate current for an ASSB-TFT operated in two modes, together with its conventional control device.
Fig. 3-25. Transfercharacteristics of an ASSB-FG device before and after programming operation.
Fig. 3-26 Programming characteristics of ASSB-FG memory devices with different drain biases and Vg = 8V.
(a)
(b)
Fig. 3-27 Programming characteristics of (a) ASSB-FG memory and (b) conventional FG memory with different bias conditions.
Fig. 3-28 Cross-sectional TEM image of the ASSB-FG memory device along the channel direction. From the high-solution inset, it can be seen that an offset region exists between the NiSi source and the poly-Si channel (indicated by the double-head arrows).