Summary

Here we brief summarize the experiment result from this experiment in this study

1. Cell 1, cell 2 and cell 3 are failed at TCT test due to solder joint crack, the result shows the joint strength is not enough to sustain the stress from temperature cold to hot change.

2. From the result of lifetime prediction, cell 1, cell 4, cell 5 and cell 6 meet the base line - Ten years normal use requirement, even cell 4 and cell 6 can meet twenty years high level requirement.

3. The weak points for cell 1, 2 and 3 are solder-joint layers. From the failure analysis, the bonding layer crack is observed after stress test. The cause is come from the good wetting performance on lead frame surface- PPF to solder paste. The solder paste is bled out after IR reflow process and caused lower thickness of joint layer.

4. Cell 4, cell5 and cell 6 all got good results on die shear strength test, and the result is positive correlation to the TCT test.

5. Compared to the six cells on reliability tests, the solder paste with higher content silver has better test result.

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Chap 5. Summary and Future Work

In this study, we evaluate the surface mount assembly on flip chip CSP package, and we find three cells of total six cells can meet the requirement of the reliability test and product lifetime in normal use condition at least ten years.

The elements for successful cells are pure copper lead frame surface treatment with each one of SAC 305, SAC 300 and SAC405 (cell 4, cell5, cell 6), that is because the solder paste is restricted in the printing land area after IR reflow process, and have a good support on the package.

For the PPF treatment lead frame, the solder paste spreads out of the printing land area and causes lower thickness in the solder joint layer, this is also the reason to explain the lower shearing test compared to other cells.

We found the best result for the reliability performance is the one with Sn 95.5%/ Ag 4%/ Cu 0.5% solder paste. This is verified on pure copper lead frame but for the PPF lead frame, due to there is a noise (solder paste bleed) on the test, so it is difficult to analyze the trend.

Based on the evaluation result, the SMT process is workable on flip chip CSP package, and can reach the reliability target. With this method application, this process requires specific controls for better yield performance.

1. Opening definition on solder paste printing stencil

2. The land opening design on PPF surface should be considered, an obstructive area on inner lead or finger is needed.

3. Copper bump pitch > 80um is preferred for the process due to Chip bonding accuracy requirement (+- 15 um)

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For future work, we plan to apply this method on SiP package with thin thickness and propose to integrate more components in substrate base. Since the thickness of cell phone is from 12mm to 7 mm, it should be a big challenge on package assembly in near future.

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Bibliographies

1. http:// www.wisegeek.com/what-is-flip-chip-technology.htm 2. http:// en.wikipedia.org/wiki/Flip_chip

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4. Ikuo Shohji, Satoshi Tsunoda, Hirohiko Watanabe, Tatsuhiko Asai and Megumi Nagano, Reliability of Solder Joint with Sn–Ag–Cu–Ni–Ge Lead-Free Alloy under Heat Exposure Conditions, Materials Transactions, Vol. 46, No. 12 (2005)

5. Ranjit Pandher, Tom Lawlor, Effect of Silver in common lead-free alloys, Cookson Electronics Assembly Materials, 109 Corporate Blvd., South Plainfield, NJ 07080

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11. Joint Industry Standard IPC/JEDEC J-STD-020D.1, March 2008, page 1 and 6

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Vol.104, (1982) pp. 12-17.

13. Changwoon Han and Byeongsuk Song, Development of Life Prediction Model for Lead-free Solder at Chip Resistor, Electronics Packaging Technology Conference, 2006 14. http://www.jedec.org/standards-documents/results/reliability

15. MyoungSu Chae, Eric Ouyang, Strip Warpage Analysis of a Flip Chip Package Considering the Mold Compound Processing Parameters, 2013 Electronic Components and Technology Conference

16. Wen-chin Lin, Determination of the Influential Factors in Manufacturing of Printed Circuit Board, 國立中央大學工業管理研究所碩士論文, 2008

17. R. W. Kay, E. de Gourcuff and M. P. Y. Desmulliez, Stencil Printing Technology for Wafer Level Bumping at Sub-100 Micron Pitch using Pb-Free Alloys, 2005 Electronic Components and Technology Conference

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Appendix 1

MIL-STD/MIL-STD-883E method 2019.8, the die shearing test criteria

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Appendix 2

The environment requirement for electronic component