II. Motivation and Theory
2.3 Reliability test
2.3.2 Stress test
2-3-2 Stress test
The purpose of stress test is to precipitate failures in an accelerated manner compared to normal use conditions. Test units are subjected to higher than usual levels of one or more accelerating variables such as temperature, humidity, voltage and current. Then the test results are used to analysis packaging failures or predict life of the units at use conditions. Anand model[12] was employed to represent the constitutive equation of solders in stress model and developed to life prediction model in the accelerated thermal test. [13]
There are many industry-standard package-level reliability tests. The test is chosen based on the failure mechanism, as different stress tests accelerate different failure mechanisms. It is also important to select test methods which are as standardized as possible in consideration of test reproducibility, cost effectiveness, data compatibility and other factors [14]. These tests are described as below.
1. Biased Highly Accelerated Stress Test (HAST) (JESD22-A110)
The purpose is to simulate extreme operating conditions. Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are subjected to bias while the devices are in the chamber. The devices are then ATE tested for electrical failures. Variables: Temp = 130°C / Humidity = 85% RH/
Time = 96 hours
2. Temperature Cycle Test (TCT) (JESD22-104)
The purpose is to accelerate the effects of thermal expansion mismatch among different components of the package and circuit. It is used to determine package resistance from high temperature to low temperature and to temperature changes during
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transportation and use.
The devices are ATE tested for function verification. Failed devices are checked for interface cracks. Variables: Temp = 150°C (top) and -65° C (bottom)
3. Pressure Cooker Test (PCT) (JESD22-A102)
The purpose is to test moisture resistance of plastic encapsulated devices. Devices are baked in an autoclave (on a tray) at high temperatures and humidity for an extended period of time under static conditions. An ATE test is performed after the autoclave.
Failed devices are checked for delamination, shorts, etc.
Variables: Temp = 121°C / Pressure = 15 Psi / Humidity = 100 % RH 4. High Temperature Storage (HTS) (JESD22-A103)
The purpose is to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.
Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures. Variables: Temp
= 150°C / Time = 1000 hours
5. Temperature Humidity Bias (THB) (JESD22-A101)
The purpose is to determine device/package resistance to prolonged temperature, humidity, and electrical stress. Devices are baked in an oven at extreme temperature and humidity for various lengths of time. The devices are subjected to maximum differential bias on alternating pins while the devices are in the oven. The devices are then ATE tested for electrical failures.
Variables: Temp = 85°C / Humidity = 85% RH.
6. Unbiased Highly Accelerated Stress Test (UHAST) (JESD22-A118) The purpose is to simulate extreme operating conditions. Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The
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devices are then ATE tested for fuction verification.
Variables: Temp = 130°C / Humidity = 85% RH.
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Chap 3. Evaluation plan and procedure
The detail evaluation plan and the procedure of the test sample manufacturing are described in this chapter. We use the design of experiments (DoE) method to run a matrix evaluation. After test samples are completed, the quality inspection, electrical test and reliability test are following. Figure3-1 shows the detail flow of this test.
Fig. 3-1 Evaluation procedure
3-1 Evaluation plan
There are four types of materials included in flip chip package, solder material, substrate, underfill and chips with bumps. In this study, we focus on the package performance on the reliability for surface mount technology process, so the considered factors in this experiment are solder materials and surface treatment of lead frame. For chips with copper pillar bumps and underfill materials, we fix these factors in this evaluation.
The flip chip chip-scale package (CSP) is chosen for this experiment and the package structure is shown as below Figure 3-2. For CSP, it means the package must have an area no greater than 1.2 times of the chip size and it must be a direct surface mountable package. On this package, the stress between interface layers is greater than that of conventional package, thus CSP is a good candidate for this evaluation.
Material
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Fig. 3-2 Cross-section view of flip chip CSP package
3-1-1 Fixed materials on the design of experiments (DoE) 1. Chip with copper pillar bump
Several kinds of bump processes have been used for mass production in electronic devices assembly, like solder bumps, copper/solder bumps, copper bumps…etc, and the most popular one is solder bumps including Pb/Sn or SAC elements. For copper pillar bumps, it plays a more important role in today’s IC device market due to fine-pitch application and better electrical performance, thus we choose copper pillar bump in this study. Figure 3-3 shows the cross-section view of a copper pillar bump.
Fig. 3-3 Cross-section view of a copper pillar bump
The composition of a copper pillar bump is Cu/Ni/ Au, and the thickness of each layer is Cu : 22um, Ni: 2-3um and Au: 5um. The purpose of gold layer is to prevent the oxidation of copper layer after bumping process. The daisy-chain pattern is also designed
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for electrical test, as shown in Figure 3-4. The daisy-chain pattern is a method of propagating signals along a bus in which bumps/ pads are connected in series and the signal passed from one bump to the next.
Fig. 3-4 Top view of chip with daisy-chain design
Copper pillar bump process contains two major parts, redistribution layer (RDL) and bump. The process flow of RDL includes polymide coating, lithography, developing, electroplating and photoresist stripping. The process flow of copper pillar bumping is as shown in Figure 3-5, photoresist coating, exposure, developing, electroplating, photoresist stripping, under bump metallurgy(UBM) removal and annealing.
Fig. 3-5 The bumping process flow
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2. Molding under fill (MUF)
Molding underfill is a kind of polymer material which includes several composite components, like epoxy resins, phenolic hardeners, catalysts, and release agents. The purpose is to encapsulate semiconductor devices to prevent the defects from moisture, crack, package stress and interfacial delamination.
Package warpage is one of the major thermo-mechanical reliability concerns in electronic packaging. The cause is come from CTE (Coefficient of Thermal Expansion) mismatch on materials which comprise in a package. The occurrence of warpage during the assembly process can lead to misalignment of parts and a variety of operational failures. [15 ]
Kyocera low stress molding underfill is chosen for this experiment. With this material, we can lower the process variation during the sample assembly, therefore, the test result should be more reliable. The Table 3-1 shows the material property of a Kyocera molding underfill for reference.
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Table 3-1 The property of molding underfill
3-1-2 Key factor materials on the design of experiments (DoE) 1. Solder paste
Solder paste is the key material used in the process of surface mount technology.
It includes a sticky mixture of flux and tiny solder particles. Flux is added to act as a temporary adhesive, holding the components until the solders melt in the soldering process, leading to a stronger physical connection. The purpose of solder paste is to connect the leads of IC packages to attachment points. The solder paste is chosen based on its intended use purpose. In this experiment, we refer to the study of Ikuo Shohji in 2005, the SAC base solder pastes have better workability and reliability, so three types of solder pastes are tested in this evaluation.
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Table 3-2 Comparison table of solder pastes
A (SAC305) B (SAC300) C (SAC405)
Melting point, o C 217~221 221~225 217~219
reflow temperature, o C 238~248 238~248 238~248 Coefficient of Thermal
Expansion (20-100)
21.6 21.5 21.8
Electrical Resistivity ,
(μohm-cm) 13.0 12.3 12.7
Tensil Strength, MPa 41.1 40.6 43.7
Thermal Conductivity, W/m.K
63.2 62.6 61.1
Elengation 41.0 41.2 40.6
Young’s Modulus, GPa 50 50 52
Poison’s Ratio 0.36 0.36 0.35
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The added flux on above materials is the same and the change item is focused on the component percentage of tin, silver and copper.
2. Surface treatment of lead frame
The surface treatment is to plate gold above the copper layer to prevent oxidation on the surface, which can cause poor adhesion or cold joint on the solder-joint interface between bump and substrate. In addition, the worst issue is the micro-crack defect penetrating the package and resulting IC device function fail.
In this experiment, we use the lead frame material for CSP package. Two treatments are considered in parallel, one is gold treatment and another one is pure copper treatment.
a. Pure Copper Leadframe (LF), as shown in Figure 3-7
b. Gold(Au) plated Leadframe (LF)
Fig. 3-7 Top view of copper lead frame
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3-1-3 Design of experiments (DoE) matrix
A full factorial experiment is designed in this study. There are two factors that contain two and three levels, respectively. Total 6 cells (2x3 matrix) are generated in this experiment.
The below table shows the detail of the full factorial DoE:
Cell leadframe Solder type Remark
1 LF-PPF Solder -A SAC305
Two reliability tests are performed in this study, thermal cycling test (TCT) and pressure cooking test ( PCT). Therefore, total 300 units (50 ea x 6 cell) will be prepared in the test.
3-2 Examination items for process check
To verify whether the quality of samples can meet the requirement of the test, there are several examination items employed in this study. These inspections are very important and essential; the purpose is to assess the feasibility of the SMT process and material whether can be applied in the electronic devices.
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1. Die shear testing
Die shear testing is a method to determining the strength of adhesion on a semiconductor chip to the attach lead frame. A shearing stress is performed and subjected on the chip to examine the overall quality of adhesion interface. The pass criteria is based on the definition of the MIL-Std-883 method 2019 as appendix 1, it depends on the strength of the bonding area.
Fig. 3-8 The die shear testing method
2. X-ray inspection
X-ray inspection is a non-destructive analysis technique. The method is to use
X-radiation that is a form of electromagnetic radiation to penetrate the package and inspect the image which is transformed by the scattered energy.
After molding process, the solder connections are underneath the chip and not visible by optical microscope inspection. The use of X-ray inspection is to ensure that the manufacturing process is able to accommodate the quality requirement.
The following categories can be observed in this test:
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a. Dry joints due to insufficient solder b. Bridging/Shorts due to surplus solder
c. Voiding due to gas bubbles within the solder
d. Misplacement/Misalignment due to inaccurate placement of chip
3. Scanning Acoustic Microscopy (CSAM) inspection
Scanning Acoustic Microscopy (SAM) is a quick analysis technique without destroying the package. SAM uses ultrasound waves to detect changes in acoustic impedances in integrated circuits (IC) and other similar materials, pulses of different frequencies are used to penetrate various materials to examine different interfaces and determine the mechanical integrity of the assembly.
The following categories can be observed in this test:
a. Internal voids due to parameter or underfill issue b. Interface delamination due to material CTE mismatch c. Dry joints due to insufficient solder
d. Missing bump due to poor adhesion issue
4. Electrical test
The Ohmic testing is used to measure the resistance and analysis the electrical performance. The resistance increases as the interconnection condition declines and can be traced by the Ohmic measurement system. The resistance test can be performed as two-wire measuring as well as with the high-accuracy 4-wire measuring. Precise and stable measuring results up to the mOhm-range are detected. Figure 3-9 shows the HP-34970A Ohmic testing equipment.
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Fig. 3-9 The HP-34970A Ohmic testing equipment
5. Environment test
The environment test is to simulate the packaging, handling of electronic devices which are sensitive for the introduction of moisture. When moisture traps inside packages can damage them during soldering, as the moisture vaporizes and expands. The expansion of trapped moisture can result in internal delamination of the package from the die or lead-frame, and cause internal cracks.
We expect to simulate the strict use condition in this test, hence the Moisture Sensitivity Level (MSL) requirement is Level 1 and the condition is as below:
Condition : 85℃ temperature, 85% RH and 168 hrs aging time.
6. Stress test
Temperature and humidity are major causes to make IC package failure, below tests are applied in this study.
Temperature cycling test (TCT) - the thermal expansion mismatch among different components of the package especially on the solder joint can be enhanced. Figure 3-10 shows the Hitachi ES63LMV Temperature cycling test oven.
Pressure cooking test (PCT) - the humidity impact and metal joint corrosion on the package can be enhanced. The test result also can be accomplished on the acceleration
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model and calculate the acceleration factor, therefore, the time-to-failure distribution in normal use condition can be estimated. Figure 3-11 shows the HIRAYAMA PC-242HS pressure cooker.
The detail test conditions are as below:
a. Pressure cooker test (PCT), Condition : 121℃, 100% RH, 100/ 200/ 300/ 500/ 1000 hours
b. Temperature cycling test (TCT), Condition : -65℃, +150 ℃, 100/200/500/1000/1500/2000/3000/ 3500 cycles
Fig. 3-10 HITACHI Temperature cycling test oven
Fig. 3-11 HIRAYAMA Pressure cooker
3-3 Process optimization
The major process in this study is surface mount technology (SMT). The adhesion of the
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solder joint interface between copper pillar bump and lead frame is also the key point. The below lists the machine information and process flow for SMT
1. Machine type:
a. Chip / component place machine: Fuji NXP -1450 with integrated wafer handler function, as shown in Figure 3-12
Fig. 3-12 Fuji NXP chip place machine
b. Auto optical inspection machine: OMRON-3F5VT
Cyber-FLEX ULTRA 8
c. IR reflow oven: BTU-PYRAMAX, -10 Zone heating Oven
- Maximum temperature rating (all zones): 350°C - Oven atmosphere: Air/N2
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Fig. 3-13 BTU IR reflow oven
2. Operation procedure of surface mount assembly:
a. Cover stainless stencil on topside of lead frame b. Print solder paste on the land of Lead frame/ substrate c. Place bare die on lead frame land area
d. Auto optical inspection (AOI) for quality control
e. IR reflow process to fix the chip and Flux cleaning, Figure 3-15 shows the IR profile
Fig. 3-14 Solder paste printing process
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Fig. 3-15 IR-reflow profile
3. DoE for bonding join strength optimization
Solder paste is the key material to join the copper pillar and lead frame, if the solder paste is insufficient, it may cause the poor bonding strength and affect the reliability. The
process optimization and affected factors are reported [16, 17]. To make sure the
bonding strength in the best condition, the process optimization to fit this experiment is an essential work. We design four different opening of printing stencils and they are 100um / 125um/ 150um/ 180um opening. The purpose is to control the solder paste printing size and thickness.
Test Parameter:
a. Printing speed : 20 mm/s b. Printing pressure : 6.0 kg c. Cycle time : 29.2 sec
Speed: 50mm/ sec
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Test method:
a. Die shear testing for bonding strength adjustment is performed b. Appearance check after solder paste printing
Fig. 3-16 Solder plating on copper lead frame
Test result
From die shearing test result, the 150um and 180um opening tools can meet the requirement. Comparing to 150um and 180um opening tools, the solder height of 180um is higher than that of 150um opening, it has risk to bleed out the solder paste and touch the die surface.
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Fig. 3-17 Appearance check result of solder paste printing by different stencil opening
Fig. 3-18 Abnormal photo for insufficient solder
After the test and data analysis, the printing stencil with 150um opening got better performance and met the quality requirement, the thickness of solder paste also can controlled within 50um, so we plan to release it for further trial run.
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3-4 Test sample manufacturing
After process optimization, the best condition for sample manufacturing is determined.
We implement it on the Flip-chip CSP assembly process and confirm the samples quality to meet our requirement.
3-4-1 The assembly process flow
There are several processes in package assembly, here we list the major process flow:
1. L/P : the process is to grind the wafer to the designate thickness 2. D/S : to saw the wafer to the unit by high speed diamond blade 3. Chip attach : to bond the chip on the lead frame or substrate
4. IR reflow : an oven with several heating zones for soldering process 5. M/D : molding, to encapsulate the chip with molding underfill material
6. S/P : solder plating, to plate the tin on the outer lead, this process is for lead package only
7. P/S : package sawing, to cut the leadframe/ substrate into units
Figure 3-19 shows the process flow of flip chip CSP package
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Fig. 3-19 FC CSP process flow
3-4-2 Quality inspection result
Quality inspection is about inspection, measuring, or testing of product characteristics. To make sure all samples can meet the quality requirement and can release to next evaluation without abnormal phenomenon, we perform tests in production.
1. Appearance inspection
The optical microscope is used to check the outlook quality. All units are inspected and the test result can meet the specification on solder paste print, bonding position
accuracy, topside and backside quality before/ after molding underfill process.
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Fig. 3-20 The appearance inspection
Fig. 3-21 The appearance inspection after molding process
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2. Die shear testing
The die shear testing for six cells has been done to confirm the solder joint strength.
Fifteen units per cell are examined and the result could pass the specification. The defect mode after shear testing is solder ball-neck broken, and this failure phenomenon meets the standard. The test readings are listed on Table 3-4.
The cell 4, cell5 and cell 6 with bare copper LF got better test result, there is no significant test difference from cell 1 to 3 and the PPF treatment lead frame is used in these cells.
unit: Kg Table 3-4 The shearing test result
Cell 1 2 3 4 5 6
1 0.959 1.083 0.967 3.257 3.288 3.213
2 1.185 0.995 0.883 3.033 3.088 3.262
3 0.887 0.954 0.882 3.183 2.672 3.332
4 1.168 1.068 1.083 3.446 3.249 3.397
5 0.852 0.877 0.928 2.541 2.751 3.078
6 0.895 0.898 0.868 3.332 2.825 3.208
7 1.126 1.078 0.892 3.193 3.014 3.574
8 0.994 0.874 1.048 3.224 3.279 3.334
9 0.972 1.056 0.961 3.206 2.905 2.687
10 1.254 0.931 0.898 2.948 3.016 3.275
11 1.065 0.956 1.218 3.152 2.962 3.078
12 0.986 1.185 0.922 2.913 3.303 2.875
13 1.169 0.848 0.972 3.101 3.011 3.371
14 1.193 1.021 1.025 2.763 2.694 2.986
15 1.194 0.908 1.017 3.228 2.948 3.258
max 1.254 1.185 1.218 3.446 3.303 3.574
min 0.852 0.848 0.868 2.541 2.672 2.687
mean 1.060 0.982 0.971 3.101 3.000 3.195
sigma 0.132 0.097 0.095 0.231 0.212 0.224
Spec 0.080 0.080 0.080 0.080 0.080 0.080
Ppk 2.469 3.092 3.122 4.357 4.589 4.643
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Fig. 3-22 Die shearing test analysis
Fig. 3-23 The breaking mode after die shearing test
3. X-ray inspection
The X-ray inspection has been done for six cells to confirm the solder joint
interconnection. Any defect such as chip shift, as shown in Figure 3-24, and internal void
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under bump connection interface should be scraped.
Fig. 3-25shows the X-ray inspection result for normal unit.
Fig. 3-24 The X-ray inspection result for a defect unit
Fig. 3-25 The X-ray inspection result for normal units
4. Scanning Acoustic Microscopy (CSAM) inspection
CSAM inspection is confirmed for six cells to exam the delamination in different interfaces within packages. Figure 3-26 shows the result of normal units and defect units.
All units are inspected and the result could pass the specification. No delamination abnormality is found in these samples.
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Fig. 3-26 CSAM inspection result of normal units and defect units
5. Cross sectioning inspection
After package separation process, we performed cross-section to confirm the
package structure, chip tilt. The unit is grinded from side of package to bonding area and inspected by optical microscope. No abnormal phenomenon was found in the sample.
Fig. 3-27 Cross section of flip chip CSP package
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6. Electrical test
The judgment of reliability test is based on the electrical test results, therefore, all samples are confirmed by electrical test. We use high-accuracy 4-wire measuring system in the test. Table 3-5 shows all initial test readings of resistance. From the test results, the
The judgment of reliability test is based on the electrical test results, therefore, all samples are confirmed by electrical test. We use high-accuracy 4-wire measuring system in the test. Table 3-5 shows all initial test readings of resistance. From the test results, the