I. Introduction
1.3 Surface-mount technology (SMT)
The surface-mount technology is a method for making electronic circuits in which the components are placed directly onto the surface of substrate or printed circuit boards (PCBs).
After IR relow or wave reflow process, the components are connected. This process was developed in the 1960s and became widely used in the late 1980s.
The first step is to print the solder paste on the substrate. Solder paste, a sticky mixture of flux and tiny solder particles, is applied to pads of substrate or PCBs with a stainless steel stencil using a screen printing process. It can also be applied by a jet-printing mechanism for fine pitch devices. After finished printing process, the substrate proceeds to the pick-and-place machines. The components are placed on the substrate by rubber tip with vacuum. Then the substrate is inspected by an Automatic Optical Inspection (AOI) to make sure all the components are at the correct position. Next, the substrate transfers into the IR reflow oven.
The surface tension of the molten solder helps keep the components in place, and if the solder pad geometries are correctly designed, surface tension automatically aligns the components on their pads.
After IR-reflow process, AOI is applied again to inspect all components are well to place on the correct position of the substrate or PCBs.
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Chap 2. Motivation and Theory
2-1 Motivation
For the high demand on mobile and tablet portable products, the package size of Integrate circuit devices (IC) trends to get thin and small. The saved space is designed to enlarge the cell capacity. This purpose is to reach longer standby and operation time on 3C products.
Chip scale package (CSP) is developed in this intension, so we will focus on chip scale package with copper pillar bump in this study. Moreover, it also can be extended to the application of System in Package (SiP). SiP is a number of integrated circuits enclosed in a single package. They are connected internally by bonding wires or with a flip chip assembly, solder bumps to join the circuit.
The major process for flip chip package is to use die bonder to mount the chip with copper bumps on substrate/ lead frame, as below figure. Through this method, only Sn/Pb bump or Cu/Sn bump can be applied on this process.
Fig. 2-1 The main process flow of flip chip package
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As we mentioned on above paragraph, this study is focused on surface mount technology to mount chips on lead frame or substrate, a SMT and molding processes are used in this CSP , as show in Figure 2-2.
Fig. 2-2 The main process flow of flip chip package for SMT method
Besides the SMT process evaluation, we include solder materials and surface treatment of lead frame on it. By this way, we plan to extend the machine application from SiP to flip chip package, also expect to integrate more function on multi packages.
We think this could be a simple way to get good reliability performance through Interfacial Bonding Behavior between Sn-Ag-Cu Series solder materials and lead frame surface treatment. Through the join of different solder composition ( Sn/Ag/Cu base) and lead frame treatment, the intermetalic compound (IMC) is formed between the Cu pillar bump and the leadframe surface. This intermetalic compound will affect the interfacial bonding strength and reliability performance.
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The below table shows the advantage and disadvantage comparison of both processes of flip chip package.
Traditional (original) New method
Advantage 1.Mature production process 2.High pint count application 3.High thermal dispatch
1.High reliability performance 2.No need solder cap on bump/
pillar
3.Flexibility for application on other package
Disadvantages 1.Reliability concern on high level 2.Solder cap on bump is needed
1.Limit on high I/O chip application 2.Narrow process window in process
Table. 2-1 process comparison of flip chip package
The weakness point on Flip chip package is the solder joint of copper pillar bump to lead frame or substrate, there are many papers submitted to use Finite Element Method software (FEM) for the simulation. A paper issued by Yunn-Horng Guu mentioned the pillar bump with a copper base and eutectic solder cap had a higher resistance to fatigue failure in comparison with a pure eutectic solder bump, the mechanical behavior of the flip-chip packag is a crucial issue in the packaging industry, and it is also related to the reliability of electronic devices[3].
The solder paste is highly related to the solder join of the bonding interface, refer to the study result of paper [4] [5], the solder paste with Ag content 3.0% to 4.0 % has below characters :
1. Better thermal fatigue resistance and reliability result 2. Better wetting performance.
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3. Broader process window
4. Better Joint reliability compared to non-silver lead-free and tin-lead alloys.
Based on these data, three types of solder paste: Sn 96.5%/ Ag 3%/ Cu 0.5%, Sn 97%/
Ag 3% and Sn 95.5%/ Ag 4%/ Cu 0.5% are chose for this study.
2-2 Theory
The reliability test is used to exam the result of the evaluation on this study.
Reliability is defined as the probability that a device or system will perform its intended function during a designated period of time under stated conditions.
2-2-1 The Bath-tube curve model
The bathtub curve is used in reliability engineering and is generated by mapping the rate of early "infant mortality" failures when first introduced, the rate of random failures with constant failure rate during its "useful life", and finally the rate of "wear out" failures as the product exceeds its design lifetime. Please refer the below Figure 2-3, the first part is a decreasing failure rate, known as early failures., the second part is a constant failure rate, known as random failures and the third part is an increasing failure rate, known as wear-out failures[6].
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Fig. 2-3 The Bath-tube curve model
The probability of reliability function is as
R(t) = P{T > t} = 1 − P{T ≤ t} = 1 − FT(t), t ≥ 0 (2-1) From (2-1)
𝑓𝑓T(t) = −R′(t) and 1 − R(t) = FT(t) = P{T ≤ t} (2-2) where F(x) is the failure function, and
ƒ(x) is the failure probability density function,
P is probability and t is the length of the period of time
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Fig. 2-4 The reliability function for lifetime and failure rate
h means constant failure rate or can be called hazard rate. It is defined for non repairable populations as the rate of failure for the survivors to time t during the next instant of time, and the function is as
h(t) = lim∆𝑡𝑡→0P(t < T ≤ t + ∆t|T > t)
Δt = lim∆𝑡𝑡→0P(t < T ≤ t + ∆t) Δt ∙ P(T > 𝑡𝑡) = lim∆𝑡𝑡→0F(t+∆t)−F(t)
Δt ∙R(t)1 =1−FF′T(t)
T(t) = 𝑓𝑓R(t)T(t) (2-3)
MTTF is Mean Time To Failures (for non-repairable equipments), and the equation is MTTF = 1 / h
The cumulative distribution function corresponding to a bathtub curve and may be analyzed using a Weibull distribution chart.
2-2-2 Weibull distribution
The Weibull distribution is widely used to model Life Data, it was originally proposed by
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the Swedish physicist Waloddi Weibull. He used it for modeling the distribution of breaking strength of materials, now this distribution is applied to model many different failure distributions.
This distribution can handle increasing, decreasing or constant failure rates. The Weibull distribution is flexible and fits to a wide range of data, including normal distributed data. Only Log-Normal data does not fit in the Weibull distribution and needs separate analysis.
For a comprehensive review of applications, we refer the readers to Johnson et al. (1994) and Murthy et al. (2003)[7]. Given a shape parameter, β, and characteristic life time, η, the three-parameters Weibull distribution probability density function (PDF) and reliability function are given by:
t = time, cycles, miles, or any appropriate parameter;
Generally, the location parameter is not used and the value can be set to zero, so the PDF equation can be reduced to two-parameter Weibull distribution.
𝑓𝑓T(t) = βη�ηt�β−1e−�ηt�
β
, t ≥ γ (2-6)
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Weibull Parameters
The shape parameter, BETA (β) is known as Weibull slope, it shows how the failure rate develops in time. Different values of the shape parameter can have responded effects on the behavior of the distribution. Figure 2-5 shows the effect of different values of the shape parameter, β, on the shape of the PDF (while keeping γ constant), we can see the shape of the PDF can take on a variety of forms based on the value of β.
Fig. 2-5 The PDF shapes of the Weibull distribution (Source: http://www.weibull.com/hotwire/issue14/relbasics14.htm)
Another characteristic of the distribution where the value of β has a distinct effect is the failure rate. Figure 2-6 shows the effect of the value of β on the Weibull failure rate.
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Fig. 2-6 the value of β on the Weibull failure rate (Source: http://www.weibull.com/hotwire/issue14/relbasics14.htm)
This is one of the most important aspects of the effect of β on the Weibull distribution.
Weibull distributions with β < 1 have a failure rate that decreases with time, also known as infantile or early-life failures. Weibull distributions with β close to or equal to 1 have a fairly constant failure rate, indicative of useful life or random failures. Weibull distributions with β > 1 have a failure rate that increases with time, also known as wear-out failures.
Corresponding to below equation (2-3) and (2-4) , we also can find the failure rate as
h(t) = 𝑓𝑓R(t)T(t) = βη�t−γη �β−1 (2-7)
Refer to Figure 2-3, the shape meets the Bath-tube curve model.
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The ETA (η) is characteristic life time or scale parameter, increasing the value of η while holding β constant has the effect of stretching out the PDF. Since the area under a PDF curve is a constant value of one, the "peak" of the PDF curve will also decrease with the increase of η, as indicated in the following figure.
Fig. 2-7 the value of η on the Weibull failure rate (Source: http://www.weibull.com/hotwire/issue14/relbasics14.htm)
If η is increased, while β and γ keep the same, this distribution gets stretched out to the right and its height decreases, while maintaining its shape and location.
If η is decreased, while β and γ keep the same, the distribution gets pushed in towards the left, and its height increases.
η has the same unit as T, such as hours, miles, cycles, actuations, etc.
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2-2-3 Arrhenius relationship equation
The semiconductor and system manufacturers face strong pressure to develop new and higher reliability products in short term today. The instant time-to-market becomes the success factor of new product promotion. Accelerated Test (AT) is developed based on this concept. Refer the readers to Thomas P. Ryan et al. (2007, chapter 14) [8], an accelerated failure model relates the time-to-failure distribution to the stress level. The general idea is that the level of stress is only compressing or expanding time and not changing the shape of the time-to-failure distribution.
With this assumption, changing stress is equivalent to transforming the time scale used to record the time at which failures occur, so it is a matter of “decelerating” back to normal use by using an appropriate acceleration factor. This is accomplished by using acceleration models.
Arrhenius relationship equation is commonly used on the accelerated test for the life time prediction in normal use condition and environment. It is expected that as stress is increased, like temperature, humidity, a reaction such as a chemical reaction, will occur more rapidly.
The Arrhenius equation reflects this idea and is named after S. A. Arrhenius (1859–1927).
The equation when applied to accelerated testing is given by
𝐿𝐿(temp) = A ∙ e�𝑘𝑘∙tempK−𝐸𝐸𝐸𝐸 � (2-8)
where L is the reaction rate, A is an unknown non-thermal constant, temp K is temp C+273.15, is thermodynamic temperature in kelvin (K), k is Boltzmann’s constant (8.617×10-5 ev/k ) or the universal gas constant and Ea is the activation energy based on characteristics of product or material.
Acceleration factors (AF) are used to estimate the failure rate from the thermally
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accelerated life test conditions to a failure rate indicative of normal use temperature for electrical devices. From the equation (2-8), the AF is found
AF =LLuse
accl = A∙e�−𝐸𝐸𝐸𝐸𝑘𝑘∙TL�
A∙e� −𝐸𝐸𝐸𝐸𝑘𝑘∙TH �
= eEak�TL1−TH1� (2-9)
where AF is acceleration factor, Luse is lifetime during normal use, Laccl is lifetime during acceleration use, TL is low temperature ( [K] = 273 +temperature in ˚C) and
TH is high temperature.
For the relationship about humidity and temperature, from the study by D. Stewart Peck in 1986, an acceleration formula is described which provides direct extrapolation from test results on humidity and temperature[9], the equation is given
Time to failure (RH)n∙ e�𝑘𝑘∙T𝐸𝐸𝐸𝐸� (2-10)
AF =LLuse
accl = �RHRHtest
use�n ∙ e�𝑘𝑘∙T𝐸𝐸𝐸𝐸��ttest1 − tuse1 � (2-11)
where RH is humidity, n is integer constant from 1 to 7, Ttest is temperature during test ( [K]
= 273 +temperature in ˚C) and Tuse is temperature during use.
2-3 Reliability test
The “Reliability” is the ability of a system or component to perform its required functions under stated conditions for a specified period of time.[10] Reliability is theoretically defined as the probability of failure, the frequency of failures, or in terms of availability, in other words, failure rate, average life, mean time to failure (MTTF), etc. From the test data, the time-dependent quality of products, are estimated and verified statistically. These tests also
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play an important role in improving reliability by analyzing failures which occur during tests and clarifying these failure mechanisms. Reliability tests provide the greatest effects when statistics and failure physics function reciprocally.
2-3-1 Environment test
The environment test is identified the classification level of nonhermetic solid state surface mount devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid damage during assembly solder reflow process.
There are eight levels defined for this test and is called Moisture Sensitivity Level (MSL), as shown in Table 2-2. This standard is used to determine what classification or preconditioning level should be used for SMD package qualification.[11]
Table. 2-2 Moisture Sensitivity Levels
After Moisture Sensitivity Level test, all devices must pass final external visual inspection,
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appropriate electrical testing and acoustic microscope, if one or more devices are failed, the package shall be considered to have failed the test and stop to go to next stress test.
2-3-2 Stress test
The purpose of stress test is to precipitate failures in an accelerated manner compared to normal use conditions. Test units are subjected to higher than usual levels of one or more accelerating variables such as temperature, humidity, voltage and current. Then the test results are used to analysis packaging failures or predict life of the units at use conditions. Anand model[12] was employed to represent the constitutive equation of solders in stress model and developed to life prediction model in the accelerated thermal test. [13]
There are many industry-standard package-level reliability tests. The test is chosen based on the failure mechanism, as different stress tests accelerate different failure mechanisms. It is also important to select test methods which are as standardized as possible in consideration of test reproducibility, cost effectiveness, data compatibility and other factors [14]. These tests are described as below.
1. Biased Highly Accelerated Stress Test (HAST) (JESD22-A110)
The purpose is to simulate extreme operating conditions. Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are subjected to bias while the devices are in the chamber. The devices are then ATE tested for electrical failures. Variables: Temp = 130°C / Humidity = 85% RH/
Time = 96 hours
2. Temperature Cycle Test (TCT) (JESD22-104)
The purpose is to accelerate the effects of thermal expansion mismatch among different components of the package and circuit. It is used to determine package resistance from high temperature to low temperature and to temperature changes during
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transportation and use.
The devices are ATE tested for function verification. Failed devices are checked for interface cracks. Variables: Temp = 150°C (top) and -65° C (bottom)
3. Pressure Cooker Test (PCT) (JESD22-A102)
The purpose is to test moisture resistance of plastic encapsulated devices. Devices are baked in an autoclave (on a tray) at high temperatures and humidity for an extended period of time under static conditions. An ATE test is performed after the autoclave.
Failed devices are checked for delamination, shorts, etc.
Variables: Temp = 121°C / Pressure = 15 Psi / Humidity = 100 % RH 4. High Temperature Storage (HTS) (JESD22-A103)
The purpose is to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.
Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures. Variables: Temp
= 150°C / Time = 1000 hours
5. Temperature Humidity Bias (THB) (JESD22-A101)
The purpose is to determine device/package resistance to prolonged temperature, humidity, and electrical stress. Devices are baked in an oven at extreme temperature and humidity for various lengths of time. The devices are subjected to maximum differential bias on alternating pins while the devices are in the oven. The devices are then ATE tested for electrical failures.
Variables: Temp = 85°C / Humidity = 85% RH.
6. Unbiased Highly Accelerated Stress Test (UHAST) (JESD22-A118) The purpose is to simulate extreme operating conditions. Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The
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devices are then ATE tested for fuction verification.
Variables: Temp = 130°C / Humidity = 85% RH.
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Chap 3. Evaluation plan and procedure
The detail evaluation plan and the procedure of the test sample manufacturing are described in this chapter. We use the design of experiments (DoE) method to run a matrix evaluation. After test samples are completed, the quality inspection, electrical test and reliability test are following. Figure3-1 shows the detail flow of this test.
Fig. 3-1 Evaluation procedure
3-1 Evaluation plan
There are four types of materials included in flip chip package, solder material, substrate, underfill and chips with bumps. In this study, we focus on the package performance on the reliability for surface mount technology process, so the considered factors in this experiment are solder materials and surface treatment of lead frame. For chips with copper pillar bumps and underfill materials, we fix these factors in this evaluation.
The flip chip chip-scale package (CSP) is chosen for this experiment and the package structure is shown as below Figure 3-2. For CSP, it means the package must have an area no greater than 1.2 times of the chip size and it must be a direct surface mountable package. On this package, the stress between interface layers is greater than that of conventional package, thus CSP is a good candidate for this evaluation.
Material
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Fig. 3-2 Cross-section view of flip chip CSP package
3-1-1 Fixed materials on the design of experiments (DoE) 1. Chip with copper pillar bump
Several kinds of bump processes have been used for mass production in electronic devices assembly, like solder bumps, copper/solder bumps, copper bumps…etc, and the most popular one is solder bumps including Pb/Sn or SAC elements. For copper pillar bumps, it plays a more important role in today’s IC device market due to fine-pitch application and better electrical performance, thus we choose copper pillar bump in this study. Figure 3-3 shows the cross-section view of a copper pillar bump.
Fig. 3-3 Cross-section view of a copper pillar bump
The composition of a copper pillar bump is Cu/Ni/ Au, and the thickness of each layer is Cu : 22um, Ni: 2-3um and Au: 5um. The purpose of gold layer is to prevent the oxidation of copper layer after bumping process. The daisy-chain pattern is also designed
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for electrical test, as shown in Figure 3-4. The daisy-chain pattern is a method of propagating signals along a bus in which bumps/ pads are connected in series and the signal passed from one bump to the next.
Fig. 3-4 Top view of chip with daisy-chain design
Copper pillar bump process contains two major parts, redistribution layer (RDL) and
Copper pillar bump process contains two major parts, redistribution layer (RDL) and