Chapter 3 Transimpedance Amplifier
3.4 Summary
According to the post-layout simulated results, the transimpedance amplifier is able to operate for 3.2 Gbps data rate. It has a voltage gain of 60 dB Ω, -3 dBbandwidth of 2.9 GHz, group delay less than +/- 15 ps, input-referred noise about 2 µArms.
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Table 3-3 lists the simulated results of the transimpedance amplifier with RGC input stage, and a resistor shunt-shunt feedback with common-source voltage amplifier.
Table 3-3 Post-layout simulated results (RCC) of TIA.
Specifications @ SS Corner
Gain 60 dBΩ 60 dBΩ
- 3dB Bandwidth 2.2 GHz 2.9 GHz
Input-Referred Noise 1.84 µArms 2 µArms
Group Delay Variation N.A. +/- 15 ps
Power Consumption N.A. 16 mW
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Chapter 4
Limiting Amplifier
The signal produced by front-end transimpedance amplifier usually suffers from small amplitude, on the order of a few of millivolts for the minimum input current level. Such a weak signal will result in incorrect recovered data streams while it is received by clock and data recovery (CDR) circuit. Therefore, an additional gain boosting stage that boosts the signal swing to logical level is necessary. Post limiting amplifier is approach that are widely used in communication systems.
In this chapter, limiting amplifier will be discussed. That includes limiting amplifier’s specifications, architectures, analysis of the stage number and circuit implementation.
4.1 Design Considerations
Gain
The gain of limiting amplifier is defined as the output voltage change per input voltage
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change. A typical limiting amplifier has a gain of around for 30 dB to 50 dB. In optical communication system, limiting amplifier provides the gain to boost the TIA’s output signal to logical level for CDR followed by. Thus, a TIA with high transimpedance gain helps to relax the gain requirement for the limiting amplifier.
Bandwidth
To reduce the ISI in random data, the limiting amplifier bandwidth is often made much larger than the desired receiver bandwidth. As a rule of thumb, the limiting amplifier -3dB bandwidth is chosen around 1.0 or 1.2 times the data rate, nearby twice the recommended receiver bandwidth. For example, for 2.5 Gbps and 10 Gbps data rate, a limiting amplifier -3dB bandwidth should be 2.5 GHz to 3GHz and 10 GHz to 12 GHz, respectively.
Input Offset Voltage
The limiting amplifier usually consists of several cascading gain cell stages. An offset voltage, caused by the non-ideal terms such as devices mismatch, Vt mismatch, and etc., will be amplified by the rear gain cells. It may cause incorrect data regeneration when the input signal is small. In other words, it may cause pulse-width distortion and decrease input sensitivity. Figure 4-1 shows the comparison of limiting amplifier output waveform with and without offset voltage.
Figure 4-1 LA output waveform with and without offset voltage.
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AM-to-PM Conversion
A limiting amplifier converts the input small signal to the output logic level and is a non-linear system. If the amplitude of input signal is not constant, then it will result in phase disturbance or so-called jitter in output signal of limiting amplifier. Typically, the delay variation resulted from AM-to-PM conversion will be less than ±10% of the bit time. That is about ±40 ps and ±10 ps for 2.5 Gbps and 10 Gbps, respectively.
4.2 Limiting Amplifier Architecture
4.2.1 Architecture Comparison
Typically, the limiting amplifier usually consists of several fully differential wide-band stages. According to the variety of cascading gain cells, limiting amplifiers can be classified into following four categories.
Identical Linear Amplifiers [12]-[14]
For limiting amplifier, that identical cascaded gain cell is a solution to solve the trade-offs between gain, bandwidth, and power consumption. For simplification, a limiting amplifier cascading identical gain cells (Figure 4-2(a)) is commonly used.
Figure 4-2 Limiting amplifier output with and without offset voltage.
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Linear Amplifiers + Slicers [15]
In the limiting amplifier the signal can be seen as small-signal operation in the front several stages; whereas large-signal operation in the later stages. In other words, the later stages typically sense sufficiently large input swings, thereby experiencing switching and operating in the large-signal mode. Therefore, the stage’s rising time and falling only depend on its output RC time constant. As shown in Figure 4-5(b), the slicer with low impedance is utilized to accelerate voltage switch and balance rising and falling time at high voltage level.
Inverse Scaling Technique [16]
As shown in Figure 4-5(c), to drive a small on-chip load, the cascaded amplifier can be inverse scaling. The input capacitance is usually lager than that of output. By inverse scaling technique, the bandwidth due to output node will be improved and so as limiting amplifier.
Tapered Buffer [17]
If an amplifier is to deliver signals to 50 W loads, then it must employ high currents and large output transistors in the last stage. As illustrated in Figure 4-5(d), the cascade must be tapered in device dimension and bias current from the first to the last so as to maintain a wideband while delivering high output current.
4.2.2 Analysis of Stage Number
Conventional post limiting amplifier is comprised of identical cascaded gain cells.
Assuming each gain cell can be approximated by a two-pole amplifier, it can be described as:
( )
2 2 246
For a given limiting amplifier with total gain of AT and -3dB bandwidth of ωT, then it will be implemented by cascading N-stage, identical, two-pole gain cells with ζ of 2/2 for maximally-flat bandwidth. Then, the gain (AS), -3dB bandwidth (ωS) and unity-gain bandwidth of single gain cell can be derived as:
( )
The single stage gain can be reduced along with the increasing of the number of gain stages, while the -3 dB bandwidth of each gain cell should be increased accordingly. When the number of stage is increasing, it turns out that the gain bandwidth product can be relaxed. But it would lead to a higher input-referred noise if the conversion gain of gain cell is too small.Besides, if the current consumption in each stage is proportional to the square of its unity gain bandwidth, the total power dissipation will also be increased for more stages in cascade.
( ) (
1 2)
1 22 2 1 2
2 N 1 N 1
U T T
Power∝ ⋅N ω ∝ ⋅N ω ⋅ − − ⋅ A − (4-5) Figure 4-3 shows the case when the linear gain contributed by the front several stage of LA is 25 (or 28dB) and bandwidth is 3.2 GHz. Also, all the parameters are normalized in Figure 4-3. It can be intuitively understood that as the number of cascaded stage increases, the gain provided by each gain stage decreases. In the meantime, the bandwidth provided by each gain stage increases. In addition, the power consumption increases proportionally when stage number is larger than three. Take power dissipation into consideration, we are forced to make a compromise between speed and power consumption. Thus, a 2-stage or 3-stage linear amplifier in front of LA has lower power dissipation and its unity-gain bandwidth is also feasible in 0.18-µm CMOS technology.
At last, a 3-stage amplifier with lower gain in each stage is chosen in this design rather than a 2-stage amplifier because the Miller effect should not be ignored.
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Figure 4-3 Normalized LA’s power consumption versus the number of stages.
4.3 Limiting Amplifier Implementation
The architecture of post limiting amplifier is shown in Figure 4-4. Excluding the DC offset cancellation network, the limiting amplifier is composed of a subtractor (SUB) in the front and 5 gain stages consisting of 3 stages in linear amplified and 2 stages in slicer amplified.
The subtractor not only exhibits lower input capacitance for TIA to be capability of high-speed operation, but also blocks the DC offset voltage from limiting amplifier and imbalanced signal from TIA.
Figure 4-4 Limiting amplifier is composed of SUB and 5 gain cells.
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Figure 4-5 Feedback type limiting amplifier architecture.
4.3.1 DC Offset Cancellation Network
Besides of offering additional voltage gain, offset cancellation is another important key function in limiting amplifier design. The offset voltage may cause incorrect data regeneration and decrease the sensitivity.
Feedback type offset cancellation is adopted in this design for its minimum circuit overhead at signal path. The less overhead means the amplifier can operate at a higher speed. Figure 4-5 shows the diagram of the feedback type architecture. From the view of high frequency signal, it is an opened loop associated with the gain cells, because LPF has a lower -3dB frequency than input signal, usually on the order of several kHz. But, from the view of low frequency signal (like DC offset), it’s a closed loop. The offset signal is fed back negatively and subtracted from the input. By using negative feedback, the equivalent offset voltage is divided by a factor of loop gain 1+Aβ.
Assume the feedback path of the limiting amplifier has a pole of s =-p, then the transfer function of the limiting amplifier can be described as:
( ) ( ) ( )
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where the Ao denotes the gain of the 5-stage gain cells.
Thus, the (4-7) and (4-8) mean that a signal at relative low frequency or the input offset voltage of LA, its gain is about 1; on the other hand, a signal at relative high frequency or the TIA output ac signal, its gain is about Ao. It is obviously that offset voltage will not be amplified by limiting amplifier which only amplifiers the ac signal from TIA.
4.3.2 Gain Cell Design
Figure 4-6 Gain cell in the limiting amplifier.
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Figure 4-7 Active feedback architecture.
2
This result reveals that the active feedback increases the GBW beyond the technology fT by a factor equal to the ratio of fT and the cell -3dB bandwidth.
Moreover, the subtractor, depicted in Figure 4-8, is also based on the Cherry-Hooper amplifier with active feedback. Compared to Figure 4-7, IB1a, IB1b and (L/W)M1,2 will reduce to
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half if to keep the current consumption and transistor overdrive voltage. Thus, it is given
1 2 subtractor gain due to TIA and DC offset cancellation network, respectively.
To summarize the subtractor, it not only delivers a path for the DC offset voltage been cancelled, but also reduces the TIA’s output capacitance for TIA to be capability of achieving higher bandwidth owing to half transistor size.
Figure 4-9 to Figure 4-13 show the limiting amplifier post-simulated results. To minimize ISI induced data jitter, the limiting amplifier is design as voltage gain of 47 dB, while the front 3 stages deliver voltage gain of 29 dB and -3 dB bandwidth of 3.1 GHz.
Figure 4-8 Subtractor schematic in the limiting amplifier.
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Figure 4-9 Magnitude responses of subtractor, gain cell and slicer.
Figure 4-10 Magnitude responses of LA and front 3 stage.
And the gain of a subtractor, a gain cell and a slicer are 3.6 dB, 9.7 dB and 8.4 dB, while the -3 dB bandwidth is 4.8 GHz, 4.8GHz and 5GHz, respectively. The group delay variation of LA with buffer is about ±15 ps from 10 MHz to 2.5 GHz. Besides, the input-referred noise is about 1.6 mVrms if the noise-bandwidth is about 2.5 GHz.
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Figure 4-11 Group delay of LA.
Figure 4-12 Input-referred noise of LA.
4.4 Summary
According to the post-layout simulated results, the limiting amplifier is able to operate for 3.2 Gbps data rate. It has a voltage gain of 47 dB (including 29 dB linear gain), group delay less than +/- 15 ps, input-referred noise about 1.6 mVrms.
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Figure 4-13 Simulated eye diagram of LA.
Table 4-1 Post-layout simulated results (RCC) of limiting amplifier.
Specifications @ SS Corner
Gain (front 3-stage) 28 dB 29 dB
LA Gain 44 dB 47 dB
- 3dB BW (front 3-stage) 3.125 GHz 3.1 GHz
Group Delay Variation N.A. +/- 15 ps
Power Consumption N.A. 92 mW
Table 4-1 lists the simulated results of the limiting amplifier with a subtractor in the front, a DC offset cancellation network, 5-stage gain cell limiting amplifier (including 3-stage linear gain cell and 2-stage slicer gain cell).
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Chapter 5
Adaptive Equalizer and Buffer
To compensate the bandwidth roll-off of a photodetector, a high-pass filter will be designed.
In order to compensate the roll-off automatically, an equalizer with adjustable zero, two slope detectors and an error amplifier are adopted. In this chapter, an adaptive equalizer will be discussed first. Following equalizer, the high-speed output buffer is described in section 5.2.
5.1 Equalizer Circuit
To compensate the bandwidth degradation of SML detector, a high-pass filter will be designed.
Typically, we can use the capacitance/resistance source degeneration, as shown in Figure 5-1, to create a zero, and the equivalent transconductance of this differential amplifier is given by:
( )
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(a) (b)
Figure 5-1 (a) Capacitance/resistance degeneration, (b) frequency response..
In the above equation, it contains a lower frequency zero located in 1/(RSCS), and a higher frequency pole located in (1 + gm1,2RS /2) /( RSCS), thus it seems like a high-pass filter.
The equalizer [18] is shown in Figure 5-2. In contrast to the gain cells, it introduces a tunable zero in the transconductance stage of the Cherry-Hooper amplifier. As discuss before, the bandwidth of the SML photodetector is about 1.6 GHz. To compensate the bandwidth degradation of SML detector, the zero of equalizer should be adjusted around 1.6 GHz so as to cover bandwidth variations and fulfill the requirement of high speed operation.
R1 R2
Figure 5-2 The equalizer circuit.
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Adaptive Equalizer & Slope Detector
The schematic of adaptive equalizer is shown in Figure 5-3. The equalizer provides additional zero to compensate the bandwidth degradation caused by the photodetector. The zero location is adjusted by a feedback control loop which detects the edge slope of the output waveforms in the last two stages. In the slope detector, compare the steep slope of input differential signals with the slow one, the output averaging voltage is higher when steep slope signal is applied. The slope detector followed by an error amplifier which provides a low frequency pole to make sure a stable loop and delivers a DC signal to equalizer.
The slope detector can be realized as shown in Figure 5-3. It consists of a differential amplifier with the drain node connected to the VDD. When a differential signal (vinx or viny) is applied to the gates of the differential amplifier (M1x, M2x or M1y, M2y), it looks like transient time detector. In addition, its output voltage is higher if the differential input slope is steeper, and vice versa. For example (see Figure 5-4), if the slop of viny is steeper than vinx, the average voltage of vouty is higher than voutx. After amplified by the error amplifier, VCTRL drops and the zero of equalizer goes higher. On the other hand, if the slop of vinx is steeper than viny, the average voltage of vouty is lower than voutx, VCTRL arises and the zero of equalizer goes lower and peaking more.
Figure 5-3 Adaptive equalizer.
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(a) (b)
Figure 5-4 Transient simulation of the slope detector.
How much output voltage drop as a pair of differential signal is applied to slope detector?
Assume the input voltage swing of slope detector is, vswing, from VDD - vswing to VDD. The output has minimum voltage as M1X and M2X drift equal current. Thus, it can be described as:
min time, it can be described as:
max
And the output swing of the slope detector is
B
The above equation means the output voltage swing depends on the tail current, transistor size and input voltage swing.
For a slow transition of either polarity, the coupled-source node voltage is minimum value when the differential input is 1 or 0. And the response of any input transient is a negative pulse. However, a faster transient will have smaller pulse amplitude due to its short period of changing state.
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Figure 5-5 Two stage error amplifier.
Error Amplifier
As depicted in Figure 5-5, the error amplifier is a two-stage amplifier. The differential inputs are connected to the slope detector’s outputs which have common-mode voltage about 0.8 V, so that the PMOS input stage is adopted in the error amplifier. To enhance the gain of the input stage, the negative impedance technique (M3 and M4) is used at its loading. In general, the conductance of (M3 and M4) is always 0.4 to 0.9 times than that of diode loading (M5 and M6) due to a stable condition. Besides, the second stage is designed to make output swing as large as possible. Thus, the DC gain of the error amplifier can be described as:
( )
And the dominant pole is located in the output node that is
( )
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5.2 Output Buffer
Impedance matching
In order to prevent the echoes or ISI, the impedance of each ends will be matched. To take an example of our OEICs, the buffer output travels on the PCB and transmission line to reach the sampling scope (see Figure 5-6). Because the transmission line has characteristic impedance of 50 Ω and the input impedance of the scope is 50 Ω, the guide line on PCB will be designed characteristic impedance of 50 Ω, and output impedance of the buffer as well.
Input Capacitance
The input capacitance of output buffer will be designed as small as possible. A large input capacitor directly contributed to the preceding stage and may degrade the bandwidth. Thus, a buffer with small input capacitance will be designed to relax the specifications of LA.
Bandwidth
In addition, the bandwidth of output buffer will be designed as high as possible to prevent bandwidth degradation of systems. Typically, the output impedance will be small.
Power Consumption
With a typical impedance level of 50 Ω, the output buffers or drivers must provide a large output current so as to produce enough voltage swing. Thus, it gets more and more important so as to lead the growing demand of low power consumption buffers.
Figure 5-6 Connection of this OEIC and an oscilloscope through a transmission line.
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5.2.1 Output Buffer Implementation
In the following, the output buffer implementations will be discussed. This includes the open-drain output buffer, simple differential output buffer and fT-doubler output buffer.
Open-Drain Output Buffer
As illustrated in Figure 5-7, the buffer exhibits relatively high output impedance which isn’t matched to the 50 Ω. At higher speeds, such mismatches create significant reflections that travel back to the buffer, see a high impedance mismatch at the near end, are reflected again, and reach the far end with some delay with respect to the original signal. As a result, the reception may experience ISI. The simulated eye diagram for a data rate of 10 Gbps in 0.18-µm technology is shown in Figure 5-8(a). The differential output waveform is subjected to severe ISI so as to destroy eye diagram. Its can be described as:
1 1,2
where gm1,2 is the tranconductance of M1 and M2, and RTL is transmission line’s characteristic impedance, 50 Ω.
Figure 5-7 Open-drain output buffer.
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Figure 5-8 Open-drain output buffer.
M1 M2
Figure 5-9 A simple differential stage.
Simple Differential Output Buffer
As shown in Figure 5-9, the output buffer can also implemented by a simple differential amplifier with 50 Ω load for near-end termination. Compared to the open-drain buffer, it minimizes the reflections form the near-end. However, the 50 W load reduces the gain to be 0.5 times that of open-drain buffer with constant current consumption.
The gain of a simple differential output buffer can be described as:
The simulated eye diagram is shown in Figure 5-8(b). Compared to Figure 5-8(a), the eye diagram opens very clearly, but the differential output swing is reduced to about ±200 mV.
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Figure 5-10 FT-doubler output buffer.
FT-Doubler Output Buffer
For output buffer, large transistor size is necessary to achieve such a large current.
Unfortunately, the large size will produce substantial parasitic capacitance that will decrease the signal bandwidth. To alleviate the load to preceding gain stages, a fT-doubler [12] circuit shown in Figure 5-10 is adopted. Compare fT-doubler with a simple differential stage with the same drive capability, one can get the idea that fT-doubler has smaller input capacitance.
The gain of fT-doubler output buffer can be also described as: amplifier. But, its current consumption is larger than a simple differential amplifier by 2 times and output capacitance as well.
5.2.2 Output Buffer Comparison
Table 5-1 and Table 5-2 list the comparisons between the three types of output buffers, which are open-drain output buffer, simple differential output buffer and fT-doubler output