Chapter 6 Optical Receiver Realizations
6.3 Performance Benchmark
Table 6-3 summarizes the performances of the state of the art and our own designs. In the row of wavelength, the 850-nm wavelength optical light is used by all of us.
In the row of architecture, the optical receiver integrates the PD, the TIA and LA on a single chip except for [6] in Table 6-3. Since [6] has not integrated the limiting amplifier, it has not shown the output swing voltage in the reported journal. Also, the output swing of our OEICs is larger then [19] and [2] by 3.2 times and 8 times, respectively. Thus, the power consumption of our OEICs is also large, and most of the power is dissipated by the limiting amplifier.
In the row of maximum speed, our OEIC with SML detector is the most high-speed in the table.
Compared with the same SML detector in [19], [2] and our 1st OEIC, the sensitivities are about the same. Nevertheless, [6] has the sensitivity level of -19 dBm with the BER less than 10-11 owing to the high responsivity PD and complicatedly equalizer. Because the different equalizers and different weighting in [6], the OEIC may suffer from PVT variation and low yield rate.
Compared to the equalizer of [6], ours only exits a zero which is to compensate the roll-off of the SML detector. Besides, our OEICs are high integrated owing to a PD, a TIA and a LA on a single chip.
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Chapter 7
Conclusion
This thesis describes the design of monolithically-integrated optical receiver front-end fabricated in TSMC 0.18µm one-poly and six-metal generic CMOS technology. To achieve small form factor and cost-down, a photodetector, a transimpedance amplifier and a post limiting amplifier are fully integrated in a single chip. Furthermore, the design methodology and implementation techniques of optical receiver were presented. Major research results can be summarized as follows.
First, two gigabit-per-second photodetectors are implemented for high-speed operation in the optical communication. One is the spatially modulated light (SML) detector consisting of a row of photodetectors alternatively covered and uncovered with light-blocking materials;
the other is the novel PIN detector emulated by P+diffusion / P-well / N+diffusion interleaved architecture.
Second, a trans-impedance amplifier with high-speed operation is demonstrated. The bandwidth is enhanced by the following techniques. (i) A low input impedance TIA is
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implemented by regulated cascode gain stage composed of a common gate amplifier with its gate controlled by a negative local feedback loop. (ii) A Shunt-Shunt feedback technique is adopted to reduce the impedance of each node in TIA.
Third, a limiting amplifier is accomplished. A Cherry-Hooper circuit structure with active feedback is realized to achieve high-speed operation owing to its higher gain-bandwidth product. Further, a fT-doubler output buffer is designed to reduce the capacitive load to the preceding stage.
Finally, an adaptive equalizer with a zero is incorporated to enhance the system bandwidth.
The zero can be adjusted by a feedback control loop which detects the edge slope of signal waveforms. The two OEICs are implemented in a 0.18 µm digital CMOS process, the input sensitivity levels with BER less than 10-12 at 3.125 Gbps and 2.5 Gbps are about -4.2 dBm and -7 dBm respectively, and the differential output swing is fixed at 800 mVpp.
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Appendix A
PCB Layout
Figure A-1 shows PCB layout by using Allegro, and Figure A-2 shows the board measured 60 mm x 42 mm with all the components soldered as well. The critical high-speed output signal paths are routed as short as possible to reduce the parasitic capacitance on the PCB.
Figure A-1 Top layer of the PCB layout composed of 4 layers with RF-4.
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Figure A-2 The PCB photograph measured 60 mm x 42 mm.
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References
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Vita
姓名 : 黃 世 豪
(Shih-Hao Huang)性別 : 男
出生日 : 1983.06.08
住址 : 940 屏東縣枋寮鄉太源村(路)40 號之
1 E-Mail：
[email protected]學歷 : 屏東縣立太源國民小學 (1989.09 ~ 1995.06)
屏東縣立枋寮國民中學 (1995.09 ~ 1998.06)
高雄市立高雄高級中學 (1998.09 ~ 2001.06)
國立交通大學電機與控制工程系 (2001.09 ~ 2005.06)
國立交通大學電子研究所碩士班 (2005.09 ~ 2008.09)
論文名稱 : 相容於標準金氧半技術之光接收機前端電路
Monolithically-Integrated Optical Receiver Front-End in Standard CMOS Process