Gain Cell Design

Figure 4-6 Gain cell in the limiting amplifier.

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Figure 4-7 Active feedback architecture.

2

This result reveals that the active feedback increases the GBW beyond the technology fT by a factor equal to the ratio of f_T and the cell -3dB bandwidth.

Moreover, the subtractor, depicted in Figure 4-8, is also based on the Cherry-Hooper amplifier with active feedback. Compared to Figure 4-7, I_B1a, I_B1b and (L/W)_M1,2 will reduce to

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half if to keep the current consumption and transistor overdrive voltage. Thus, it is given

1 2 subtractor gain due to TIA and DC offset cancellation network, respectively.

To summarize the subtractor, it not only delivers a path for the DC offset voltage been cancelled, but also reduces the TIA’s output capacitance for TIA to be capability of achieving higher bandwidth owing to half transistor size.

Figure 4-9 to Figure 4-13 show the limiting amplifier post-simulated results. To minimize ISI induced data jitter, the limiting amplifier is design as voltage gain of 47 dB, while the front 3 stages deliver voltage gain of 29 dB and -3 dB bandwidth of 3.1 GHz.

Figure 4-8 Subtractor schematic in the limiting amplifier.

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Figure 4-9 Magnitude responses of subtractor, gain cell and slicer.

Figure 4-10 Magnitude responses of LA and front 3 stage.

And the gain of a subtractor, a gain cell and a slicer are 3.6 dB, 9.7 dB and 8.4 dB, while the -3 dB bandwidth is 4.8 GHz, 4.8GHz and 5GHz, respectively. The group delay variation of LA with buffer is about ±15 ps from 10 MHz to 2.5 GHz. Besides, the input-referred noise is about 1.6 mVrms if the noise-bandwidth is about 2.5 GHz.

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Figure 4-11 Group delay of LA.

Figure 4-12 Input-referred noise of LA.

4.4 Summary

According to the post-layout simulated results, the limiting amplifier is able to operate for 3.2 Gbps data rate. It has a voltage gain of 47 dB (including 29 dB linear gain), group delay less than +/- 15 ps, input-referred noise about 1.6 mV_rms.

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Figure 4-13 Simulated eye diagram of LA.

Table 4-1 Post-layout simulated results (RCC) of limiting amplifier.

Specifications @ SS Corner

Gain (front 3-stage) 28 dB 29 dB

LA Gain 44 dB 47 dB

- 3dB BW (front 3-stage) 3.125 GHz 3.1 GHz

Group Delay Variation N.A. +/- 15 ps

Power Consumption N.A. 92 mW

Table 4-1 lists the simulated results of the limiting amplifier with a subtractor in the front, a DC offset cancellation network, 5-stage gain cell limiting amplifier (including 3-stage linear gain cell and 2-stage slicer gain cell).

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Chapter 5

Adaptive Equalizer and Buffer

To compensate the bandwidth roll-off of a photodetector, a high-pass filter will be designed.

In order to compensate the roll-off automatically, an equalizer with adjustable zero, two slope detectors and an error amplifier are adopted. In this chapter, an adaptive equalizer will be discussed first. Following equalizer, the high-speed output buffer is described in section 5.2.

5.1 Equalizer Circuit

To compensate the bandwidth degradation of SML detector, a high-pass filter will be designed.

Typically, we can use the capacitance/resistance source degeneration, as shown in Figure 5-1, to create a zero, and the equivalent transconductance of this differential amplifier is given by:

( )

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(a) (b)

Figure 5-1 (a) Capacitance/resistance degeneration, (b) frequency response..

In the above equation, it contains a lower frequency zero located in 1/(RSCS), and a higher frequency pole located in (1 + g_m1,2R_S /2) /( R_SC_S), thus it seems like a high-pass filter.

The equalizer [18] is shown in Figure 5-2. In contrast to the gain cells, it introduces a tunable zero in the transconductance stage of the Cherry-Hooper amplifier. As discuss before, the bandwidth of the SML photodetector is about 1.6 GHz. To compensate the bandwidth degradation of SML detector, the zero of equalizer should be adjusted around 1.6 GHz so as to cover bandwidth variations and fulfill the requirement of high speed operation.

R1 R2

Figure 5-2 The equalizer circuit.

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Adaptive Equalizer & Slope Detector

The schematic of adaptive equalizer is shown in Figure 5-3. The equalizer provides additional zero to compensate the bandwidth degradation caused by the photodetector. The zero location is adjusted by a feedback control loop which detects the edge slope of the output waveforms in the last two stages. In the slope detector, compare the steep slope of input differential signals with the slow one, the output averaging voltage is higher when steep slope signal is applied. The slope detector followed by an error amplifier which provides a low frequency pole to make sure a stable loop and delivers a DC signal to equalizer.

The slope detector can be realized as shown in Figure 5-3. It consists of a differential amplifier with the drain node connected to the V_DD. When a differential signal (v_inx or v_iny) is applied to the gates of the differential amplifier (M1x, M2x or M1y, M2y), it looks like transient time detector. In addition, its output voltage is higher if the differential input slope is steeper, and vice versa. For example (see Figure 5-4), if the slop of viny is steeper than vinx, the average voltage of v_outy is higher than v_outx. After amplified by the error amplifier, V_CTRL drops and the zero of equalizer goes higher. On the other hand, if the slop of vinx is steeper than viny, the average voltage of v_outy is lower than v_outx, V_CTRL arises and the zero of equalizer goes lower and peaking more.

Figure 5-3 Adaptive equalizer.

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(a) (b)

Figure 5-4 Transient simulation of the slope detector.

How much output voltage drop as a pair of differential signal is applied to slope detector?

Assume the input voltage swing of slope detector is, v_swing, from V_DD - v_swing to V_DD. The output has minimum voltage as M1X and M2X drift equal current. Thus, it can be described as:

min time, it can be described as:

max

And the output swing of the slope detector is

B

The above equation means the output voltage swing depends on the tail current, transistor size and input voltage swing.

For a slow transition of either polarity, the coupled-source node voltage is minimum value when the differential input is 1 or 0. And the response of any input transient is a negative pulse. However, a faster transient will have smaller pulse amplitude due to its short period of changing state.

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Figure 5-5 Two stage error amplifier.

Error Amplifier

As depicted in Figure 5-5, the error amplifier is a two-stage amplifier. The differential inputs are connected to the slope detector’s outputs which have common-mode voltage about 0.8 V, so that the PMOS input stage is adopted in the error amplifier. To enhance the gain of the input stage, the negative impedance technique (M3 and M4) is used at its loading. In general, the conductance of (M₃ and M₄) is always 0.4 to 0.9 times than that of diode loading (M5 and M6) due to a stable condition. Besides, the second stage is designed to make output swing as large as possible. Thus, the DC gain of the error amplifier can be described as:

( )

And the dominant pole is located in the output node that is

( )

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5.2 Output Buffer

Impedance matching

In order to prevent the echoes or ISI, the impedance of each ends will be matched. To take an example of our OEICs, the buffer output travels on the PCB and transmission line to reach the sampling scope (see Figure 5-6). Because the transmission line has characteristic impedance of 50 Ω and the input impedance of the scope is 50 Ω, the guide line on PCB will be designed characteristic impedance of 50 Ω, and output impedance of the buffer as well.

Input Capacitance

The input capacitance of output buffer will be designed as small as possible. A large input capacitor directly contributed to the preceding stage and may degrade the bandwidth. Thus, a buffer with small input capacitance will be designed to relax the specifications of LA.

Bandwidth

In addition, the bandwidth of output buffer will be designed as high as possible to prevent bandwidth degradation of systems. Typically, the output impedance will be small.

Power Consumption

With a typical impedance level of 50 Ω, the output buffers or drivers must provide a large output current so as to produce enough voltage swing. Thus, it gets more and more important so as to lead the growing demand of low power consumption buffers.

Figure 5-6 Connection of this OEIC and an oscilloscope through a transmission line.

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5.2.1 Output Buffer Implementation

In the following, the output buffer implementations will be discussed. This includes the open-drain output buffer, simple differential output buffer and f_T-doubler output buffer.

Open-Drain Output Buffer

As illustrated in Figure 5-7, the buffer exhibits relatively high output impedance which isn’t matched to the 50 Ω. At higher speeds, such mismatches create significant reflections that travel back to the buffer, see a high impedance mismatch at the near end, are reflected again, and reach the far end with some delay with respect to the original signal. As a result, the reception may experience ISI. The simulated eye diagram for a data rate of 10 Gbps in 0.18-µm technology is shown in Figure 5-8(a). The differential output waveform is subjected to severe ISI so as to destroy eye diagram. Its can be described as:

1 1,2

where gm1,2 is the tranconductance of M1 and M2, and RTL is transmission line’s characteristic impedance, 50 Ω.

Figure 5-7 Open-drain output buffer.

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Figure 5-8 Open-drain output buffer.

M1 M2

Figure 5-9 A simple differential stage.

Simple Differential Output Buffer

As shown in Figure 5-9, the output buffer can also implemented by a simple differential amplifier with 50 Ω load for near-end termination. Compared to the open-drain buffer, it minimizes the reflections form the near-end. However, the 50 W load reduces the gain to be 0.5 times that of open-drain buffer with constant current consumption.

The gain of a simple differential output buffer can be described as:

The simulated eye diagram is shown in Figure 5-8(b). Compared to Figure 5-8(a), the eye diagram opens very clearly, but the differential output swing is reduced to about ±200 mV.

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Figure 5-10 FT-doubler output buffer.

FT-Doubler Output Buffer

For output buffer, large transistor size is necessary to achieve such a large current.

Unfortunately, the large size will produce substantial parasitic capacitance that will decrease the signal bandwidth. To alleviate the load to preceding gain stages, a f_T-doubler [12] circuit shown in Figure 5-10 is adopted. Compare fT-doubler with a simple differential stage with the same drive capability, one can get the idea that f_T-doubler has smaller input capacitance.

The gain of fT-doubler output buffer can be also described as: amplifier. But, its current consumption is larger than a simple differential amplifier by 2 times and output capacitance as well.

5.2.2 Output Buffer Comparison

Table 5-1 and Table 5-2 list the comparisons between the three types of output buffers, which are open-drain output buffer, simple differential output buffer and f_T-doubler output

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buffer, with the same gain and with the same output swing.

In our designs, the impedance matching is very important because the data rate is above 3 Gbps with PRBS signal. Thus, to get rid off the ISI due to microwave reflection in the output, the open-drain output buffer is not suitable for our design.

Besides, in order to relax the specifications of LA, the fT-doubler is chosen owing to its low input capacitance.

Table 5-1 Buffer’s performance comparison with the same DC gain.

Near-End

Table 5-2 Buffer’s performance comparison with the same output swing.

Near-End

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Chapter 6

Optical Receiver Realizations

This chapter presents the realization of monolithic CMOS optical receiver analog front-ends (AFE) with two kinds of CMOS photodetectors. Both two optical receiver front-ends are capable of delivering 800 mV_pp to 50 Ω output loads after optical to electrical conversion. Moreover, they are implemented in a standard 0.18 µm digital CMOS technology.

Section 6.1 illustrates that the first optical receiver front-end which integrates a SML detector, a TIA, and a post limiting amplifier on a single chip. Also, the OEIC architecture, simulated results and measured results will be discussed.

We propose and utilize a lateral PIN detector emulated by P⁺diffusion / P-well / N⁺diffusion interleaved architecture and surrounded by N-well and deep N-well to enhance the PD’s responsivity and bandwidth. In section 6.2, the second monolithically-integrated receiver front-end is introduced. It also integrates the novel lateral PIN detector, a TIA, and a limiting amplifier on a single chip.

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6.1 A 3.125 Gbps AFE with SML Detector

6.1.1 SML Detector

An approach of fully CMOS optical receiver with high speed operation is by employing SML detector. According to the simulated results, the responsivity is about 62 mA/W, while -3 dB bandwidth is about 2.1 GHz by the SML detector which consists of 10 N-well/P-substrate dark detectors (size: 2.1 µm x 65 µm) and 10 N-well/P-substrate illuminated detectors (size:

2.1 µm x 65 µm) interleaved. To characterize more accurately the performance of the SML detector, it was integrated with on-chip transimpedance amplifier for measurement.

The experimental results are shown in Figure 6-1. The measured -3 dB bandwidth is about 1.6 GHz. Compared to the N-well/P-substrate PN junction PD, whose -3 dB bandwidth is about 10 MHz. In other words, the SML detector can improve the photodetector bandwidth by more than 2 orders. However, its bandwidth is still insufficient for a receiver operated above 3 Gbps.

Figure 6-1 Measured magnitude response of SML detector.

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Regulated Cascode TIA Post Limiting Amplifier Buffer

VDD

Figure 6-2 Optical receiver front-end architecture.

6.1.2 Architecture

This section describes the design of a 3.125 Gbps optical receiver, which monolithically integrates a photodetector (PD), a TIA and a post limiting amplifier (PA) in a generic 0.18-µm CMOS technology. The architecture of the optical receiver is shown in Figure 6-2.

High speed operation is achieved by utilizing SML detector incorporating with adaptive analog equalizer. In order to achieve an operating speed above 3 Gbps, adaptive equalizer is also adopted to compensate the modest frequency response of the SML detector which is measured 1.6 GHz in -3dB bandwidth.

The transimpedance amplifier with a RGC stage at the input node is capable of tolerance the large photodetector capacitance. The simulated results (in section 3.3) show the TIA provides a conversion gain of about 60 dBΩ, and a -3dB bandwidth of about 2.9 GHz to compromise between input-referred noise and ISI.

The five-stage limiting amplifier with 3-stage linear amplifier and 2-stage slicer (in section 4.3) is able to switch the signal at data rate 3.125 Gbps. Also, the fT-doubler output buffer with smaller input capacitance is utilized to relax the specifications of the limiting amplifier.

To the authors’ knowledge, this is the fully integrated CMOS optical receiver that exhibits the highest operating speed reported to date. Besides, due to a relatively low responsivity of the SML detector, no automatic gain control circuit is needed in this design.

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6.1.3 Test Chip

The layout of this optical receiver front-end with SML detector is shown in Figure 6-3. This chip is implemented by 0.18 µm one-poly six-metal CMOS process, and measured 0.99 µm by 0.71 µm which is dominated by the limiting amplifier. It exhibits 30 I / O pads, and the pad descriptions are listed in Table 6-1. There are 22 pads connected to neither V_DD or G_ND, 3 pads (#1, #3 and #21) connected to large bypass capacitance of 0.1 µF, 2 output pads (#19 and #20) connected to the AC coupling capacitance of 0.1 µF and delivering the output signals to sampling scope, Agilent 86100C, 1 pad (#10) being the input signal to control the zero location of the equalizer in case that the adaptive function fails, 1 pad (#11) connected to the variable resistance of 20 kΩ to adjust the input biasing current to the correct operating point, and the other 1 pad (#16) being unused.

Figure 6-3 Chip layout of OEIC with SML detector.

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Table 6-1 The pad descriptions of OEIC with SML detector.

PAD # Description PAD # Description

The measurement setup is shown as Figure 6-4. The OEIC is mounted on a printed circuit board for measurement. The eye diagrams and the bit error rate performance are characterized using Anritsu MP1800. The pattern generator in the Anritsu MP1800 sends a 2³¹-1 PRBS test pattern to modulate an 850-nm New Focus 10 Gbps VCSEL as a light source. VSCEL generates the 850-nm wavelength optical light which is guided by the multimode fibers and Cascade lightwave probe (fixed in the RF-1 Cascade probe station) to the photodetector on the OEIC. Between VCSEL and lightwave probe, the optical power is attenuated by OZOptics digital attenuator for input sensitivity measurement. After amplifying the photocurrent, the OEIC sends a pair of differential output signal back to the Anritsu MP1800 for bit-error-rate test. At the same time, Anritsu MP1800 sends the unity-gain buffer output and trigger signal to the Agilent 86100C for eye diagram measurement.

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Figure 6-4 Measurement setup.

6.1.4 Measurement Results

The chip micrograph is shown in Figure 6-5. Implemented in a generic 0.18-µm CMOS technology, the total chip area is about 710 µm by 990 µm. The area of photodetector is 65 µm by 65 µm to comply with the diameter of the multi-mode fiber.

The TIA is powered with a 3.3 V supply to provide a sufficient voltage headroom for the photodetector, while the limiting amplifier is operated under a single 1.8 V supply. The total power dissipation is 175 mW, among which 30 mW is consumed by the output buffer. By cascading transimpedance amplifier and limiting amplifier on a single chip, the optical receiver provides a conversion gain of 110 dBΩ. The overall f_H-3dB is about 2.46 GHz, which is limited by the photodetector. It is capable of delivering 800 mVpp differential voltage swings to 50 Ω output loads directly.

The bit error rate performance is summarized in Figure 6-6. As the responsivity of the photodetector is only about 62 mA/W, the input sensitivity levels with BER less than 10^-12 at 2.5 Gbps and 3.125 Gbps are about -5.8 dBm and -4.2 dBm respectively. Figure 6-7 and Figure 6-8 show the measured eye diagrams at 2.5 Gbps with the maximum input power, -3

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dBm, and the input sensitivity level (-5.8 dBm). The data jitters are about 16.64 psrms (111.11 ps_pp) and 19.79 ps_rms (133.33 ps_pp), respectively. In addition, Figure 6-9 and Figure 6-10 shows the measured eye diagrams at 3.125 Gbps with -3 dBm, and the input sensitivity level (-4.2 dBm). The data jitters are about 17.04 ps_rms (108.44 ps_pp) and 16.86 ps_rms (120.89 ps_pp), respectively.

Figure 6-5 Chip micrograph of OEIC with SML detector.

Figure 6-6 Measured bit error rate performance of the OEIC.

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Figure 6-7 Eye diagram at 2.5 Gbps with the maximum input power, -3 dBm.

Figure 6-8 Eye diagram at 2.5 Gbps with sensitivity level, -5.8 dBm.

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Figure 6-9 Eye diagram at 3.125 Gbps with the maximum input power, -3 dBm.

Figure 6-10 Eye diagram at 3.125 Gbps with sensitivity level, -4.2 dBm.

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6.2 A 2.5 Gbps AFE with PIN Detector

6.2.1 PIN Detector

As shown in Figure 2-9, the PIN detector is 50 µm × 50 µm in active area and consists of 13 P-I-N fingers, the P+ and N+ stripes are 1.45-µm wide, separated by a 0.5-µm wide P-well region. Thus a reasonable low (~ 2 to 6 V) reverse biased voltage (VR) is sufficient to deplete the P-well region of the photodetector for a high speed operation. According to the simulated results, the responsivity is about 73 mA/W, while -3 dB bandwidth is about 1.9 GHz.

6.2.2 Architecture

This section describes the design of a 2.5 Gbps optical receiver, which monolithically integrates a PD, a TIA and a limiting amplifier in a generic 0.18-µm digital CMOS technology.

A novel PIN detector is proposed and adopted in the design without technology modification.

The architecture of fully integrated optical receiver is shown in Figure 6-11. The incoming signal is converted to a photo current by an on-chip PIN detector, and regenerated to a voltage signal of 800 mVpp by a transimpedance amplifier (TIA), a limiting amplifier (LA). To alleviate bandwidth degradation by parasitic capacitance of photodetector, a regulated cascode

Figure 6-11 Optical receiver architecture

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(RGC) topology is adopted as the input stage. In addition, the responsivity of this PIN detector is not large enough to have an automatic gain control circuit in this design.

The transimpedance amplifier with a RGC stage at the input node is capable of tolerance the large photodetector capacitance. The simulated results (in section 3.3) show the TIA provides a conversion gain of about 60 dBΩ, and a -3dB bandwidth of about 2.9 GHz to compromise between input-referred noise and ISI.

The five-stage limiting amplifier with 3-stage linear amplifier and 2-stage slicer (in section 4.3) is able to switch the signal at data rate 2.5 Gbps. Also, the f_T-doubler output buffer with smaller input capacitance is utilized to relax the specifications of the limiting amplifier.

6.2.3 System Simulation Results

Figure 6-12 to Figure 6-15 show the post-simulated results of the OEIC with PIN detector in

Figure 6-12 to Figure 6-15 show the post-simulated results of the OEIC with PIN detector in

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