T HESIS O RGANIZATION - 低電壓差動訊號傳輸標準之平面顯示器資料接收器設計

Chapter 1 Introduction

1.3 T HESIS O RGANIZATION

The chapter 2 of the thesis would discuss the low-voltage differential signaling (LVDS) standard. The detail DC specifications, signal level and applications of LVDS standard are presented. In the chapter 3, the architecture and implementation of a CDR are discussed. A modified architecture of CDR would be presented and compared with the traditional architecture. The chapter 4 would discuss each building block of the modified architecture presented in chapter 3. How each block is implemented would be presented in this chapter.

In chapter 5, the measurement results of the LVDS receiver fabricated in 0.13-μm CMOS process would be present. In chapter 6 are conclusion and future works.

Table 1.1 The video resolutions and the corresponding specificity

Resolutions SVGA XGA SXGA UXGA

Pixels 800 600

1024

× 768 1280 × 1024 1600 1200 ×

Fig. 1.1 A typical serial link and its components

DRC

Fig. 1.2 A typical FPD Link application

d30 d31 d32 d33 d34 d35 d36 Input

clock Channel 3

d20 d21 d22 d23 d24 d25 d26 Channel 2

d10 d11 d12 d13 d14 d15 d16 Channel 1

d00 d01 d02 d03 d04 d05 d06 Channel 0

Fig. 1.3 The timing relation between input data and input clock in channels

d30 d31 d32 d33 d34 d35 d36 Input

clock Channel 3

d20 d21 d22 d23 d24 d25 d26 Channel 2

d10 d11 d12 d13 d14 d15 d16 Channel 1

d00 d01 d02 d03 d04 d05 d06 Channel 0

Skew between channel 1 and input clock

Fig. 1.4 The timing relation between data and clock when skews happen

Chapter 2 Specifications of Low-Voltage Differential Signaling (LVDS)

2.1 S

TANDARDS OF

LVDS

There are two industry standards that define LVDS [1]. One of the two standards is the generic electrical layer standard defined by the TIA (Telecommunications Industry Association) [2]. This standard is known as ANSI/TIA/EIA-644. The other application specific standard is the standard defined by the IEEE (Institute for Electrical and Electronics Engineering), which is titled SCI (Scalable Coherent Interface) [3]. In this thesis, the receiver is designed following the IEEE standard, SCI.

The original SCI is specified in IEEE standard 1596-1992. The original standard provides computer-bus-like services but uses a collection of fast point-to-point links instead of a physical bus in order to reach far higher speeds. This basic specification defines differential ECL (Emitter Coupled Logic) signals, which provide a high transfer rate (16 bits are transferred every 2 ns). However, because this specification only addressed the high data rates required and didn’t address the low power concerns, this original specification is inconvenient for some applications. Thus, SCI-LVDS specified in IEEE 1596.3 was defined as a subset of SCI. SCI-LVDS specifies signaling levels (electrical specifications) for not only the high-speed but also the low-power physical layer interface. Besides, SCI-LVDS also defines the encoding for packet switching used in SCI data transfers.

2.2 I

NTRODUCTION OF

LVDS

The primary goal of IEEE standard for LVDS is to create a physical layer specification for drivers and receivers and signal encoding suitable for use with the SCI as specified by IEEE standard 1596-1992 in low-cost workstation and personal computer applications. In this thesis, because our research focuses on the receiver, following introduction of LVDS will focus on the specification for receivers.

2.2.1 Configuration

Fig. 2.1 shows a typical LVDS interface, which is connected point-to-point. In the LVDS interface, the driver sends a low-voltage swing (400 mV single-ended maximum) differential signal to the receiver with a very high data rate (in IEEE standard for LVDS the data rate is reach 500 Mbits per second per signal pair), and low power dissipation. The power consumption is low because signal swings are small. The LVDS driver drives a minimum 2.5 mA current through a 100-ohm termination resister and switches the direction of current to change the value of data carried by the differential signal. Because the driver load is an uncomplicated point-to-point 100-ohm transmission line environment, the driver can switch the direction of the current through the termination resister in a high speed.

LVDS is independent of the physical layer transmission media. As long as the media deliver the signals to receiver with adequate noise margin and within the skew tolerance range, the interface will be reliable. This is a great advantage when using cables to carry LVDS signals. Sine all connections are point-to-point connected, physical links between nodes are independent of other node connections in the same system. This allows for freedom in developing a useful interconnection that fits the needs of application cases.

In IEEE LVDS standard, the physical environment of point-to-point connections between circuit boards is divided into two cases. First case is for the connections used

between two or more different circuit boards, which must operate with tolerance for Vgpd

(approximately 1 V for 2.5 V powered system). Second case is for the connections used on a PCB or similar environment that will guarantee V

gpd is less than 50 mV. In each of these two different cases, the IEEE LVDS standard has different specification. IEEE LVDS standard calls the first as general purpose link and second case as reduced rang link. In this thesis, because the receiver is designed for a FPD Link, which is used between the motherboard and the TFT LCD panel, all the designs are follow the specification in the general purpose link case.

2.2.2 Driver Output Levels

The output signal of the driver is in a small-swing differential voltage when the driver is properly terminated. Fig. 2.2 shows the differential signal and the relation between the two single-ended outputs. The differential signal is composed of the two single-ended outputs. Because this two single-ended outputs switch alternately, the driver keeps the current constant. The load resistance determines the differential voltage level. In differential application cases the load resistance is different, but in most cases the load resistance is 100-ohm. Fig. 2.2 shows the case where a current source is providing a 4 mA current and the outputs are switching the current at a 50% duty cycle.

Fig. 2.2 also shows the receiver threshold limits in relation to the single-ended signals that arrive at the receiver inputs. When the magnitude of the differential signal is exceeds the threshold voltage, the receiver would determine the logic of input data is switched. In IEEE LVDS standard, a differential voltage grater than or equal to Vidth(max) is a logic high, and less than or equal to Vidth(min) is a logic low.

In ideal case, the amplitude and common-mode voltage of the steady-state differential signals would not change, but in application case, both of the amplitude and common-mode voltage would change. Thus, IEEE LVDS standard defines the acceptable range of these

changes on signal level. Fig. 2.3 defines the change range of the differential voltage (Δ Vod) and the driver offset voltage (Δ Vos) in IEEE LVDS standard. Δ Vod and ΔVos can also be defined in a expression way. Equation (2-1) and equation (2-2) are the definitions of Δ Vod

and ΔVos respectively.

Table 2.1 shows the detail of the driver specification in general purpose link case in IEEE LVDS standard.

2.2.3 Receiver Input Level

Fig. 2.4 shows the receiver signal level. When the differential input signal is greater than +Vidth, the receiver would detect the input data as logic high. If the input signal were lower than –Vidth, the receiver would detect the input data as logic low. To eliminate the possibility of oscillating receiver output signal when the differential input signal is undefined, the threshold hysteresis is needed in receiver design. The undefined input signal may occur when the receiver inputs are unconnected, or when the connected driver is powered down. Fig. 2.5 shows the receiver hysteresis. When the input signal is changing between +Vidth and –Vidth, the receiver would not change the output state.

When the link is operated between two different circuit boards, the different ground-potential may shift the common-mode voltage level. To avoid the error recovered data induced by the different common-mode level happen, the specificity defines an acceptable common-mode voltage range. Fig. 2.6 shows the Vicm waveform. Vicm defined as the average of Via and Vib measured with respect to the receiver ground potential. Besides the different potential between driver ground and receiver ground, noise couple between channels would also induce the move of the common-mode level. IEEE standard limits the maximum shift value of common-mode level, and defines the Vicm(max) and Vicm(min) to limit the range of the input Vicm waveform.

A link system transmitting parallel signals must consider the effect of skews. Because the different channel environments or noise couples, the synchronous signals transmitted through different channels may arriver the receiver in different time. On the other hand, the synchronous signals become asynchronous after transmitted through different channels, and skews between signals must be considered when the receiver recovers these parallel signals.

IEEE standard defines the range of skews, and in this rang the receiver must be able to recover data with skews correctly. Fig. 2.7 defined the tskew for propose of IEEE standard.

To set the specificity of signal level more completely IEEE standard defines another two kind of skews for generated differential signal beside tskew. Skew 1 called tskew1 is the skew between the high-to-low and low-to-high transitions of complementary single-ended signal.

Fig. 2.8 shows the definition of tskew1, and equation (2-3) defines tskew1 in expression. Skew 2 called tskew2 is the skew between any differential signals measured at the output of driver.

Fig. 2.9 shows the definition of tskew2, and equation (2-4) defines tskew2 in expression.

skew HLA LHB

t = tp −tp

or

tp_HLB−tp_LHA (2-3)

Where tpHLA/B and tpLHA/B are the propagation delays on driver output A and B for high

to low and low to high.

2 [ ] [ ]

skew diff diff

t = tp i −tp j (2-4)

Where i is any one of the parallel signals and j is any other signal.

Table 2.2 shows the detail of the receiver specification in general purpose link case in IEEE LVDS standard.

Table 2.1 LVDS driver specification in general purpose link case

Symbol Parameter Conditions Min Max Units Voh Output voltage high, Voa or Vob Rload = 100Ω ±1% 1475 mV Vol Output voltage low, Voa or Vob Rload = 100Ω ±1% 925 mV

|Vod| Output differential voltage Rload = 100Ω ±1% 250 400 mV Vos Output offset voltage Rload = 100Ω ±1% 1125 1275 mV

Ro Output impedance, single ended Vcm = 1.0 V and 1.4 V 40 140 Ω

ΔRo Ro mismatch between A & B Vcm = 1.0 V and 1.4 V 10 %

|ΔVod| Change in |Vod| between “0” and “1” Rload = 100Ω ±1% 25 mV

ΔVos Change in Vos between “0” and “1” Rload = 100Ω ±1% 25 mV Isa, Isb Output current Driver shorted to

ground 40 mA

Isab Output current Driver shorted to

together 12 mA

|Ixa|, |Ixb| Power-off output leakage Vcc = 0 V 10 mA

Clock Clock signal duty cycle 250 MHz 45 55 %

tfall Vod fall time, 20-80% Zload = 100Ω ±1% 300 500 ps trise Vod rise time, 20-80% Zload = 100Ω ±1% 300 500 ps

tskew1 Differential skew Any differential pair on

package 50 ps

tskew2 Channel-to-channel skew Any two signals on

package 100 ps

Table 2.2 LVDS receiver specification in general purpose link case

Symbol Parameter Conditions Min Max Units Vi Input voltage range, Via or Vib |Vgpd| < 925 mV 0 2400 mV

Vidth Input differential threshold |Vgpd| < 925 mV –100 +100 mV Vhyst Input differential hysteresis Vidhh– Vidhl 25 mV Rin Receiver differential input impedance –––––– ^{90 110}^mV

tskew

Skew tolerable at receiver input to meet

set-up and hold time requirements Any two package inputs 600 Ω

Interconnect Receiver

Driver

V

O+

V

O-V

I+

V

I-V

gpd

100

Fig. 2.1 Typical LVDS interface

LVDS V

= 1.4 V

Fig. 2.2 The driver signal level of LVDS for 1.2V VOS

Voa

+V

–V

+V

^idth

–V

^idth

undefined logic state

Fig. 2.4 Receiver input signal levels

V^out (receiver output single-ended signal)

V^idthh

V^idthl V^{idth (max)}

V^{idth (min)}

Vⁱⁿ (receiver input differential signal)

Fig. 2.5 Receiver hysteresis

V

^icm

(max)

V

^icm

(min) V

^icm

f = 0 Hz to 1 GHz

Fig. 2.6 Vicm input waveform

2 ns

t

^skew

V

[i]

V

[i]

V

[j]

V

[j]

V

[i]

V

[j]

Fig. 2.7 tskew between two receiver inputs

t

^skew1

V

^os

V

^oa

V

^ob

Fig. 2.8 tskew1 between complementary single-ended signals

t

^skew2

0 V

^od

0 V

^od

V

^od

[i]

V

^od

[j]

Fig. 2.9 tskew2 between any parallel signals

Chapter 3 Architecture of Data Recovery System

3.1 T

RADITIONAL

D

ESIGN

In a typical FPD Link, there are four data channels and one clock channel as shown in Fig 3.1. The driver serializes seven parallel data into one channel. Fig 3.2 shows the timing relation between clock and serialized data. The data rate of each serialized data is seven times the frequency of the clock. However, the different parasitic effect in each channel will induce different time delay and distortion on each transmitted data and clock. Because the different channel effect, these signals will become asynchronous after arrive the receiver. In ideal case, no skews happen after channel effect, the receiver needs only a PLL (phase lock loop) to lock the input clock and proffer seven different data-sampling clock phases and by using these different sampling clock phases the receiver can recover the serial data into seven parallel data with data rate the same as the clock frequency (in FPD Link there are seven different data are serialized in each channel in one clock period). Fig. 3.3 shows the operation timing in the idea case. In application cases, skews between any two signals are unavoidable and the seven different data-sampling clock phases may locate nearly transition edges of the serial data as shown in Fig. 3.4. If the sampling clock phase is near the transition edge, the changing data may be missed or double sampled as shown in Fig 3.5.

Thus, to avoid these error data induced by skews happen the recovery system needs an extra mechanism to detect the happen of skews and shift the sampling clock phases away the transition edges of the each serial signal to make sure that these data can be sampled in stable state.

3.2.1 Three Times Oversampling

In traditional design, three times oversampling is usually used in recovery system [4] - [6]. In FPD Link using three times oversampling needs a PLL proffer 21 different sampling clock phases, three times the number of serial data in one clock period. By using these 21 different sampling clock phases, the recovery system can oversample each datum three times as shown in Fig. 3.6. However, when the skews between data and clock happen, the oversampled results of the same datum may be different as the logic state of serial data is changing. Fig. 3.7 shows the sampling timing relation when the skew between serial data and clock happens.

By detecting the different between sampled data sampling the same serial datum, three times oversampling system can detect whether the skew happens or not. Fig. 3.8 shows the timing relation between sampling clock phases and serial data when different skews happen.

In Fig. 3.8 (a), as the sampling clock phases lag input serial data stream by a certain amount, data transition might appear between second and third sampled data value within data information set. In Fig. 3.8 (b), if the sampling clock phases lead the input serial data stream by a certain amount, data transition might appear between first and second data value within data information set. In case Fig. 3.8 (c), the input serial data stream is lock by the sampling clock phases, and the first, second and third data value within data information set are the same.

3.2.2 Phase Selecting

Fig. 3.9 shows the architecture of a traditional CDR (clock and data recovery circuit) [4]. It consists of two input buffer, a data sampler, a synchronizer, a phase detector, a voter, a DLPF (digital low pass filter), a phase selector, and a PLL (phase lock loop). One of these two input signal is serial input data in LVDS signal, and another one is input clock in LVDS signal too.

At first, these two input buffer transmit input signals from LVDS signals into full-swing signals. The PLL locks the full-swing input clock and provides the data sampler 21 different sampling clock phases. Because the data rate of input serial data stream is seven times the frequency of input clock, the data sampler uses these 21 different sampling clock phases provided by PLL to sample each serialized datum three times. After data sampler, the input data stream is divided into 21 bits data. However, because these 21 bits data are sampled by different sampling clock phase these 21 bits data translate in different time. On the other hand, the 21 bits data are asynchronous as shown in Fig 3.10. To reduce the complexity of the recovery system, the synchronizer is used to synchronize the 21 bits asynchronous data.

By comparing every three sampled data of each serial datum, the phase detector can detect if any serial datum is lagged or leaded. If one datum were detected lead or lag, the first sampled result is different from the second and third sampled results or the third result is different from the first and second results, the phase detector would send a signal “up” or

“down” in a couple bits, one “up” bit and one “down” bit, as the phase detecting result of this datum. Thus, in each clock period the phase detector would send out seven couple bits as detecting result signals of these seven serial data respectively.

However, because the effect of jitters these seven detecting result signal would not always the same. For example, one “up” result and three “down” results appear in one clock period as shown in Fig. 3.11. After the phase detector is a voter. The voter would receive seven couple bits from the phase detector in every clock period. Each couple bits carry the detection information of one serial datum in this clock period. By comparing these “up” bits and “down” bits in these seven couple bits, the voter must determine whether the input serial data stream leads the input clock or lags. If the “up” signals is over tow bits more than the “down” bits, the voter would send out another “up” signal. On the other hand, if the

“down” signals are over two bits more than the “up” bits, the voter would send out another

“down” signal.

In application cases, the effect of jitters is serious and that means the jitters disperse in a large rang. Thus the voter is not enough to avoid the wrong “up” or “down” signal induce by the effect of jitters. To increase the jitter tolerance of the CDR, after voter the “up” or

“down” signal must pass the DLPF, that means the DLPF would not let the “up” or “down”

signal pass unless the “up” or “down” bit must keep in high logic for three consecutive clock periods at least. If the “up” or “down” bit keeps in high logic over three consecutive clock periods the DLPF would send out anther real “up” or “down” signal.

The phase selector would receive a couple of bits, one real “up” bit and one real

“down” bit, in every clock period. If the DLPF pass a real “up” signal to the phase selector, the phase selector would accept the detection that the input serial data stream leads these 21 sampling clock phases and shift up these 21 different sampling clock phases one phase let faster sampling clock phases sample the input serial data stream in next clock period.

Similarly, if the DLPF pass a real “down” signal to the phase selector, the phase selector would accept the detection that the input serial data stream lags these 21 sampling clock phases and shift down these 21 different sampling clock phases one phase let slower sampling clock phases sample the input serial data stream in next clock period. Fig. 3.12 shows the operation of the phase selector.

These detecting system will keep shifting these data sampling clock phases up or down until there are no real “up” and real “down” signals are send into the phase selector and that mean the three times oversampling is in lock state. Fig. 3.13 shows the timing relation between the input serial data stream and the input clock in lock state. In lock state, when jitters happen the first sampled datum and third sampled datum may be an error datum that sampled in wrong datum but the second sampled datum would keep the same logic stat with

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