Receiver Input Level - I NTRODUCTION OF LVDS

Chapter 2 Specifications of Low-Voltage Differential Signaling (LVDS)

2.2 I NTRODUCTION OF LVDS

2.2.3 Receiver Input Level

Fig. 2.4 shows the receiver signal level. When the differential input signal is greater than +Vidth, the receiver would detect the input data as logic high. If the input signal were lower than –Vidth, the receiver would detect the input data as logic low. To eliminate the possibility of oscillating receiver output signal when the differential input signal is undefined, the threshold hysteresis is needed in receiver design. The undefined input signal may occur when the receiver inputs are unconnected, or when the connected driver is powered down. Fig. 2.5 shows the receiver hysteresis. When the input signal is changing between +Vidth and –Vidth, the receiver would not change the output state.

When the link is operated between two different circuit boards, the different ground-potential may shift the common-mode voltage level. To avoid the error recovered data induced by the different common-mode level happen, the specificity defines an acceptable common-mode voltage range. Fig. 2.6 shows the Vicm waveform. Vicm defined as the average of Via and Vib measured with respect to the receiver ground potential. Besides the different potential between driver ground and receiver ground, noise couple between channels would also induce the move of the common-mode level. IEEE standard limits the maximum shift value of common-mode level, and defines the Vicm(max) and Vicm(min) to limit the range of the input Vicm waveform.

A link system transmitting parallel signals must consider the effect of skews. Because the different channel environments or noise couples, the synchronous signals transmitted through different channels may arriver the receiver in different time. On the other hand, the synchronous signals become asynchronous after transmitted through different channels, and skews between signals must be considered when the receiver recovers these parallel signals.

IEEE standard defines the range of skews, and in this rang the receiver must be able to recover data with skews correctly. Fig. 2.7 defined the tskew for propose of IEEE standard.

To set the specificity of signal level more completely IEEE standard defines another two kind of skews for generated differential signal beside tskew. Skew 1 called tskew1 is the skew between the high-to-low and low-to-high transitions of complementary single-ended signal.

Fig. 2.8 shows the definition of tskew1, and equation (2-3) defines tskew1 in expression. Skew 2 called tskew2 is the skew between any differential signals measured at the output of driver.

Fig. 2.9 shows the definition of tskew2, and equation (2-4) defines tskew2 in expression.

skew HLA LHB

t = tp −tp

or

tp_HLB−tp_LHA (2-3)

Where tpHLA/B and tpLHA/B are the propagation delays on driver output A and B for high

to low and low to high.

2 [ ] [ ]

skew diff diff

t = tp i −tp j (2-4)

Where i is any one of the parallel signals and j is any other signal.

Table 2.2 shows the detail of the receiver specification in general purpose link case in IEEE LVDS standard.

Table 2.1 LVDS driver specification in general purpose link case

Symbol Parameter Conditions Min Max Units Voh Output voltage high, Voa or Vob Rload = 100Ω ±1% 1475 mV Vol Output voltage low, Voa or Vob Rload = 100Ω ±1% 925 mV

|Vod| Output differential voltage Rload = 100Ω ±1% 250 400 mV Vos Output offset voltage Rload = 100Ω ±1% 1125 1275 mV

Ro Output impedance, single ended Vcm = 1.0 V and 1.4 V 40 140 Ω

ΔRo Ro mismatch between A & B Vcm = 1.0 V and 1.4 V 10 %

|ΔVod| Change in |Vod| between “0” and “1” Rload = 100Ω ±1% 25 mV

ΔVos Change in Vos between “0” and “1” Rload = 100Ω ±1% 25 mV Isa, Isb Output current Driver shorted to

ground 40 mA

Isab Output current Driver shorted to

together 12 mA

|Ixa|, |Ixb| Power-off output leakage Vcc = 0 V 10 mA

Clock Clock signal duty cycle 250 MHz 45 55 %

tfall Vod fall time, 20-80% Zload = 100Ω ±1% 300 500 ps trise Vod rise time, 20-80% Zload = 100Ω ±1% 300 500 ps

tskew1 Differential skew Any differential pair on

package 50 ps

tskew2 Channel-to-channel skew Any two signals on

package 100 ps

Table 2.2 LVDS receiver specification in general purpose link case

Symbol Parameter Conditions Min Max Units Vi Input voltage range, Via or Vib |Vgpd| < 925 mV 0 2400 mV

Vidth Input differential threshold |Vgpd| < 925 mV –100 +100 mV Vhyst Input differential hysteresis Vidhh– Vidhl 25 mV Rin Receiver differential input impedance –––––– ^{90 110}^mV

tskew

Skew tolerable at receiver input to meet

set-up and hold time requirements Any two package inputs 600 Ω

Interconnect Receiver

Driver

V

O+

V

O-V

I+

V

I-V

gpd

100

Fig. 2.1 Typical LVDS interface

LVDS V

= 1.4 V

Fig. 2.2 The driver signal level of LVDS for 1.2V VOS

Voa

+V

–V

+V

^idth

–V

^idth

undefined logic state

Fig. 2.4 Receiver input signal levels

V^out (receiver output single-ended signal)

V^idthh

V^idthl V^{idth (max)}

V^{idth (min)}

Vⁱⁿ (receiver input differential signal)

Fig. 2.5 Receiver hysteresis

V

^icm

(max)

V

^icm

(min) V

^icm

f = 0 Hz to 1 GHz

Fig. 2.6 Vicm input waveform

2 ns

t

^skew

V

[i]

V

[i]

V

[j]

V

[j]

V

[i]

V

[j]

Fig. 2.7 tskew between two receiver inputs

t

^skew1

V

^os

V

^oa

V

^ob

Fig. 2.8 tskew1 between complementary single-ended signals

t

^skew2

0 V

^od

0 V

^od

V

^od

[i]

V

^od

[j]

Fig. 2.9 tskew2 between any parallel signals

Chapter 3 Architecture of Data Recovery System

3.1 T

RADITIONAL

D

ESIGN

In a typical FPD Link, there are four data channels and one clock channel as shown in Fig 3.1. The driver serializes seven parallel data into one channel. Fig 3.2 shows the timing relation between clock and serialized data. The data rate of each serialized data is seven times the frequency of the clock. However, the different parasitic effect in each channel will induce different time delay and distortion on each transmitted data and clock. Because the different channel effect, these signals will become asynchronous after arrive the receiver. In ideal case, no skews happen after channel effect, the receiver needs only a PLL (phase lock loop) to lock the input clock and proffer seven different data-sampling clock phases and by using these different sampling clock phases the receiver can recover the serial data into seven parallel data with data rate the same as the clock frequency (in FPD Link there are seven different data are serialized in each channel in one clock period). Fig. 3.3 shows the operation timing in the idea case. In application cases, skews between any two signals are unavoidable and the seven different data-sampling clock phases may locate nearly transition edges of the serial data as shown in Fig. 3.4. If the sampling clock phase is near the transition edge, the changing data may be missed or double sampled as shown in Fig 3.5.

Thus, to avoid these error data induced by skews happen the recovery system needs an extra mechanism to detect the happen of skews and shift the sampling clock phases away the transition edges of the each serial signal to make sure that these data can be sampled in stable state.

3.2.1 Three Times Oversampling

In traditional design, three times oversampling is usually used in recovery system [4] - [6]. In FPD Link using three times oversampling needs a PLL proffer 21 different sampling clock phases, three times the number of serial data in one clock period. By using these 21 different sampling clock phases, the recovery system can oversample each datum three times as shown in Fig. 3.6. However, when the skews between data and clock happen, the oversampled results of the same datum may be different as the logic state of serial data is changing. Fig. 3.7 shows the sampling timing relation when the skew between serial data and clock happens.

By detecting the different between sampled data sampling the same serial datum, three times oversampling system can detect whether the skew happens or not. Fig. 3.8 shows the timing relation between sampling clock phases and serial data when different skews happen.

In Fig. 3.8 (a), as the sampling clock phases lag input serial data stream by a certain amount, data transition might appear between second and third sampled data value within data information set. In Fig. 3.8 (b), if the sampling clock phases lead the input serial data stream by a certain amount, data transition might appear between first and second data value within data information set. In case Fig. 3.8 (c), the input serial data stream is lock by the sampling clock phases, and the first, second and third data value within data information set are the same.

3.2.2 Phase Selecting

Fig. 3.9 shows the architecture of a traditional CDR (clock and data recovery circuit) [4]. It consists of two input buffer, a data sampler, a synchronizer, a phase detector, a voter, a DLPF (digital low pass filter), a phase selector, and a PLL (phase lock loop). One of these two input signal is serial input data in LVDS signal, and another one is input clock in LVDS signal too.

At first, these two input buffer transmit input signals from LVDS signals into full-swing signals. The PLL locks the full-swing input clock and provides the data sampler 21 different sampling clock phases. Because the data rate of input serial data stream is seven times the frequency of input clock, the data sampler uses these 21 different sampling clock phases provided by PLL to sample each serialized datum three times. After data sampler, the input data stream is divided into 21 bits data. However, because these 21 bits data are sampled by different sampling clock phase these 21 bits data translate in different time. On the other hand, the 21 bits data are asynchronous as shown in Fig 3.10. To reduce the complexity of the recovery system, the synchronizer is used to synchronize the 21 bits asynchronous data.

By comparing every three sampled data of each serial datum, the phase detector can detect if any serial datum is lagged or leaded. If one datum were detected lead or lag, the first sampled result is different from the second and third sampled results or the third result is different from the first and second results, the phase detector would send a signal “up” or

“down” in a couple bits, one “up” bit and one “down” bit, as the phase detecting result of this datum. Thus, in each clock period the phase detector would send out seven couple bits as detecting result signals of these seven serial data respectively.

However, because the effect of jitters these seven detecting result signal would not always the same. For example, one “up” result and three “down” results appear in one clock period as shown in Fig. 3.11. After the phase detector is a voter. The voter would receive seven couple bits from the phase detector in every clock period. Each couple bits carry the detection information of one serial datum in this clock period. By comparing these “up” bits and “down” bits in these seven couple bits, the voter must determine whether the input serial data stream leads the input clock or lags. If the “up” signals is over tow bits more than the “down” bits, the voter would send out another “up” signal. On the other hand, if the

“down” signals are over two bits more than the “up” bits, the voter would send out another

“down” signal.

In application cases, the effect of jitters is serious and that means the jitters disperse in a large rang. Thus the voter is not enough to avoid the wrong “up” or “down” signal induce by the effect of jitters. To increase the jitter tolerance of the CDR, after voter the “up” or

“down” signal must pass the DLPF, that means the DLPF would not let the “up” or “down”

signal pass unless the “up” or “down” bit must keep in high logic for three consecutive clock periods at least. If the “up” or “down” bit keeps in high logic over three consecutive clock periods the DLPF would send out anther real “up” or “down” signal.

The phase selector would receive a couple of bits, one real “up” bit and one real

“down” bit, in every clock period. If the DLPF pass a real “up” signal to the phase selector, the phase selector would accept the detection that the input serial data stream leads these 21 sampling clock phases and shift up these 21 different sampling clock phases one phase let faster sampling clock phases sample the input serial data stream in next clock period.

Similarly, if the DLPF pass a real “down” signal to the phase selector, the phase selector would accept the detection that the input serial data stream lags these 21 sampling clock phases and shift down these 21 different sampling clock phases one phase let slower sampling clock phases sample the input serial data stream in next clock period. Fig. 3.12 shows the operation of the phase selector.

These detecting system will keep shifting these data sampling clock phases up or down until there are no real “up” and real “down” signals are send into the phase selector and that mean the three times oversampling is in lock state. Fig. 3.13 shows the timing relation between the input serial data stream and the input clock in lock state. In lock state, when jitters happen the first sampled datum and third sampled datum may be an error datum that sampled in wrong datum but the second sampled datum would keep the same logic stat with the sampled datum because the second sampling clock phase would still be kept in the right datum. Thus, the CDR would select each second sampled result as the recovered datum of

each serial datum and send out these seven recovered data in parallel as the output of the CDR.

Besides, to differentiate the new architecture of CDR presented in following from the traditional design, the architecture of a traditional CDR is called “phase selecting”.

3.2 N

D

ESIGN

3.2.1 Three Quarter Steps Oversampling

Fig. 3.14 shows a typical architecture of a PLL. The number of VCO cells in a PLL is determined by the number of phases the PLL must provide. Besides, in application cases, these VCO cells are usually designed in fully differential and that can increase the stability of the PLL. Because these VCO cells are fully differential, these inverted phases can be used as the output phases of the PLL when the number of phase the PLL must provide is an even number. Thus, if a PLL is required to provide n phases where n is an even number, the PLL can use only n/2 VCO cells to provide n different phases dispreading in one clock period uniformly. Fig. 3.15 shows the relation between output phases of the VCO cells and output phases of the PLL when the PLL must provide 8 different phases in one clock period.

However, if the PLL must provide odd number phases, the PLL can’t use these inverted phases of VCD as output phases and a PLL providing n number phase where n is an odd number must use n VCO cells to provide these output phase the PLL must provide.

In application cases of FPD Link, because the input data stream is 7 bits deep signal serialized in one clock period, the PLL must provide 21 different sampling clock phases to implement three times oversampling. Because 21 is an odd number, the PLL can not use these inverted phases of VCO cells as a part of these 21 different sampling clock phases.

Thus, in three times oversampling the PLL must use 21 VCO cells to provide 21 different sampling clock phases dispreading uniformly in one clock period and that would make the

layout area of the PLL expand. However, the VCD is the primary part in the layout area of the PLL. To reduce the problem this thesis presents a modified process, which is called

“three quarter steps oversampling”, to recover data.

In “three quarter steps oversampling” the PLL provides 28 different sampling clock phases dispreading uniformly in one clock. Because there is seven data are serialized in one clock, there are four different sampling clock phases in ever data step and each distance between every two adjacent phases is equate to a quarter data step time. To detect the locations of skews between input data stream and input clock the “three quarter steps oversampling” would select three of these four phases in each data step to oversample each datum. Because each datum is oversampled three times and each distance between every two adjacent sampling clock phases is equate to a quarter step time, this modified process which is used to recover data is called “three quarter steps oversampling”. Because the PLL in “three quarter steps oversampling” provides 28 different sampling clocks phases where 28 is an even number, the PLL can use only 14 VCO cells to provide these sampling clock phases. Thus, the number of VCO cells used in “three quarter steps oversampling” is less than that used in “three times oversampling”. On the other hand, the layout area of the PLL used in “three quarter steps oversampling” will be smaller than the PLL used in “three times oversampling”. Fig. 3.16 shows the VCO cells of the PLL used in “three quarter steps oversampling” and “three times oversampling” respectively.

Fig 3.17 shows the operation of the “three quarter steps oversampling”. By using 21 of these 28 different sampling clock phases provided by the PLL, the CDR could detect whether the sampling clock phases lag input data stream or lead. If the sampling clock phases lag the input data stream as shown in Fig. 3.17 (a), the CDR would shift up these sampling clock phases one phase. If the sampling clock phases lead the input data stream as shown in Fig. 3.17(b), the CDR would shift down these sampling clock phases one phase.

The CDR would keep shifting these sampling clock phases until the input data stream is

locked by these sampling clock phases as shown in Fig. 3.17 (c).

Besides the improvement of reducing the layout area of PLL, the “three quarter steps oversampling” also has higher tolerance of input data eye diagram. Fig. 3.18 shows the timing relation between the eye diagram of the input data stream and the sampling clock phases in the “three quarter steps oversampling” case and the “three times oversampling”

case respectively. In “three quarter steps oversampling” the CDR can keep in lock state when the eye diagram of the input data stream closes nearly 50%, but in “three times oversampling” the eye diagram of the input data stream must open over 60% to keep the CDR in lock state.

3.2.2 Delay Selecting

Three quarter steps oversampling does reduce the size of PLL, but it also has another problem. There are only 21 phases used to sample data when three times oversampling is used, but there will be 28 phases used to sample data when three quarter steps oversampling is used. Using more different phases to sample data will make the layout of CDR more complex. Besides, because the sampling clock phases used in three quarter steps oversampling is more than that used in three times oversampling, the three quarter steps oversampling CDR need more MUXs to implement the motion of selecting sampling clock phases.

To overcome this problem, a new architecture of a CDR is presented in following.

Besides using three different sampling clock phase oversample data stream, using the same sampling clock phase sample three different delayed data can also detect the happen of skews too [9]. By using VCO cells as delay cell, the CDR can delay input data stream one phase, two phases, and three phases respectively. Using these three the same data streams delayed one phase, two phases, and three phases as a detection window, the CDR can use

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