VCO and Differential-to-Single-Ended Converter

Fig. 4.23 shows the schematic diagram of the VCO. The designed VCO is a 14 stages oscillator, which can provide 28 different clock phases. Seven of these 28 different clock phases would be sent out for the data sampler to sample the input data stream. The designed VCO cells, which were presented in reference [12], have low sensitivity and high noise rejection capability of the supply and substrate voltage. As the result, the output clocks of the VCO composed of these VCO cells has low jitter characteristic. However the output signal of the VCO cell is a low swing and differential signal, which can’t be used in the data sampler. To solute this problem, a differential-to-single-ended converter is needed. Fig. 4.24 shows the schematic diagram of the differential-to-single-ended converter. It is composed of two opposite phase NMOS differential amplifiers driving two PMOS common-source amplifiers connected by an NMOS current mirror. Because the two NMOS differential amplifiers use a NMOS current source the same as that used in the VCO cells, the converter can receive the correct common-mode input voltage level. These output signals of the differential-to-single-ended converter is full swing digital signals and can be used to sample the input data stream in the data sampler.

100 Ω

Fig. 4.1 Traditional LVDS input buffer

Vb1

out-Fig. 4.2 New design of LVDS receiver input buffer

Vddh

out-Fig. 4.3 LVDS receiver input buffer in this thesis

F3dB = 638 MHz

Fig. 4.4 Simulated frequency response of the LVDS receiver input buffer (Fig. 4.3)

Delay Cell Delay

Cell

M U X Delay

serial data stream Cell selected signal

3 [S0,S1,S2]

operational code form shift selector

Fig. 4.5 Architecture of the delay selector

V

^bn

V

^bp

V

ⁱⁿ⁺

V

in-V

^out-

V

^out+

Vddl

Fig. 4.6 Schematic diagram of the delay cell

V

out-V

out+

V

ⁱⁿ⁺

V

bn

V

in-Fig. 4.7 Schematic diagram of the differential to single ended converter

D0 D1 D2

Fig. 4.8 Simulation result of the delay cells and differential to the single ended converters

D1

D2

S1

S2

selected data D0

S0

Fig. 4.9 Schematic diagram of the three to one MUX

Data Sampler

7 21

Delay Cell

Delay Cell

Delay Cell Detection Window

Selected Data Stream

Sampling Clock Phases from PLL

Sampling Results

Fig. 4.10 Detection window and data sampler

d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6

d0 d1 d2 d3 d4 d5 d6

clk0 clk1 clk2 clk3 clk4 clk5 clk6 d0

Fig. 4.11 Operation timing of the data sampler

data0 data1 data2

Fig. 4.12 Schematic diagram and truth table of the phase detector

d0 d1 d2 d3 d4 d5 d6 d0 d1 d2 d3 d4 d5 d6

down down up down

jitter

data sampling

phases

clock

wrong detection results induced by jitters

Fig. 4.13 Wrong detection results induced by jitters

down0 down1 down6

up0 up1 up6

up M

pex

N1

Fig. 4.14 Schematic diagram of the voter

S0 UP=0

up up

up

up up

up up

up S1 UP=0

S2 UP=0 S3

UP=1

Fig. 4.15 State diagram of DLPF

DFF UP DOWN

UP

DOWN

S

^n-1

clock

S

ⁿ⁺¹

S

ⁿ

Fig. 4.16 Schematic diagram of the shift selector

Delay Selector

serial data stream Cell selected data stream

3

Fig. 4.17 Sifter selector and delay selector

PFD Charge

Fig. 4.18 Architecture of the designed PLL

TSPC-DFF

TSPC-DFF

INV

INV

INV

up

INV INV

CLK

fb INV

down

CLK

in

Delay Buffer reset

Fig. 4.19 Schematic diagram of the PFD

down down

V

bn

up up

V

o

V

ddl

Fig. 4.20 Schematic diagram of the charge pump

Vddl Vddl

V ^ctrl Vddl Vddl

V ^ctrl

C 1 C 2

R ¹ R ¹

C 1 C 2

Fig. 4.21 Schematic diagram of the loop filter

Vctrl

Vbp

Vbn

Start-up Circuit Amplifier Bias

Differential Amplifier Half-Buffer Replica

Control Voltage Buffer N1

Vddl

Fig. 4.22 Schematic diagram of the bias generator

Vbn

Fig. 4.23 Schematic diagram of the VCO

V

out-V

out+

V

in+

V

bn

V

in-Fig. 4.24 Schematic diagram of the differential-to-single-ended converter

Chapter 5

Experiment Results

Fig. 5.1 shows the layout and the die photo of the LVDS data recovery receiver fabricated in a 0.13-μm 1P8M CMOS process with 3.3V and 1.2V power supply. In the die photo Fig. 5.1(b) because the polymer layer can’t see the circuit under the polymer layer. In the tap out test chip there are two test circuits, serial output test circuit and parallel output test circuit. Fig. 5.2 shows the block diagram of the serial output test circuit in the tap out test chip. To simplify the process of testing whether the LVDS receiver recovers input data stream correctly or not, some test circuits are added in the test circuit. To reduce the channels must be observed, a serializer is used to serialize these recovered parallel data.

Because the serial recovered data is a high data rate data stream, a LVDS output buffer is needed to drive this high-speed data stream.

In the test process a known pattern is sent into the test chip and by observe the output data of the test circuit it can be verify that whether the LVDS receiver recovers input data stream correctly or not. If the LVDS receiver can actually recover the input data correctly the output data stream would be the same as the input pattern, or the output data stream would be different from the input pattern. Fig. 5.3 shows the measurement environment setting of the test for the serial output test circuit. The known differential data pattern and differential clock signals generated by the pulse pattern generator are sent into the test chip, and the output data stream is observed from the infiniium oscilloscope. Fig. 5.4 shows the top view of the serial output testing PCB photo and Fig. 5.5 shows the bottom view. In the testing of the serial output test circuit, besides a cyclic “010101” pattern, in this thesis a cyclic “1001001 0110110” pattern is also used to test the function of the test chip too. Fig.

5.6 ~ Fig. 5.9 show the test result when the cyclic “010101” pattern is sent into the test chip

at a data rate up to 1.1 Gb/s, 1.25 Gb/s, 1.8 Gb/s and 2 Gb/s respectively. When the data rate is 1.1 Gb/s, 1.25 Gb/s and 1.8 Gb/s the output data are all the same as the input pattern but when the data rate is up to 2 Gb/s there are some errors happen in the output data stream as shown in Fig. 5.9. Fig. 5.10 ~ Fig. 5.13 show the test result when the cyclic “1001001 0110110” pattern is sent into the test chip at a data rate up to 1.1 Gb/s, 1.25 Gb/s, 1.8 Gb/s and 2 Gb/s respectively. The same as the cyclic “010101” pattern, when the data rate is up to 1.1 Gb/s, 1.25 Gb/s and 1.8 Gb/s the output data are all the same as the input pattern but when the data rate is up to 2 Gb/s there are some errors happen in the output data stream as shown in Fig. 5.13. As the result, the upper boundary of the data rate that the LVDS receiver can recovers the input data correctly is 2 Gb/s and the lower boundary is 1.1 Gb/s.

Fig. 5.14 shows the block diagram of the parallel output test circuit in the tap out test chip. Because the data rate of the recovered parallel data is the same as the clock frequency, taper buffers are able to drive these recovered parallel data streams. Fig. 5.15 shows the measurement environment setting of the test for the parallel output test circuit. Fig. 5.16 shows the top view of the parallel output testing PCB photo and Fig. 5.17 shows the bottom view. In the testing, set a pattern lets the recovered data stream D0 is a cyclic “01” signal, and lets recovered data streams D1 and D6 are cyclic “0011” signals as shown in Fig. 5.18.

By observing recovered data streams D0, D1, D6 and recovered clock from the infiniium oscilloscope, it can be tested whether the LVDS receiver recovers input data streams correctly or not. By setting different delay time between data and clock, the skew tolerance of the LVDS receiver can be verified. If the positive or negative delay time is over the skew tolerance, the LVDS receiver would fail to recover data. As shown in Fig. 5.19(a), if the positive delay time is over the skew tolerance the recovered D0 would become a cyclic

“0011” signal and the D1 would become a cyclic “01” signal. If the negative delay time is over the skew tolerance the recovered D0 would become a cyclic “0011” signal and the D6 would become a cyclic “01” signal as shown in Fig. 5.19(b). Fig. 5.20 ~ Fig. 5.24 show the

testing result when setting the pulse pattern generator make a 0 ps, 100 ps, 150 ps, –600 ps and –650 ps skew between the input data and input clock respectively at 1.25 Gb/s data rate.

When the skew is between –600 ps and 100 ps the recovered data is correct D0 is a cyclic

“0101” signal and D1 and D6 are cyclic “00110011” signals. When the skew is –650 ps and 150 ps the recovered data is wrong. A reasonable assuming that a 200 ps skew between the input data and input clock on chip already exists when the pulse pattern generator set no skew happen. As the result, it is accepted that the skew tolerance of this LVDS receiver is more than ±300 ps which is ±37.5 % of the data step, 800 ps.

Fig. 5.25 shows the measurement environment setup of the LVDS Link test. Using the pulse generator provide a reference clock for the LVDS transmitter, the LVDS transmitter can serialize the on chip PRBS signals and send out the serial data stream in LVDS level.

The LVDS receiver receives the serial LVDS data stream and recovers these data into parallel full swing signals. Fig. 5.26 ~ Fig. 5.28 show the measurement result observing recovered clock and recovered data stream, D6, from the oscilloscope when the input data rate is 1.15 Gb/s, 1.4 Gb/s and 1.75 Gb/s respectively. Table 5.1 is the summary of the measurement result.

Table 5.1 Measurement result summary

Symbol Parameter Conditions Min Max Units

Vcm Input common mode voltage Vd = 400 mV 0 1270 mV

Vd Input differential voltage Vcm = 1 V 150 –– mV

fclk Input clock frequency Vcm = 1 V and Vd = 400 mV 165 250 MHz DR Input data rate Vcm = 1 V and Vd = 400 mV 1.11 1.8 Gb/s

tskew Skew tolerance between input signals DR = 1.25 Gb/s –350 350 ps

P Power consumption DR = 1.25 Gb/s –– 39.7 mW

Fig. 5.1 Layout and die photo of the tap out test chip

Fig. 5.2 Block diagrams of the serial output test circuit in the tap out test chip

Fig. 5.3 Measurement environment setting of the serial output test

Fig. 5.4 Top view of the serial output testing PCB photo

Fig. 5.5 Bottom view of the serial output testing PCB photo

0.9 ns

Fig. 5.6 Cyclic “010101” pattern test result at data rate up to 1.1 Gb/s

0.8 ns

Fig. 5.7 Cyclic “010101” pattern test result at data rate up to 1.25 Gb/s

0.57 ns

Fig. 5.8 Cyclic “010101” pattern test result at data rate up to 1.8 Gb/s

errors

Fig. 5.9 Cyclic “010101” pattern test result at data rate up to 2 Gb/s

0.9 ns

Fig. 5.10 Cyclic “1001001 0110110” pattern test result at data rate up to 1.1 Gb/s

0.8 ns

Fig. 5.11 Cyclic “1001001 0110110” pattern test result at data rate up to 1.25 Gb/s

0.57 ns 0

1 1 0 1 1 0 1 0 0 1 0 0 1

Fig. 5.12 Cyclic “1001001 0110110” pattern test result at data rate up to 1.8 Gb/s

errors

Fig. 5.13 Cyclic “1001001 0110110” pattern test result at data rate up to 2 Gb/s

Taper buffer D0

Data Recovery Circuit Circuits for Test

Taper buffer D1

Fig. 5.14 Block diagrams of the parallel output test circuit in the tap out test chip

Fig. 5.15 Measurement environment setting of the parallel output test

Fig. 5.16 Top view of the parallel output testing PCB photo

Fig. 5.17 Bottom view of the parallel output testing PCB photo

Fig. 5.18 Test pattern for skew tolerance test

Fig. 5.19 Error recovered data streams when data delay is over skew tolerance

D6 D0 D1 clock

Fig. 5.20 Parallel output testing result when no skew is set in pattern generator

D6 D0 D1 clock

Fig. 5.21 Parallel output testing result when set a 100ps skew in pattern generator

D6 D0 D1 clock

Fig. 5.22 Parallel output testing result when set a 150ps skew in pattern generator

D6 D0 D1 clock

Fig. 5.23 Parallel output testing result when set a –600ps skew in pattern generator

D6 D0 D1 clock

Fig. 5.24 Parallel output testing result when set a –650ps skew in pattern generator

Fig. 5.25 Measurement environment setup of the LVDS Link test

Clock: 165 MHz Data rate: 1.15 Gb/s clock

D6

Fig. 5.26 LVDS Link measurement result at data rate up to 1.15 Gb/s

Clock: 200 MHz Data rate: 1.4 Gb/s clock

D6

Fig. 5.27 LVDS Link measurement result at data rate up to 1.4 Gb/s

Clock: 250 MHz Data rate: 1.75 Gb/s clock

D6

Fig. 5.28 LVDS Link measurement result at data rate up to 1.75 Gb/s

Chapter 6

Conclusion and Future Works

6.1 C

ONCLUSION

In this thesis a LVDS CDR receiver is present and the function of LVDS receiver is all verified. The LVDS receiver is implemented in 0.13-μm 1P8M COMS process with 3.3 V and 1.2 V power supply. The LVDS receiver can recover the seven deep LVDS serial input data at data rate from 1.11 Gb/s to 1.8 Gb/s, which can suppose the FPD Link application for UXGA resolution. The skew tolerance of the implemented LVDS receiver is +350 ps

~ –350 ps when the input data rate is 1.25 Gb/s. The power consumption of the LVDS DCR receiver is less than 40 mW when the operation data rate is 1.25 Gb/s.

6.2 F

UTURE

W

ORKS

Although the LVDS CDR receiver is already presented in the thesis and the function of the implement receiver is verified, there are still some tasks can be improved. DLL, delay lock loop, is a circuit similar to the PLL. DLL can lock a reference clock the same as a PLL.

And the DLL can implement that with a layout area much smaller than PLL. It is an interesting topic to implement the LVDS DCR receiver with a DLL instead of the PLL.

REFERENCES

[1] LVDS Owner’s Manual & Design Guide, National Semiconductor Corp., Apr. 1997.

[2] Electrical characteristics of low-voltage differential signaling (LVDS) interface

circuits, TIA/EIA-664, National Semiconductor Corp., ANSI/TIA/EIA, 1996.

[3] IEEE standard for low-voltage differential signaling (LVDS) for scalable coherent

interface (SCI), 1596.3 SCI-LVDS standard, IEEE Std. 1596.3-1996, 1994

[4] S. Kim, K. Lee, D.-K. Jeong, D. D. Lee, and A. Nowatzyk, “An 800 Mbps multi-channel CMOS serial link with 3 X oversampling,” in Proc. IEEE Custom

Integrated Circuit Conf., 1995, pp. 451-454.

[5] K. Lee, Y. Shin, S. Kim, D.-K Jeong, G. Kim, B. Kim, and V. D. Costa, “1.04 GBd Low EMI Digital Video Interface System Using Small Swing Serial Link Technique,”

IEEE J. Solid-State Circuits, vol. 33, pp. 816-822, May 1998.

[6] S.-J. Jou, C.-H. Lin, Y.-H. Chen, and Z.-H. Li, “Module Generator of Data Recovery for Serial Link Receiver,” in Proc. IEEE SOC Conf., 2003, pp. 95-98.

[7] K. Lee, S. Kim, G. Ahn, and D. K. Jeong, “A CMOS Serial Link for Fully Duplexed Data Communication,” IEEE J. Solid-State Circuits, vol. 30, pp. 353-364, April 1995.

[8] C.-K. K. Yang and M. A. Horowitz, “A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links,” IEEE J. Solid-State Circuits, vol.31, no.12, pp.

2015-2023, Dec. 1996.

[9] Y. Miki, T. Saito, H. Yamashita, F. Tuki, T. Baba, A. Koyama, and M. Sonehara, “A

50-m W/ch 2.5-Gb/s/ch Data Recovery Circuit for the SFI-5 Interface With Digital Eye-Tracking,” IEEE J. Solid-State Circuits, vol. 39, no.4, pp. 613-621, Apr. 2004.

[10] A. Boni, A. Pierazzi, and D. Vecchi, “LVDS I/O interface for Gb/s-per-Pin Operation in 0.35- μ CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2004.

m

[11] I. A. Young, J. K. Greason, and K. L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessor,” IEEE J. Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, Nov. 1992.

[12] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.

[13] A. Maxim, B. Scott, E. M. Schneider, M. L. Hagge, S. Chacko, and D. Stiurca, “A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-um CMOS PLL based on sample-reset loop filter,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp.

1673-1683, Nov. 2001.

簡歷

VITA

姓 名： 吳 建 樺

學 歷：

台北市立建國高級中學 (85 年 9 月 ~ 88 年 6 月)

國立交通大學電子工程學系 (88 年 9 月 ~ 92 年 6 月)

國立交通大學電子研究所碩士班 (92 年 9 月 ~ 94 年 9 月)

研究所修習課程：

類比積體電路I 吳介琮教授

類比積體電路II 吳重雨教授

數位積體電路 柯明道教授

積體電路設計實驗I 李鎮宜教授

積體電路設計實驗II 李鎮宜教授

積體電路之靜電放電防護設計特論 柯明道教授

電腦輔助設計 周景揚教授

元件物理（一） 雷添福教授

射頻積體電路實驗 郭建男教授

Email：ukulely.ee88@nctu.edu.tw

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