Chapter 1 Introduction
1.2 T HESIS O RGANIZATION
The chapter 2 in the thesis discusses the structure and the device characteristics of SiGe HBTs and diodes. Five kinds of diodes including P-well/N-well diode, varactor (for voltage controlled capacitor) diode, and vertical base-collector (VBC) diode with different implantation types such as local-collector, high-speed, or without implantation are investigated. Three kinds of SiGe HBT devices are studied in this thesis, which are the low-voltage (LV) SiGe NPN HBT (BVceo = 3.8V, ft = 47GHz at Vbc = 1V), the high-voltage (HV) SiGe NPN HBT (BVceo = 6V, ft = 30GHz at Vbc
= 1V), and the high-speed (HS) SiGe NPN HBT (BVceo = 2.5V, ft = 70GHz at Vbc = 1V).
In chapter 3, a new design to minimize the leakage current of the diode string is proposed. Compared with the traditional P+/N-well diode string, this structure has a deep N-well to isolate P-well and the common P-substrate. An extra bias is applied to the deep N-well to minimize the substrate leakage current. The connection of deep N-well to the extra bias makes the parasitic n-p-n of the triple-well diode being slightly turned on. This current will flow into the next diode of the diode string, but not to the common P-substrate. So, the substrate leakage current can be effectively
decreased. A resistance is further connected between the bias voltage and the deep N-well to control the leakage current level through the diode string. As the substrate leakage current could be reduced, another leakage current path appears. Because of the parasitic n-p-n bipolar transistors of the triple well diode, the leakage current will be a mount of current flow through the junction between P-well and N+ under the high-temperature condition.
In chapter 4, the leakage current and ESD robustness of Low-Leakage-Current Diode String (LLCDS) as the power clamp circuit in SiGe BiCMOS process have been investigated. By calculating the relation between bias resistance and the leakage current of LLCDS, the leakage current of LLCDS can be minimized with specified value of bias resistance. Such LLCDS can be used as the power-rail ESD clamp circuit and ESD connection cell between the separated power rails, to provide effective ESD protection in SiGe BiCMOS process.
C HAPTER 2
Characteristics of ESD Devices in 0.35-µm SiGe BiCMOS Process
2.1 INTRODUCTION
SiGe HBT has become a key technology for RF applications in giga-bit communication systems. ESD protection in SiGe technology plays an important role in telecommunication system reliability [1]-[5]. In a SiGe BiCMOS process, with the consideration of Giga-HZ input signals, the SiGe HBT is also used as the on-chip ESD protection device to protect itself.
In the 1990s a further revolution in bipolar transistor design occurred with the emergence of SiGe HBTs. Previously heterojunction bipolar transistors had only been available in compound semiconductor technologies, such as AlGaAs/GaAs. However, material research showed that a good heterojunction could be obtained if the SiGe layer was thin and the Ge content relatively low.
As the results, the relation between ESD robustness and layout parameters of SiGe HBT should be characterized to achieve a good enough ESD protection design in such high-speed communication integrated circuits. Another successful ESD protection design for RF IC applications had been reported by using the double diodes with the turn-on-efficient power-rail ESD clamp circuit [6], [7].
The relation between ESD robustness and layout parameters of diodes with different junctions in SiGe BiCMOS process should be characterized for ESD protection design. With the detailed experimental results, the on-chip ESD protection
design for Giga-Hz RF circuits can be optimized with both considerations on RF performance and ESD robustness.
In this chapter, the test structures of SiGe HBT devices and diodes with different junctions or layout parameters have been fabricated in a 0.35-µm SiGe BiCMOS process to investigate their ESD robustness.
2.2 TEST STRUCTURE FOR DIODES AND HBTS
2.2.1 Diodes
Five kinds of diodes including P-well/N-well diode, varactor (for voltage controlled capacitor) diode, and vertical base-collector (VBC) diode with different implantation types such as local-collector, high-speed, or without implantation are investigated. Fig. 2.1 shows the top view and cross-sectional view of the P-well/N-well diode, which is used as a reference for comparing with the other diodes of different structures.
Varactor means voltage controlled capacitor; is used as a diode in this research because of the junction between P+ and N-(NEPI). Fig. 2.2 shows the top view and cross-sectional view of varactor (VR) diode, where the attention will focus to the junction between P+ and N- (NEPI).
Fig. 2.3 shows the top view and cross-sectional view of VBC diode with local collector (LC) implantation. The diode junction is formed between base poly (BP) and local collector region with NEPI. In this work, next kind of diode is formed by the part of HBT for SiGe process. The emitter poly is removed and put the contact right on the base poly. As the result, the current flow through the base and collector will be
vertical. The local collector (LC) implantation under the base poly region is further changed as high-speed implantation, or even no implantation in the diode structures to compare their ESD robustness.
In the test structures for investigation, the width (W) of diode junction is drawn in the range from 3 to 12 µm, and the length (L) of diode junction is drawn from 20 to 80 µm in this work.
2.2.2 HBT Devices
The structure of the SiGe HBT device is different from the CMOS bipolar transistor. The SiGe HBT is formed by emitter poly, base poly, and N+ buried layer.
Emitter poly is right on the base poly, and the base poly is right on the local collector region. The local collector region is connected with N+ buried layer and through N+
sinker to contact.
Three kinds of SiGe HBT devices are studied in this work, which are the low-voltage (LV) SiGe NPN HBT (BVceo = 3.8V, ft = 47GHz at Vbc = 1V), the high-voltage (HV) SiGe NPN HBT (BVceo = 6V, ft = 30GHz at Vbc = 1V), and the high-speed (HS) SiGe NPN HBT (BVceo = 2.5V, ft = 70GHz at Vbc = 1V). To investigate the ESD robustness of SiGe HBTs, the experimental chips had been fabricated in a 0.35-µm 3.3V/5V RF BiCMOS process.
The dependences of emitter length, emitter width, and base resistance on the ESD robustness are investigated for all LV, HV, and HS SiGe HBTs. Moreover, the pattern of high-speed implantation is also drawn with different style to investigate its impact on ESD robustness.
Fig. 2.4 shows the cross-sectional view of a low-voltage SiGe NPN HBT. An
N-type local collector (LC) implantation region is formed under the emitter poly and connecting to the N-type sinker through the bottom N+ buried layer. The N-type sinker is formed as the collector terminal. In the high-voltage SiGe NPN HBT for 5-V operating voltage, the LC implantation is not performed for increasing the breakdown voltage of base/collector junction. On the other hand, the LC implantation is replaced by a high-speed (HS) implantation with high concentration collector region to speed up the operating speed of the HBT device.
2.3 EXPERIMENTAL RESULTS
2.3.1 Diodes
The DC characteristics of these different structure diodes are shown in Fig. 2.5.
Different diode structures have different reverse breakdown voltages because of different densities of the P-N junction. Fig. 2.6 shows the breakdown voltages, defined at the current of 1 µA under reverse-biased condition, of different diode types.
From the experimental result, the junction between P-well and N-well has the highest breakdown voltage.
In the varactor (VR) diode with a junction between P+ and NEPI (N), this VR diode can work with good characteristics under forward and reverse biased conditions.
In the VBC diode with a junction between base poly and the local collector, it also has good characteristics under forward and reverse biased conditions. All of diodes whose leakage is less than 1nA under the normal power bias (Vdd = 3.3 V).
To observe the high current characteristics of ESD devices in SiGe BiCMOS process, transmission line pulsing (TLP) system with a pulse width of 100 ns is used
to measure the second breakdown current, It2 [8], [9]. Three diodes, the P-well/N-well diode, VR diode, and VBC+LC diode, are zapped by the TLP to find their It2. Besides TLP test, the ESD simulator is also used to measure the ESD level of devices. The ESD stress is performed with a commercial KeyTek ZapMaster ESD simulator. The start voltage of human-body-model (HBM) ESD stress is 50 V, and the step voltage is 500 V. Each measurement is performed on 2 samples, at least. Using this method, the ESD robustness of these devices can be investigated and discussed in this work.
The second breakdown current (It2) and HBM ESD robustness of the P-well/N-well diode, VR diode, and VBC+LC diode with different widths under forward-biased condition are shown in Fig. 2.7 and 2.8, respectively. The It2 and ESD robustness on the diode is increased when the diode width is increased, but that of the VBC+LC diode is not significantly improved when the diode width is further increased. Under forward-biased condition, P-well/N-well diode has the highest It2 and ESD level, which is a reference during designing the ESD protection circuit. So the P-well/N-well diode is suitable to be the ESD protection device under forward- biased condition.
Fig. 2.9 shows the second breakdown current (It2) of the P-well/N-well diode, VR diode, and VBC+LC diode with different widths under reverse-biased condition. In Fig. 2.9, the P-well/N-well diode, with a fixed length of 6 µm but different widths, has a very low second breakdown current. Although it has good ESD characteristics under forward-biased condition, it should be avoided in ESD protection design to use the P-well/N-well diode to discharge ESD current in the reverse-biased condition. For the VR diode and VBC+LC diode with a fixed length of 6 µm but different widths, their second breakdown currents are almost proportion to their widths.
Fig. 2.10 shows the dependence of HBM ESD robustness on the diode length of the VBC diode with a fixed width of 40 µm under the forward-biased condition. In Fig. 2.10, the ESD robustness of the VBC diode is independent to the diode length. So, the VBC diode can be drawn with the minimum length for saving layout area to get the same ESD level.
2.3.2 HBT with Different Emitter Lengths
Fig. 2.11 shows three types of ESD stress for the SiGe HBT device. There are BC ESD stress, BE ESD stress and CE ESD stress. BC ESD stress is stress the base node of the SiGe HBT; collector node is grounded and emitter node is floating. BE ESD stress is stress the base node of the SiGe HBT; emitter node is grounded and collector node is floating. CE ESD stress is stress the collector node of the SiGe HBT; emitter node is grounded and base node is floating. In order to study the ESD robustness of these SiGe HBT devices completely, every kind of the junction should be tested by ESD stress.
Fig. 2.12 shows the TLP I-V curve of the low-voltage SiGe HBT with different emitter lengths and a fixed emitter width of 0.45 µm under CE stress. Fig. 2.13 shows ESD robustness of the low-voltage SiGe HBTs with a fixed emitter width of 0.45 µm but different emitter lengths. All the low-voltage SiGe HBT devices only pass 50-V HBM ESD stress when emitter width equals to 0.45 µm. Because the HBM ESD level of the CE ESD stress is too small to see the difference under different emitter lengths, the TLP I-V curve can show the more clear value.
The similar results are also seen in the high-voltage SiGe HBTs with different emitter lengths, as that shown in Fig. 2.14 and Fig. 2.15. This may result from the too
small emitter width and higher junction breakdown voltage. Because the junction between base poly and local collector region has the largest area to deliver the heat under ESD stress, the HBM ESD level is highest in all ESD stress type.
Fig. 2.16 shows the TLP I-V curve of the high-speed SiGe HBT with different emitter lengths and a fixed emitter width of 0.45 µm under CE stress. The high-speed SiGe HBTs with the lowest junction breakdown voltage have an increasing ESD robustness with the increase of emitter length, as that shown in Fig. 2.17, where the emitter width also equals to 0.45 µm.
2.3.3 HBT with Different Emitter Widths
Fig. 2.18 shows the TLP I-V curve of the low-voltage SiGe HBT with different emitter width and a fixed emitter length of 30 µm under CE stress. Fig. 2.19 shows the ESD result versus the emitter width for the low-voltage SiGe HBTs under a fixed emitter length. In Fig. 2.19, the low-voltage SiGe HBT sustains higher ESD level when its emitter width is drawn larger than 0.45 µm, and achieves 800-V ESD robustness when its emitter width equals to 1.5 µm with emitter length of 20.3 µm.
This equals about 20 V/µm, which is double of the ESD level of the gate-grounded NMOS in the same BiCMOS process.
Fig. 2.20 shows the TLP I-V curve of the high-voltage SiGe HBT with different emitter width and a fixed emitter length of 30 µm under CE stress. Fig. 2.21 shows the ESD result versus the emitter width for the high-voltage SiGe HBTs under a fixed emitter length. In Fig. 2.21, the high-voltage SiGe HBT shows a relatively low ESD level. Only 200-V ESD level can be sustained, when its emitter width equals to 1.5 µm with emitter length of 20.3 µm.
Fig. 2.22 shows the TLP I-V curve of the high-speed SiGe HBT with different emitter width and a fixed emitter length of 30 µm under CE stress. Fig. 2.23 shows the ESD result versus the emitter width for the high-voltage SiGe HBTs under a fixed emitter length. Similarly, the ESD level increases, when the emitter width of high-speed SiGe HBT increases, as shown in Fig. 2.23. If the emitter width of SiGe HBT is fixed at 0.45 µm, the order of ESD robustness is: LV SiGe HBT = HV SiGe HBT < HS SiGe HBT.
However, when the emitter width of SiGe HBT is fixed at 1.5 µm, the order of ESD robustness is: LV SiGe HBT > HS SiGe HBT > HV SiGe HBT. This is a very interesting phenomenon, and more analysis and experimental measurement will be performed in our following future work to get a clear insight.
2.3.4 HBT with Different Base Resistances
Fig. 2.24 shows the cross-sectional view of a multi-finger SiGe HBT with 4 emitter fingers. The emitter window is 20.3 µm × 0.9 µm. The base resistance can be the minimum value, when all base terminals (B1, B2, B3, B4, and B5) are connected together through the contact layer on its top.
Table I shows the ESD robustness of the low-voltage SiGe HBT when all emitter nodes are grounded, where the ESD zapping are applied to the collector node with some base nodes are grounded, such as only node1 grounded, others floating, or node 1, 3 and 5 grounded, others floating. When all base terminals are connected together to ground, only 100-V HBM ESD stress is passed. The same result also appears when the base terminals B1, B3, B5 are connected to ground.
However, when only B1 and B3 are connected to ground, the ESD robustness will
increase to 1800 V. The floating on the base finger B5 significantly increases the ESD robustness of SiGe HBT. Table II shows the case of only one emitter and one base terminals connecting to ground. SiGe HBT with B1E2 grounded can sustain 700-V ESD stress. But, only 100-V ESD stress can be passed when B1E3 grounded. The above measured results show an interesting phenomenon, and more analysis and experimental measurement will be performed in our following work to get a clear explanation.
2.3.5 HBT with Different Layout Patterns
Fig. 2.25 shows the designed patterns in the high-speed SiGe HBT devices with different high-speed implantation regions. K1 is the standard layout of the high-speed SiGe HBT with unit-square shape. K2, K3, K4, and K5 are designed in different shapes for investigation. Because the SiGe HBT device is a vertical bipolar structure, the current flow may be affected by the different layout patterns of the N+ buried layer. The current flow is vertical from emitter to base, but is horizontal from N+
buried layer to N+ sinker. If the layout pattern of the N+ buried layer is discontinuously, the collector current will be harder flowing to the N+ sinker and the current distribution will not be uniform. As a result, the effect of delivering heat may be worse than other layout pattern.
Because the K4 pattern is parallel to the collector current, the current distributes uniformly, and the heat delivering may be better. As a result, The BC HBM ESD level of K4 layout pattern is the best. As for BE and CE HBM ESD level have less effect by changing N+ buried layer. The emitter window equals to 20.3 µm × 1.5 µm. The ESD robustness degrades with the designed patterns, as shown in Fig. 2.26. The standard
layout has ESD robustness about 22 V/µm, but the other patterns (K2, K3, K4, and K5) degrade to about only 50%.
2.4 CONCLUSION
Different electrostatic discharge (ESD) devices in a 0.35-µm Silicon germanium (SiGe) RF BiCMOS process are characterized in high current regime by transmission line pulse (TLP) generator and ESD simulator for on-chip ESD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with low-voltage (LV), high-voltage (HV), and high-speed (HS) implantations has been measured and compared in details.
The characteristics of diodes with different structures in the SiGe BiCMOS process have been investigated for using in ESD protection design. The diodes can work with good ESD robustness under forward-biased condition. The ESD robustness of SiGe hetrojunction bipolar transistor in the SiGe BiCMOS process has been also characterized.
If the emitter width of SiGe HBT is fixed at 0.45 µm, the order of ESD robustness is: LV SiGe HBT = HV SiGe HBT < HS SiGe HBT. However, when the emitter width of SiGe HBT is fixed at 1.5 µm, the order of ESD robustness is: LV SiGe HBT > HS SiGe HBT > HV SiGe HBT. With the proper layout parameters, SiGe HBT can perform double ESD robustness than that of NMOS device in the SiGe BiCMOS process.
P-well
W
P+
N+
N-well
L L
W
(a)
N-well P-well
P+ FOX
FOX N+ FOX
P-sub
Cathode Anode
(b)
Fig. 2.1 (a) Top view and (b) cross-sectional view of P-well/N-well diode in a SiGe BiCMOS process.
P+ N+
N+ W
L NEPI DT
(a)
NEPI
N Sinker N
Sinker
P+ FOX
FOX
N+ Buried Layer DT DT
Anode
Cathode
(b)
Fig. 2.2 (a) Top view and (b) cross-sectional view of varactor (VR) diode in a SiGe BiCMOS process.
Base Poly
Collector W
L NEPI
LC
DT
(a)
NEPI
Collector Sinker LC
FOX
N+ Buried Layer
DT Base Collector
DT
FOX BP
(b)
Fig. 2.3 (a) Top view and (b) cross-sectional view of vertical base-collector (VBC) diode in a SiGe BiCMOS process.
FOX FOX
Fig. 2.4 The device cross-sectional view of low-voltage SiGe NPN HBT with local collector (LC) implantation.
Fig. 2.5 The DC characteristics of these different structure diodes.
PW/NW VBC+LC VBC VR VBC+HS
Fig. 2.6 Breakdown voltage versus diode type when leakage current equals to 1 µA.
Length = 6 µm
Fig. 2.7 Comparisons of second breakdown current among the P-well/N-well diode, the VR diode, and the VBC+LC diode with different widths under forward-biased condition.
Length = 6 µm
Fig. 2.8 Comparisons of HBM ESD robustness among the P-well/N-well diode, the VR diode, and the VBC+LC diode with different widths under forward-biased condition.
Fig. 2.9 Comparison of second breakdown current among the P-well/N-well diode, VR diode, and VBC+LC diode with different widths under reverse-biased condition.
2 4 6 8 10 12 4600
4800 5000 5200 5400
HBM ESD Level (V)
Diode Length (
µm) VBC diode Width=40
µm
Fig. 2.10 HBM ESD robustness versus diode length of the VBC diode with the diode width of 40 µm under forward-biased condition.
Fig. 2.11 Three types of ESD stress for the SiGe HBT device.
Fig. 2.11 Three types of ESD stress for the SiGe HBT device.