Chapter 4 Minimization of Leakage Current in the Diode
4.3 E XPERIMENTAL R ESULTS
The design had been fabricated in a 0.18-µm BiCMOS SiGe process. During measurement, the cathode of LLCDS and the substrate are grounded with two separated channels, so that the cathode current and the substrate leakage current can be monitored separately. The DC characteristics of the conventional diode string, LLCDS, and LLCDS2 are shown in Fig. 4.8, Fig. 4.9, and Fig. 4.10, respectively.
According to experimental results, LLCDS and LLCDS2 can have lower substrate leakage current than the conventional diode string.
LLCDS and LLCDS2 have a lower substrate leakage current because there is a
bias applied in the node of deep N-well. In Fig. 4.12, the relationship between bias resistance (R) and the total leakage current through LLCDS with four diodes (N=4) is measured under different temperatures. Because the value of resistance is about kilo ohm order, the N-well resistance is used in these circuits. The total leakage current through the diode string (N=4) is increased when the temperature increases from 25°C to 125°C. Under this condition, the value of bias resistance can be optimized even under high temperature condition.
The relationship between bias resistance (R) and the total leakage current through LLCDS with four diodes (N=4) under different temperatures is shown in Fig.4.14.
Compared with Fig. 4.12, the total leakage current indeed reduces in advance.
Because adding more stage R, the parasitic bipolar junction transistor can work in saturation region without β gain of base current.
From the measured results, LLCDS (N=4) with a bias resistance of 10 kohm has a minimum leakage current. LLCDS indeed has a lower leakage current if the value of R was chosen properly. The equations to minimize the leakage current of LLCDS with different diode stages or different blocking voltages can be calculated from the aforementioned equations.
The relationship between voltage and the total leakage current of the conventional diode string, LLCDS, and LLCDS2 under 125°C for N=4 are shown in Fig. 4.15.
With a bias resistance of 20 kohm, the ESD robustness of LLCDS with different diode numbers in series is investigated by the transmission-line-pulse generator (TLP) with pulse width of 100ns. The dependence of secondary breakdown current (It2) of the conventional diode string, LLCDS, and LLCDS2 on the diode number (N) in series is shown in Fig. 4.16, where every diode has the same device dimension of W/L = 40µm/12µm in layout pattern. However, the secondary break-down current (It2) of the
conventional diode strings and LLCDS with different diode numbers (N) in series did not have obvious variation.
With an It2 of higher than 4A, the diode sting (under N=4) can sustain the human-body-model ESD level of 6 kV. In Fig. 16 the It2 of LLCDS does not decrease when diode number increases. Thus, the number of diodes in the diode string can be reasonably increased to get a higher blocking voltage without degrading the ESD robustness.
The relationship between Ro and total leakage current of the HBT triggered by the conventional diode string, HBT triggered by LLCDS, and HBT triggered by LLCDS2 under 125°C for N=4 are shown in Fig. 4.17. After adding a SiGe HBT, the leakage current was reduced substantially in LLCDS with a HBT while it was not reduced in the conventional diode string with a HBT. The conventional diode string has a smaller blocking voltage because of the serious substrate leakage current, so the VBE of the HBT would be higher than its counterpart in LLCDS with a HBT.
As a result, the leakage current of the conventional diode string with a HBT is much larger than LLCDS with a HBT under high-temperature condition. The TLP I-V curve of the HBT triggered by conventional diode string is shown in Fig. 4.18 for N=4 per unit area of the HBT. The TLP I-V curve of the HBT triggered by LLCDS is shown in Fig. 4.19 for N=4 per unit area of the HBT. The TLP I-V curve of the HBT triggered by LLCDS2 is shown in Fig. 4.20 for N=4 per unit area of the HBT.
Because the weakest point is at the collector-emitter junction of the HBT, the ESD robustness of these circuits will be limited by the HBT.
4.4 CONCLUSION
A new design for the diode string in 0.18-µm SiGe BiCMOS process has been proposed and verified. With the additional extra bias to supply little current into the deep N-well of diodes in the LLCDS, the overall leakage current of LLCDS can be minimized. By selecting a suitable bias resistance, the total leakage current of LLCDS can be kept much smaller than that of the conventional diode string. The new proposed LLCDS and the LLCDS-triggered SiGe HBT are very suitable for applying in the power-rail ESD clamp circuits in cooperation with the input ESD diodes to achieve good RF ESD protection design in the SiGe BiCMOS technology.
VDD
RF I/O
RF Circuits
Power-rail ESD clamp
circuit
VSS
Fig. 4.1 The whole-chip ESD protection design with the diode string applied in the power-rail ESD clamp circuit.
P-substrate
P+ N+ P+ N+ P+ N+
N-well N-well N-well
VDD VSS
FOX FOX FOX FOX FOX FOX FOX FOX
Fig. 4.2 The cross-sectional view of the conventional diode string.
Rbias
Fig. 4.3 The cross-sectional view of LLCDS in 0.18-µm BiCMOS SiGe.
VDD
Fig. 4.4 The equivalent circuit of LLCDS in 0.18-µm BiCMOS SiGe.
Fig. 4.5 The equivalent circuit of LLCDS2 in 0.18-µm BiCMOS SiGe.
V D D
Fig. 4.6 The circuit design on HBT triggered by diode for low-voltage power supply.
VDD
Fig. 4.7 The equivalent circuit of LLCDS applied in another power-rail ESD clamp circuit.
Fig. 4.8 The DC characteristics of the conventional diode string at 25°C.
0.0 0.5 1.0 1.5 2.0 2.5
Fig. 4.10 The DC characteristics of LLCDS2 at 25°C.
10k 20k 30k 40k 50k 60k 70k 80k 90k100k --25
30 35 40 45
Total Leakage Current ( µA)
Bias Resistance (ohm)
125
oC Simulation
Fig. 4.11 The simulation result of the relationship between bias resistance (R) and total leakage current of LLCDS with diode number of N=4 and bias condition of VDD=1.8V, at the temperatures of 125°C.
0 500 1k 10k 20k 50k 100k 1M 1E-8
1E-7 1E-6 1E-5 1E-4 1E-3
Total Leakage Current (A)
Bias Resistance (Ohm) T=25 oC
T=75 oC T=125 oC
Fig. 4.12 The relationship between bias resistance (R) and total leakage current of LLCDS with diode number of N=4 and bias condition of VDD=1.8V, measured at the temperatures of 25°C, 75°C, and 125°C, respectively.
0 20 40 60 80 100 7
8 9 10 11 12 13 14
Total Leakage Current (
µA)
R (kohm)
125
oC Simulation
Fig. 4.13 The simulation result of the relationship between bias resistance (R) and total leakage current of LLCDS2 with diode number of N=4 and bias condition of VDD=1.8V, at the temperatures of 125°C.
0 500 1k 10k 20k 50k 100k 1M 1E-7
1E-6 1E-5 1E-4
Total Leakage Current (A)
R (ohm)
T=25
oC
T=75
oC VDD=Vbias= 1.8V T=125
oC
Fig. 4.14 The relationship between bias resistance (R) and total leakage current of LLCDS2 with diode number of N=4 and bias condition of VDD=1.8V, measured at the temperatures of 25°C, 75°C, and 125°C, respectively.
0.0 0.5 1.0 1.5 2.0 10
-910
-810
-7T o tal L eakag e C u rren t ( A )
Voltage (V)
At 125oC VDD=Vbias=1.8V
Conventional diode string LLCDS, R=20 kohm
LLCDS2, R=20 kohm
Fig. 4.15 The total leakage current of the conventional diode string, LLCDS, and LLCDS2 under 125°C for N=4 and R=10 kohm.
0 1 2 3 4
4.0 4.5 5.0
The conventional diode string LLCDS
LLCDS2
It 2 (A )
Diode Number (N)
Fig. 4.16 The dependence of secondary breakdown current (It2) of the conventional diode string, LLCDS and LLCDS2 on the diode number (N) in series.
3k 10k 50k 100k 300k 500k 1E-9
1E-8 1E-7 1E-6
To ta l Le a k a g e C u rre nt ( A)
Ro (ohm)
At 125oC, VDD=1.8V, N=4
HBT triggered by conventional diode HBT triggered by LLCDS (R= 10 kohm) HBT triggered by LLCDS2 (R= 10 kohm)
Fig. 4.17 The relationship between Ro and total leakage current of the HBT triggered by conventional diode string , HBT triggered by LLCDS, and HBT triggered by LLCDS2 at bias resistance (R) = 10 kohm under diode number of N=4 and bias condition of VDD=1.8V, measured at the temperatures of 125°C.
0 2 4 6 8 10
0 5 10 15
Current (mA/ µ m
2)
Voltage (V)
HBT triggered by
the conventional diode string
1E-8 1E-7 1E-6
Leakage Current (A)
Fig. 4.18 The TLP I-V curve of the HBT triggered by conventional diode string for N=4, VDD=1.8V, and R=Ro=10 kohm.
0 2 4 6 0
5 10 15
Current (mA/ µm
2)
Voltage (V)
HBT triggered by LLCDS
1E-8 1E-7 1E-6 1E-5 1E-4
Leakage Current (A)
Fig. 4.19 The TLP I-V curve of the HBT triggered by LLCDS for N=4, VDD=1.8V, and R=Ro=10 kohm.
0 2 4 6
0 5 10 15 20
Current (mA/ µm
2)
Voltage (V)
HBT triggered by LLCDS2
1E-8 1E-7 1E-6 1E-5 1E-4
Leakage Current (A)
Fig. 4.20 The TLP I-V curve of the HBT triggered by LLCDS2 for N=4, VDD=1.8V, and R=Ro=10 kohm.
TABLE 4.1
Parameters of devices used in the SPICE simulation
β Is (Amp) Dp DE W (nm) η
Parasitic bipolar 20 8.88e-18 0.989 1.22 30.2
HBT bipolar 393.3 5.93e-19 0.485 2 7.6
Diode 1.7e-13 1.04
TABLE 4.2
Parameters of devices measured from the experimental results at 25oC
β Is(Amp) η
Parasitic bipolar 20
HBT bipolar 360
Diode 1.1e-12 1.47
Chapter 5
Summary and Future Works
5.1 SUMMARY
In chapter 2, the characteristics of diodes with different structures in the SiGe BiCMOS process have been investigated. A high ESD robustness can be achieved for the diodes under forward-biased condition. The ESD robustness of SiGe hetrojunction bipolar transistor in the SiGe BiCMOS process has been also characterized. If the emitter width of SiGe HBT is fixed at 0.45 µm, the order of ESD robustness is: LV SiGe HBT = HV SiGe HBT < HS SiGe HBT. However, when the emitter width of SiGe HBT is fixed at 1.5 µm, the order of ESD robustness is: LV SiGe HBT > HS SiGe HBT > HV SiGe HBT. With the proper layout parameters, SiGe HBT can perform double ESD robustness than that of NMOS device in the SiGe BiCMOS process.
In chapter 3, a new design on the diode string in 0.18-µm SiGe BiCMOS process has been proposed and verified. From the experimental results, the total blocking voltage of the diode string can be effectively increased by an extra bias to the deep N-well through a bias resistance. Although the additional extra bias will cause some current into the diode string, a bias resistance can minimize the overall leakage current of the diode string. Optimization design on the bias resistance and circuit implementation are studied and verified in detail in chapter 4.
In chapter 4, although the additional extra bias may cause leakage current into
LLCDS, the overall leakage current of LLCDS can be minimized by a bias resistance and the total leakage current can be effectively reduced as compared to that of the conventional diode string. This new proposed diode string is very suitable for applying in the power-rail ESD clamp circuit and the ESD connection cell between the separated power lines.
5.2 FUTURE WORKS
In this thesis, the diode strings as the power-rail ESD clamp circuit are developed in SiGe process with low leakage current and high ESD robustness. Because the value of resistance affects the work region of the parasitic BJT, using different values of resistance to optimize the leakage current can be studied in the future. The ESD protection circuit should not interfere with the internal circuits during normal circuit operating condition, while it can provide effective ESD protection to the internal circuit under ESD stress condition.
REFERENCES
[1] S. Voldman, N. Schmidt, R. Johnson, L. Lanzerotti, A. Joseph, C. Brennan, J.
Dunn, D. Harame, P. Juliano, E. Rosenbaum, and B. Meyerson, “Electrostatic discharge characterization of epitaxial base silicon germanium heterojunction bipolar transistors,” in Proc. of EOS/ESD Symp., 2000, pp. 239-251.
[2] S. Voldman, A. Botula, D. T. Hui, and P. A. Juliano, “Silicon germanium heterojunction bipolar transistor ESD power clamps and the Johnson limit,” in Proc. of EOS/ESD Symp., 2001, pp. 326-336.
[3] S. Voldman, “Variable-trigger voltage ESD power clamps for mixed voltage applications using a 120 GHz/100 GHz (ft/fMAX) silicon germanium heterojunction bipolar transistor with carbon incorporation,” in Proc. of EOS/ESD Symp., 2002, pp. 52-61.
[4] V. Vashchenko and P. hopper, “Simulation of Si-Ge BiCMOS ESD structures operation including spatial current instability mode,” in Proc. of IEEE Int. Conf.
on Microelectronics, vol. 2, 2002, pp. 745-748.
[5] V. D. Heyn, N. M Iyer, G. Groeseneken, K. Reynders, and P. Moens, “Effect of the n+ sinker in self-triggereing bipolar ESD protection structures,” in Proc. of EOS/ESD Symp., 2002, pp. 274-280.
[6] M.-D. Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao, “ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,” in Digest of IEEE RFIC Symp., 2002, pp. 427-430.
[7] M.-D. Ker and C.-M. Lee, “Interference of ESD protection diodes on RF performance in giga-Hz RF circuits,” in Proc. of IEEE Int. Symp. on Circuits and Systems, vol. 1, 2003, pp. 297-300.
[8] T.J. Maloney and N.Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in Proc. of EOS/ESD Symp., 1985, pp. 49-54.
[9] J. Barth, J. Richner, K. Verhaege, and L. G. Henry, “TLP calibration, correlation, standards, and new techniques,” in Proc. of EOS/ESD Symp. , 2000, pp. 85-96.
[10] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuit for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, vol. 46, pp. 173-183, 1999.
[11] M.-D. Ker, C.-Y. Wu, T. Cheng, and H.-H. Chang, “Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC,” IEEE Trans.
on VLSI Systems, vol. 4, no. 3, pp. 307-321, 1996.
[12] M.-D. Ker, T.-Y. Chen, and C.-Y. Wu, “ESD protection design in a 0.18-µm salicide CMOS technology by using substrate-triggered technique,” in Proc. of IEEE Int. Symp. on Circuits and Systems, vol. 4, 2001, pp. 754-757.
[13] S. Dabral, R. Aslett, and T. Maloney, “Designing on-chip power supply coupling diodes for ESD protection and noise immunity,” in Proc. of EOS/ESD Symp., 1993, pp. 239-249.
[14] T. Maloney and S. Dabral, “Novel clamp circuits for IC power supply protection,” in Proc. of EOS/ESD Symp., 1995, pp. 1-12.
[15] T. Maloney, “Electrostatic discharge protection circuits using biased and terminated PNP transistor chains,” U.S. patent 5,530,612, June 1996.
[16] S. Voldman and G. Gerosa, “Mixed-voltage interface ESD protection circuits for advanced microprocessors in shallow trench and LOCOS isolation CMOS technologies,” in IEDM Tech. Dig., 1994, pp. 277-280.
[17] M.-D. Ker and W.-Y. Lo, “Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in 0.35-µm silicided CMOS process,” IEEE J. of Solid-State Circuits, vol. 35, pp. 601-611, April 2000.
[18] S.-S. Chen, T.-Y. Chen, T.-H. Tang, J.-L. Su, T.-M. Shen, and J.-K. Chen,
“Low-leakage diode string designs using triple-well technologies for RF-ESD applications,” IEEE Electron Device Letters, vol. 24, pp. 595-597, Sept. 2003.
[19] S.-S. Chen, T.-Y. Chen, T.-H. Tang, J.-K. Chen, and C.-H. Chou,
“Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-µm SiGe BiCMOS process,” IEEE Trans. Electron Devices, vol. 50, pp.
1683-1689, July 2003.
[20] M.-D. Ker, T.-Y. Chen, and C.-Y. Chang, “ESD protection for CMOS RF integrated circuits,” in Proc. of EOS/ESD Symp., 2001, pp.346-354.
[21] S. Voldman and E. Gebreselasie, “Low-Voltage Diode-Configured SiGe:C HBT Triggered ESD Power Clamps Using a Raised Extrinsic Base 200/285 GHz (fT/fMAX) SiGe:C HBT Device ESD protection for CMOS RF integrated circuits,＂ in Proc. of EOS/ESD Symp., 2004, pp.57-66.
簡歷
VITA
姓 名：吳偉琳
學 歷：
新竹市實驗高級中學 (85 年 9 月~87 年 6 月)
國立交通大學電子物理學系 (88 年 9 月~92 年 6 月)
國立交通大學電子研究所碩士班 (92 年 9 月~94 年 4 月)
PUBLICATION LIST
[1] Ming-Dou Ker, Woei-Lin Wu, and Chyh-Yih Chang, “Characterization on ESD devices with test structures in Silicon Germanium BiCMOS process,”
International Conference on Microelectronic Test Structures (ICMTS), 2003, pp.
7-12.
[2] Woei-Lin Wu, Chyh-Yih Chang, and Ming-Dou Ker, “High-Current characteristics of ESD devices in 0.35-mm Silicon Germanium RF BiCMOS process,” in Proc. of Taiwan ESD conference, 2003, pp.157-162.
[3] Woei-Lin Wu and Ming-Dou Ker, “Design on Diode String to Minimize Leakage Current for ESD Protection in 0.18-µm BiCMOS SiGe Process,” in Proc. of Taiwan ESD conference, 2004, pp.72-76.
[4] Ming-Dou Ker and Woei-Lin Wu, “ESD Protection Design with the Low-Leakage-Current Diode String for RF Circuits in BiCMOS SiGe Process,”
accepted by EOS/ESD Symp., 2005.