The Origin of Phase Noise

In the section 2.1.1, we analyze noise source from the circuit and we describe effects of noise now.It is possible to analyze phase noise either in the time domain or in the frequency domain. Both analyses are equivalent due to the duality between the time and frequency domains. For ring oscillators, people would like to use a time domain analysis.

Hence, the notion of phase noise is translated into “jitter”. The jitter can be expressed as the time difference between the zero crossing of the real oscillator and an ideal oscillator oscillating at the same average frequency. It is common to represent the jitter in a histogram. The specification that people usually report under the name of jitter is in fact the variance of the jitter since the jitter itself is different for each cycle. Indeed, for ring oscillators, the frequency of oscillation is not as obvious as for LC-tank oscillators.

Besides, people like to refer to ring oscillators as delay cells, which implies a time constant rather than a frequency.

Figure1.6.1Conversion of noise around integer multiples of the oscillation frequency into phase noise

However, for LC-tank oscillators, since an oscillator is a periodically time varying system. The time-varying nature of the VCO converts the noise around integer multiples of the oscillating frequency into phase noise, which is illustrated in Figure 1.5.1. The major noise sources are noise generated in transistors in the G^M cell shown in Figure 1.3.2 and the thermal noise by various resistances in circuit. A detail analysis on the effect of various noise sources is shown in my reference. The noise generated by a transistor is shown in Equation 1.16. Due to the hot carrier effect, the value of a in Equation 1.16 can be as high as three in short channel devices, while a is around 2/3 for long channel devices. g^d0 is the channel conductance and is defined as the reciprocal of the resistance at the drain node when V^ds=0. g^d0 is a function of W, L, and V^gs.

f K

KT f

g I

i

^B

a

noise

=

d

+ Δ

0

2

4 γ

1.16

To improve the phase noise, we should increase the ratio of the carrier power to the noise power. One way to do it is to increase the size of the transistors and reduce the biasing current. Keeping g^d0 constant, the thermal noise generated by the transistors is

kept at a constant level, but the 1/f noise reduces due to the increase in the total gate area. However, increasing the gate dimension, the gate capacitance contributes a larger portion of the total capacitance required for oscillation, and hence reducing the tuning range.

Another noise source is the thermal noise of the series resistance of the inductors. The noise generated by the resistor is

v

^noise2

^{= 4} KTR

1.17 To minimize the noise power generated by the series resistance, the quality factor of the

inductor should be maximized.

Figure 1.6.2 Illustration of phase noise specification.

Chapter 2

Design and Implementation LC-Tank VCO’s

2.1

Design issues in CMOSs differential lc oscillator

An analysis of phase noise in differential crosscoupled inductance–capacitance (LC) oscillators is presented. The effect of tail current and tank power dissipation on the voltage amplitude is shown. In this section, I will consider about the effect of tail current and tank power dissipation. Various noise sources in the complementary cross-coupled pair are identified, and their effect on phase noise is analyzed. The predictions are in good agreement with measure- ments over a large range of tail currents and supply voltages.

Due to their relatively good phase noise, ease of implementation, and differential operation, cross-coupled inductance–capacitance (LC) oscillators play an important role in high-frequency circuit design. In this paper, the time-variant phase-noise model of my reference will be applied to analyze these oscillators. A simple expression for the tank amplitude is first obtained. The effect of different noise sources in such oscillators is then investigated, and methods for exploiting the cyclostationary properties of noise are shown.

New design implications arising from this approach and experimental results are given.

The dependence of tank amplitude on the tail current and supply voltage is calculated in Section I. The effect of noise sources in both active and resistive tank loss is analyzed in Section. Section C is to investigate the effect of tail-current noise.

I. TANK MPLITUDE

The model of LC-resonant oscillators is shown in fig2.1.1. The oscillation frequency is decided by the equivalent inductance L_eq and capacitance C_eq in the tank. For the purpose of frequency tuning, it is common to use varactors and to vary C_eq in LC-resonant oscillators. The tuning range has to be very wide to meet the UWB system specification. Unfortunately the noise on the control voltage translates into phase noise and wider tuning range makes this problem more serious. Moreover, the size of the varactors has to be increased and the nonlinearity of larger varactors converts more amplitude noise into phase noise.

Fig. 0.1.1 Model of the ideal LC-resonant oscillator

This VCO adopts a complementary cross-coupled negative-gm configuration which has several benefits: (1) only one inductor is needed and large chip area is saved. (2) Smaller voltage drop across the MOS transistors reduces the effect of velocity saturation in the short channel regime. (3) The complementary structure offers higher trans-conductance for a given current, which results in fast switching of the cross-coupled pair. (4) The output swing is more symmetry to alleviate the noise up-conversion effect and then phase noise performance is improved. In addition, the current source is in parallel with a capacitor which provides a path to remove the noise disturbance from the current source. For symmetry the capacitor is actually placed at both sides of the current source.

Tank voltage amplitude has an important effect on the phase noise, as emphasized by the presence of q in the denominator of the expression for the single-sideband phase noise

( )

is the power spectral density of the parallel current noise, is the rms value of the impulse sensitivity function (ISF) associated with that noise source q(max) is the maximum signal charge swing, and Δ is the offset frequency from the carrier. ω

A simple expression for the tank amplitude can be obtained assuming that the current in the differential stage switches quickly from one side to another. Fig. 2.1.1(a) shows the current flowing in the complementary cross-coupled differential LC oscillator when it is completely switched to one side. The differential pair thus can be modeled as a current source switching between

I

^{TAIL and}

− I

^TAIL in parallel with a resistance–inductance–capacitance (RLC) tank, as shown in Fig. 2.1.1(b). is the equivalent parallel resistance of the tank.

Fig. 2.1.1 (a) Current flow when the stage is switched to one side.

(b) Differential equivalent circuit.

At the frequency of resonance, the admittances of the L and C cancel, leaving Req Harmonics of the input current are strongly attenuated by the LC tank, leaving the fundamental of the input current to induce a differential voltage swing of amplitude

R I

^{tail eq}

4π across the tank if one assumes a rectangular current waveform. At high frequencies, the current waveform may be approximated more closely by a sinusoid due to finite switching time and limited gain. In such cases, the tank amplitude can be better approximated as

V

^tank

^≈ I

^tail

R

^eq 2.2

This mode of operation is referred to as the current-limited regime of operation since, in this regime; the tank amplitude is solely determined by the tail-current source and the tank equivalent resistance. Fig. 2.1.1 shows the simulated node voltages as well as the drain currents of the NMOS transistors, M1 and M2 in this regime of operation. The values of L and are such that the circuit oscillates at 10GHz.

Fig. 2.1.2 Simulated voltages and currents in the current-limited regime

Fig.2.1.3 Simulated voltages and currents in the voltage-limited regime

Note that (2) loses its validity as the amplitude approaches the supply voltage because both NMOS and PMOS pairs will enter the triode region at the peaks of the voltage. Also

the tail NMOS transistor may spend most (or even all) of its time in the linear region. This behavior can be seen in the simulated voltages and currents shown in Fig.2.1.3 The tank voltage will be clipped at Vdd by the PMOS transistors and at ground by the NMOS transistors. Therefore, for the oscillator of Fig.2.1.1 (a), the tank voltage amplitude does not significantly exceed vdd Note that since the tail transistor is in the triode region, the tail current does not stay constant. Thus, the drain-source voltage of the differential NMOS transistors can drop significantly, resulting In a large drop in their drain current, as shown in Fig. 2.1.3. This region of operation is known as the voltage-limited regime.

Fig.2.1.4 shows the simulated tank voltage amplitude as a function of tail current for three different values of vdd. As can be seen, the tank amplitude is proportional to the tail current in the current-limited region, while it is limited by Vdd in the voltage-limited regime.

Fig. 2.1.4 Simulated tank voltage amplitude versus tail-current source for the complementary differential oscillator.

II. NOISE SOURCES FROM CMOS

Fig. 2.1.5 depicts the noise sources in the oscillator. The noise power densities for these sources are required to calculate the phase noise using (1). In general, these noise sources are cyclostationary because of the periodic changes in currents and voltages of the active devices. In this section, we first introduce a simplified stationary model for the noise sources and then examine subtleties arising from their cyclostationary behavior. It is very useful to analyze phase noise of the circuits in the section 2.2, 2.3 and 2.4.

Fig. 2.1.5 Complementary LC oscillator with noise sources

Fig. 2.1.6 (a) Simplified model for transistor noise sources.

(b) Differential equivalent circuit.

In a simplified stationary approach, the power densities of the noise sources can be evaluated at the most sensitive time (i.e., the zero crossing of the differential tank voltage) to estimate the effect of these sources [7]. Fig. 2.1.6(a) shows a simplified model of the sources in this balanced case. Converting the current sources to their Thevenin equivalent and writing Kirchoff’s voltage law, one obtains the equivalent differential circuit shown in Fig. 2.1.6(b). Note that the equivalent parallel resistance is canceled by the negative resistance provided by the positive feedback. Therefore, the total differential noise power due to the four cross-coupled transistors is

⎟⎠

Where μ is the mobility of the carriers in the channel, Cox is the oxide capacitance per unit area, W and L are the width and length of the MOS transistor, respectively,

V

^GS is the gate- source voltage, and

V

^{T is the}

threshold voltage. Equation (4) is valid for both short- and long-channel regimes of operation. However, is around 2/3 for long-channel transistors while it may be between two and three in the short-channel region due to hot-electron effects?

In addition to these sources, the contribution of the effective series resistance of the inductor

r

^s caused by ohmic losses in the metal and substrate is given by

To gain further insight into the effect of the tail noise source, its ISF, as well as those for the NMOS and PMOS drain noise sources, are shown in Fig. 2.1.8. The ISF’s are calculated using direct impulse injection and measuring the resultant phase shift.

As can be seen from Fig. 2.1.8, the ISF associated with the tail-current source has a fundamental frequency that is double the oscillation frequency. This is expected since the tail nodeis pulled up every time each one of the differential NMOS transistors turns on, and thus the tail node moves at twice the frequency of the differential voltage.

Fig.2.1.8. The simulated ISF’s of different noise sources in the 1.8-GHz complementary differential oscillator.

Due to this frequency doubling, the Fourier component of the ISF at

ω

^odenoted by C1 is zero, and therefore the noise of the tail-current source in the vicinity of

ω

^ohas

no effect on the differential noise current. However, even-order coefficients such as

c

^0,

c

^{2, and}

c

⁴are significant; therefore, noise components around even harmonics of

ω

^o have a significant effect on the phase noise, as shown in Fig.2.1.9. Also, the low-frequency noise component of the tail noise source can affect phase noise through asymmetry. To verify this behavior, a sinusoidal current with amplitude of 200μA was injected in parallel with the tail-current source, and the induced sideband power below the carrier was measured using fast Fourier transform (FFT) analysis in HSPICE. In Fig. 2.1.10, sinusoidal injection at low frequency

f

_mand in the vicinity of twice the oscillation frequency

2 f

₀⁺

f

_mresults in noticeable sidebands. However, sinusoidal injection of the same amplitude at

f

₀⁺

f

_m does not produce any observable sidebands.

Fig.2.1.9.Evolution of tail noise current

The tail capacitor mentioned in the previous section attenuates the high-frequency noise components of the tail-current source, so one expects corresponding attenuation of phase noise due to this noise. In fact, the induced sidebands due to injection at

f f ⁺ _m

2 ₀ in the presence of the 10-pF tail capacitor are very small and are below the numerical noise floor of the FFT operation.

Since upconversion of 1/f noise is thus the most significant remaining noise component of noisy tail current, one must properly size the tail-current transistor and satisfy the single-ended symmetry criterion by sizing the cross-coupled NMOS and PMOS transistors properly.

How to obtain quadrature signals

There are several ways to obtain quadrature signals: divider-by-2 circuit, RC poly-phase filters, and two interleaved voltage-controlled oscillators. The divider-by-2 circuit needs an oscillator operating at 2 times higher than the desired frequency and a high-speed frequency divider. Both circuits dissipate a lot of power in spite of a smaller chip size. RC poly-phase filters attenuate the signal and increase the effective capacitance of the tank. Also a lot of chip area is needed for a good matching of the filters. For the low power consumption and quadrature phase accuracy, two interleaved voltage-controlled oscillators are adopted in this circuit. According to the Barkhausen criterion, oscillation occurs only when the loop gain [A(jω)]⁴ is unity.

Therefore A(jω) has amplitude of one with a 90 degree phase shift and quadrature signals are obtained at the four outputs of these two VCOs.

Fig. 0.1.11 Two interleaved VCO configuration

As shown in Fig. 0.1.12 (a), the VCO is in a complementary cross-coupled negative-gm configuration. The advantages of this configuration are mentioned in Chapter 2. However, there is a difference from the VCO in Chapter 2. The tail current source is removed to maximize the output swing. Two benefits also achieved thanks to the removal of the current source. First the current source is the main contributor to the phase noise. Second, when all transistors in the VCO core are put in GHz-switching bias condition, flicker noise will apparently be reduced by about 10 dB. The dimension of four cross-coupling PMOS transistors is an important parameter. If cross-coupling is made weak, two-tones oscillation exists probably; if it is made strong, DC power is wasted and more capacitance is added into the LC-tank. By means of transient simulations, the optimal width of the cross-coupling

transistors should be set to one-third of the width of the core transistors while the length of all transistors is chosen as the minimal length (0.18 μm in this circuit)

2.2

Design circuit for tail current of the oscillator

A 10-GHz CMOS conventional quadrature voltage controlled oscillator (QVCO) is described by fig.2.1.2 Two differential pairs (one for negative gm generation and the other one for the coupling input) of each resonator have separate biasing transistors which are switched on and off by the coupling input of each resonator. The simulation of proposed VCO in fig2.2.2 implemented in a 0.18-μm CMOS technology shows 5-dB phase noise improvement from a conventional QVCO with constant tail current sources while the two QVCOs consume the same power of 3.88 mW in the simulation.

With quadrature voltage controlled oscillator (QVCO) where two LC-tank VCOs coupled with each other as shown in Fig. 2.2.1, accurate quadrature-phase local oscillator (LO) signals can be obtained. The conventional QVCO in Fig.2.2.1, however, usually shows poorer phase noise performance than a single-phase VCO.

This is because the phase shift of the resonator of the QVCO is not zero at the oscillation condition and thus its quality factor is degraded .

Several approaches have been reported to improve the phase noise performance of QVCO. In [1] and [2], additional phase shift was inserted between the two LC-tanks, allowing each resonator to be optimally driven at zero-degree phase shift. In this way, superior phase noise performance was obtained but the accurate control of the phase shift is complicated and the phase shifter introduces additional power consumption.

As alternative ways, the series coupling and harmonic coupling schemes are developed which requires either a higher supply voltage or an on-chip transformer.

In this section, the phase noise of a QVCO is improved by the newly proposed coupling and biasing scheme in fig2.2.2. In the following, the detailed description of

the proposed low-phase noise QVCO and the simulated results of the 10-GHz QVCO implemented in a 0.18-μm CMOS technology are given

One of the major sources of the phase noise of MOSFET VCO is the noise of biasing transistor. For a single-phase CMOS VCO, it has been shown the phase noise can be greatly reduced if biasing transistor is switched on and off because the trapped electrons causing the noise are released periodically . This switched biasing scheme can be extended to QVCO by the output voltage as shown in Fig. 2.2.2(a). According to the SpectreRF simulation result shown in Fig.2.2.2, the phase noise is improved by 5dB from the conventional QVCO in Fig.2.1.1.

(a)

(b)

(c)

Fig. 2.2.1 (a) conventional quadrature vco with constant bias current (b) The waveform conventional quadrature vco

For the conventional QVCO in Fig. 2.1.1(a), however, the output swing is limited by the common-source node voltage because the minima of the output are not aligned with the minima of the common-source node voltage as shown in Fig. 2.1.1(b).

This is due to the time delay caused by the resistance of the transistor in the triode region and the parasitic capacitance at the common source node.

（a）

(b)

(c)

Fig.2.2.2. (a) QVCO with the biasing transistors switched by its own output (b) The simulated waveform of QVCO

(C) The phase noise of QVCO

In this work, the special circuit shown as fig2.2.2(a) in stead of providing a fixed tail current, two tail transistors separated , which are controlled by the differential output voltage, are employed. Since the tail transistors are turn off alternatively by the differential output of the VCO during each oscillating period, the probability of trapping carriers by the dangling bonds in the conducted channels is significantly reduced. For the 10-GHz VCO design, simulation results indicate that a 5-dB phase noise improvement at 1-MHz offset can be achieved by employing the switched-bias technique.

In fact, the mos as tail current source can not seen as the ideal switches, because

In fact, the mos as tail current source can not seen as the ideal switches, because

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