This scction presents a source-injection parallel coupled (SIPC) quadrature voltage-controlled oscillator (QVCO) topology. In the proposed SIPC-QVCO, compare to the conventional parallel-coupled LC-QVCO (P-QVCO), the coupling transistors are configured in a way so that the noise, con- tributed by the coupling transistors at the output, can be avoided. The newly proposed SIPC-QVCO and conventional P-QVCO are fabricated based on 0.18μm CMOS technology. The phase noise of SIPC-QVCO simulated at 10GHz shows more than 10 dB improvements than that of the conventional P-QVCO over the offset frequency range of 1 MHz while dissipating the same amount of power.
THE QUADRATURE LO signal is a key element in many of the direct conversion transceivers whic tend to dominate today’s wireless communication technology. ince the introduction of the parallel-coupled LC-quadrature voltage-controlled oscillator (QVCO) (P-QVCO) topology, which was proposed by Rofougaran [1], it has become one of the most commonly used topology for the quadrature signal generation. Recently, Andreani [2] reported a series-coupled LC-QVCO topology (S-QVCO) that exhibits improvement in phase noise compare to the P-QVCO. However, the S-QVCO has disadvantage in the low supply voltage application, which is one of the major trends in concurrent technologies, due to the stack of the coupling transistors in series with the cross-coupled transistors of the differential VCO. In this letter, a source-in- jection parallel-coupled LC-QVCO (SIPC-QVCO) topology is proposed as a low voltage and low phase noise QVCO.
A.SIPC-QVCO Topology Description
Fig.2.3.1cshows the schematic of the proposed SIPC-QVCO topology.As shown in Fig.2.3.1, the SIPC-QVCO consists of two LC-tuned differential VCOs and four coupling transistors. Note that, contrary to the conventional P-QVCO, the drain nodes of the coupling transistors are connected directly to the supply voltage ( ). In
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Fig.2.3.1 Proposed SIPC-QVCO with CMOS schematic.
B. Mechanism of Quadrature Signal Generation
The schematic of the SIPC-QVCO might seem like a minor modification from the conventional P-QVCO. However, the mechanism for quadrature signal generation is fundamen- tally modified. Fig. 2.3.2(a) and (b) represent the P-QVCO and SIPC-QVCO as a combination of functional block diagrams. As can be seen in Fig.2.3.2(a), the quadrature output signals in P-QVCO are generated by the combination of two differ- ential-VCOs and the cascade of two differential amplifiers (Implemented as coupling transistors) with one of them incross-connection. In Fig.
2(b), the simplified block diagram of the SIPC-QVCO is constructed as an alternating combination of two differential-VCOs and two frequency-doublers. The coupling transistor pairs and are configured as differential voltage buffer.
Fig. 2.3.2 Block diagram of (a) the conventional P-QVCO and (b) SIPC-QVCO
Fig. 2.3.3 Switching and coupling transistors and the LC-tanks for (a) the conventional P-QVCO and (b) the SIPC-QVCO.
C. Phase Noise Analysis
To understand the advantage of the SIPC-QVCO in phase noise, Fig.2.3.3 compares some parts SIPC-QVCO with P-QVCO: the switching and coupling transistors and the
transistors modeled as a voltage source in series with the gate and
i
n2 represents the resulting noise current in the drain. In the case of conventional P-QVCO shown in Fig.2.3.3(a), when the coupling transistor is in saturation, the resulting 1/f noise current
i
n2flows through the inductor L1. Since the inductor impedance at low frequencies is small, the voltage drop across the LC-tank by
i
n2 is insignificant. However, when the coupling transistor turns off, the abrupt change in the noise current leads to a voltage induction across the inductor L1, in proportion to the value of and the time derivative, which could be a significant amount. Therefore, the switching operation of the coupling transistors effectively up-converts the 1/f noise to the frequency of oscillation leading to phase noise degradation. This is the main reason for the degradation of the inferior phase noise performance in P-QVCO compare to that of the core differential-VCO.In comparison, with the SIPC-QVCO, the 1/f noise of the coupling transistor contributes no voltage induction across the LC-tank since the drain of the coupling transistors are directly connected to the supply voltage as shown in Fig.2.3.3 (b).
Note that the separation of the coupling transistors from the LC-tuning circuits helps to obtain wider tuning range as parasitic capacitances of the coupling transistors are separated.
D.SIMULATION RESULT
The proposed SIPC-QVCO and the conventional P-QVCO have been implemented with a 0.18μm CMOS technology. For the fair comparison, both QVCOs adopted same active and passive component sizes and biased to dissipate the same total dc current of 16 mA from 1.5-V supply. Both QVCOs are simulated at the same frequency of 10 GHz by the small adjustments in the control voltage of the varactor.
Fig. 2.3.4 compares the phase noise performance of the two QVCOs. As can be seen in Fig. 4, over the offset frequency ranges of 10KHZ ~ MHz, SIPC-QVCO shows more than 10-dB superior phase noise performance compare to that of the conventional P-QVCO. The simulated output power level of each quadrature signal was -10dBm. Fig.2.3.5 shows the simultadd time domain signal operating at 10 GHz.
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Fig.2.3.4. (a) simulated phase noise performances of the SIPC-QVCO.
(b) Simulated phase noise performances of the P-QVCO
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Fig.2.3.5. (a) Simulated time-domain outputs of SIPC-QVCO.
(b) Simulated time-domain outputs of P-QVCO
I have to be careful for designing size of mos( ). The size of mos() is too small that the two vco can not generate quadrature signal as shown in fig. 2.3.6. However, more large size of the coupling mos causes more power dissipation, because the drain
nodes of the coupling mos are connected directly to the supply voltage (vbias). In order to design low power qvco, I have to reduce the size of coupling mos in the SIPC-QVCO, so in the next section, we try to not use coupling mos to obtain quadrature signal.
Fig.2.3.6. simulated time-domain outputs of too small coupling mos() (sipc-qvco)
2.4 .
SIPC with capacitanceA novel quadrature voltage controlled oscillator (QVCO) using source injection parallel coupling with the capacitances is presented. The QVCO realized with LC-tank is demonstrated in a 0.18um RF CMOS 1P6M process. Using the switch of current source technique efficiently reduces the power dissipation. However, by stacking switching transistors, the architecture cannot perform well in phase noise. Through an improved circuit schematic with source injection parallel coupling, the phase noise of the circuit can be lower than vco in the section 2.2. As a result of reducing four transistors in the circuit, the total power dissipation can be cut down even more by using four capacitances to coupling two vco cores. The simulation shows the phase noise is around -109dBc/Hz at 1MHz offset as shown in fig 2.4.1 and the output frequency tuning range of the fabricated QVCO is 1.8 GHz ranging from 9.15 to 10.95 GHz. The circuit draws only 1.8.mA from a 1.5-V supply. Compared with the recent works, the proposed topologies show a better phase noise performance and can be for low-power applications.
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Fig. 2.4.1 (a) the source injection parallel circuit by capacitance QVCO (b) The phase noise of sipc-qvco with capacitance.
The development of single-chip CMOS solutions for the 10-GHz wireless local area network standard is desirable to enable implementations at low cost. In today’s complex radio architecture, it is often necessary for the local oscillator in a transceiver to produce two tones with a quadrature phase relationship. The voltage-controlled oscillator has been the subject of intense study. Recently, a CMOS VCO can be implemented by using a ring structure or an LC tank. Both of them are beneficial and detrimental. By definition, the ring VCO is known for a wide tuning range but drawback of a high phase noise that it is disqualified for most structures in modern RF transceivers. Accordingly, most investigations are focused on the LC VCO design. Owing to the limited range of the variable capacitance of the varactor, the tuning range of CMOS LC VCOs is very small. Hence, Razavi proposed that the varactor controlled by the DC potentials at both of its input terminals to enable the LC VCO yielding a wide tuning range. In recent years, several techniques exist to generate quadrature . Each method has its own advantages and disadvantages.
Different implementations of quadrature oscillators can be found in the literature:
1) Using four-delay stage ring oscillator to fulfill the quadrature phase.
In this section, we try to use capacitances and mos to induce quadrature phase.
filter.
3) A VCO running at double frequency followed by a digital frequency divider based on flip-flop.
4) Two oscillators are injection locked in quadrature by coupling their second-order harmonic in anti-phase, and using a coupling network that exhibits high odd-mode and low even-mode impedance.
5) Two crossed-coupled VCO forced to run in quadrature by using coupling transistors and capacitance. In additional coupling transistors in parallel with the tank of two differential oscillators are used for quadrature generation (P-QVCO). Alternative solutions are the series-coupled QVCO (S-QVCO) topologies as proposed in fig 1.4.. That exhibits improvements in terms of phase robustness and phase noise compared to the P-QVCO.
With the demand for low cost and high integration of wireless transceiver building blocks, here, we present an alternative method to obtain quadrature oscillator based on the switching current source in the triode region technique to reduce the power dissipation. In this work, the original coupling transistors are modified by using source injection parallel coupling to improve the phase noise. A new QVCO using switch current source technique and source injection parallel coupling is demonstrated here.
Circuit Blocks Description- Figure 2.4.1 shows the proposed QVCO topology. In the section 2.2, the circuit of the tail current source proposed by fig 2.2 can not work as the two ideal switches, because the output voltage signal limited by the circuit is not enough big to turn off mos of current source. This VCO adopts a cross-coupled negative-gm configuration since the structure offers higher trans-conductance for a given current, which results in fast switching of the cross-coupled pair. The cross-coupled VCO and the current source operate as switches and the topology consists of two identical VCO in parallel. Each one is composed of two switching transistors as the current source, varactors Cv and inductors L. In order to analyze this circuit, the following introduction is divided into two parts: (1) the switching current source technique. (2) The source injection parallel coupling.
(1) the switching current source in the triode region of the technique
The main advantage of switching current source in the triode region of the technique is to lower the power dissipation, because the MOS biased by the
designed to control the two side of the varactors since the dc voltage are different between two differential output nodes (I/Q). By way of adding capacitors C for dc block and ac short, the voltage of the netX is different as shown fig 2.4.3. The circuit is equivalent for two identical VCO in ac and two VCO in parallel like . In general, a differential VCO uses a current source to bias oscillators reliably and the phase noise of the VCO is increased. The node Vx (Vy, Vz, Vw ) which are drain of tail current source is operated at the same frequency of the oscillation frequency of the LC tank VCO, the node VX( Vy, Vz, Vw )since the node is pulled up when each one of the differential NMOS turn on. As a result, the small capacitor C is adopted for ac short to inject the high-frequency from another vco core, then the mos work as switches. The noise of current source is reduced. A VCO with a current source in the triode region can operate with a low power supply and work as two ideal switches in the proposed QVCO.
The main issue for recent QVCO approach is to achieve a monolithic integration between low phase noise with a wide frequency tuning range and low power consumption at given operating frequencies. As mentioned above, power consumption can be decreased to a half compared to the conventional QVCO topologies and the phase noise can be decreased by this special way.
Due to stacking switching transistors to provide current like the ideal switches, the architecture performs well in phase noise. Hence, the source injection parallel coupling will improve the phase noise, because the MOS of the current source is affected to work like the two ideal switches by another vco core
(2) The source injection parallel coupling
The use of source injection parallels removes the additional noise contributions compared to the conventional coupling transistor based topology, because there are no coupling MOS to add noise in the circuit. The coupling transistors are removed and the two differential VCOs are coupled through the source injection parallel. The capacitors C are adopted for ac coupling and dc block. Therefore, the source injection parallel coupling can be seen as the coupling transistors in the section 2.3. In the other hand, the conventional coupling transistors dissipate 30% ~ 100% of the power
and the power dissipation can be avoided altogether.
Fig. 2.4.2Quadrature output
Fig. 2.4.3 current waveform of Ic, Id, and Itial