A multi-finger HBT can be viewed several sub-HBTs connected in parallel, with their respective collector, emitter and base leads connected together. The DC equivalent circuit with thermal network of an n-finger HBT can be drawn as Fig. 4.9. It is possible for all identical n fingers to have different bias
M
nM
2M
1V
CCI
C1I
B2I
INBX
I
C2I
CnI
BnI
B1EX1 EX2 EXn
CX
I
CCP
D1T
J1P
D2T
J2P
DnT
JnFigure 4.9: An equivalent circuit including thermal networks of an n-finger HBT with constant current bias.
condition, due to the significance of the coupled electrical-thermal feedback.
Therefore, this will influence the DC and RF characteristics of each finger and the whole multi-finger transistor, in particular for devices under high cur-rent or high power operation. With electrical-thermal iteration been discussed
in section 3.1.4, our approach can explore the collapse phenomenon of the multi-finger HBT under high voltage and current bias. To clearly examine the nonlinearity, we perform the simulation for a three-finger HBT, i.e. n = 3.
Without loss of generality, each finger is theoretically assumed identical. The model parameters of each finger for both the electrical and thermal models are shown in Table 4.2. Besides, the multiplier factor M of each distinct finger is set to be 1.0.
Finger 1, Finger 2 and Finger 3 of this three-finger HBT are represented by M 1, M2 and M3, respectively. ICC and IIN denote the total collector current of the device and DC base input current in Fig. 4.9. The behavior of those two side fingers, Finger 1 and Finger 3, are the same for the identical fin-ger assumption. According to the case of three-finfin-ger transistor, the junction temperature of outside finger, TJ1 and central finger, TJ2 can be derive from equations (2.26) and (2.27) and is shown as follows:
TJ1=TJ3=TN{1−(BB − 1)
TN [PD1·(RT H0+RT C2)+PD2·RT C1]}BB−1−1 , (4.2) and
TJ2 =TN{1 −(BB − 1)
TN [PD1· (2 · RT C1) +PD2· RT H0]}BB−1−1 . (4.3) In above equations, RT H0 = RT 11 = RT 22 = RT 33, RT C1 = RT 12 = RT 21, and , see also Eq. (2.27). The emitter area of each finger is equal to 2.8 × 12 µm2and the substrate thickness is 100 µm. There is the same spacing between Finger 1 and Finger 2, and between Finger 2 and Finger 3, which is 14.4 µm.
Therefore, the theoretical values of RT H0, RT C1and RT C2are 1834.20, 487.04 and 101.43 ◦C/W, respectively [52, 65, 66, 67, 72]. Furthermore, TN is set to be ambient temperature, 300 K and the energy band gap of GaAs at this temperature, Eg(TN), equals 1.424 eV.
VCC (V)
Figure 4.10: The common-emitter I-V characteristics: (a) ICC
versus VCC(b) and IC1and IC2versus VCCof the three-finger HBT with thermal effects being considered.
The simulated common-emitter I-V curves for this three-finger HBT is demonstrated in Fig. 4.10. Each line in Fig. 4.10 (a) represents the total collec-tor current under the bias of a constant input current, IIN. As collector-emitter voltage VCC is less than 4.0 V, the NDR region could also be observed in the low and moderate bias region. When VCC increases even more (> 4.0 V), an abrupt lowering of ICCoccurs. The dots in Fig. 4.10 mark the break points be-tween the collapse (abrupt lowing) and NDR region. These marks collectively form the collapse loci. The collector currents of Finger 1 (IC1) and Finger 2 (IC2) are plotted as black and red lines in Fig. 4.10 (b) to explain the collapse in detail. IC1and IC2with the same IINare denoted by lines with the same styles, and they begin to split when collector-emitter voltage VCCincreases. As VCC
raises, the central finger (Finger 2) becomes slightly warmer than the others, then its base-emitter junction turn-on voltage becomes slightly lower (see also Fig. 4.11 and Fig. 4.12). Consequently, Finger 2 conducts more current for a given fixed base input current. This increased collector current,in turn, in-crease the power dissipation in the junction. From Eq. (4.3), the inin-creased dissipated power raises the junction temperature even further. Collapse oc-curs when the junction temperature at Finger 2, TJ2, becomes much higher than those at the side fingers. So that the feedback action of increased col-lector current with junction temperature quickly leads to a situation that just the central finger conducts the almost entire current of this device. Though IC2 raises, the whole device drains less current for the current degradation of side fingers. Since the transition from near even current conduction to one
finger domination occurs suddenly, an dramatic current gain lowering due to the lowered emitter injection efficiency at high temperatures can be observed.
Conclusively, the fundamental reason of both NDR and collapse is the current gain drop with increasing temperature.
300
Furthermore, the changes of junction temperature is shown in Fig. 4.11 and Fig. 4.12. In the comparison between TJ1 and TJ2, we can observe the concentrated heat at the central finger, which induces the current gain collapse.
300
In NDR region, all fingers shares relatively even amount of current and the junction temperatures increase gradually with VCC. In contrast, as the device power is almost dissipated in Finger 2 and TJ2 surges rapidly in the collapse region, the current gain suddenly plummets.
4.4 Summary of This Chapter
We presented the DC simulation and the comparison between our simulated outcome and HSPICE’s results in this chapter. The contents of this chapters are written as:
• our DC simulation results for an HBT, which is compared with mea-sured data and results of HSPICE solver,
• the simulated results with the consideration of self-heating effect, and
• the DC simulation for an multi-finger HBT with self-heating and ther-mal coupling effects.
The DC results are the initial condition of the time-domain simulation dis-cussed in next chapter. With accurate initial value, our solver can deliver stable and reliable solution for large-signal time-domain circuit problem.
Time Domain Simulation and Frequency Domain Analysis
W
e focus on the time-domain circuit simulation in this work. With the algorithms discussed in Chapter 3, the coupled nonlinear ODEs of the simulated circuits are solved in time-domain without any approxima-tion. Thus, the accuracy of the time-domain analysis with this this method is guaranteed. Based on the efficiency of this method, we significantly re-duce the consumed simulation time for intermodulation distortion analysis, which is a major weakness in the most of time-domain methods. The other improvement is the prevention of error propagation. As the simulated time steps increase, the max norm error become larger for the traditional Newton’s iterative (NI) related methods. With the robustness of MI method, our method91
can keep its accuracy after tremendous time steps. We demonstrate the simu-lated results in time-domain of both our method and HSPICE simulator in this chapter. The HSPICE is a well-known NI-based numerical solver. Compared with HSPICE, our method shows its capability to simulate the intermodula-tion distorintermodula-tion. In addiintermodula-tional, the spectrums after FFT are also be shown in this chapter. These frequency-domain results illustrates the difference between our method and HSPICE simulator more clearly.