Chapter 1: Introduction
1.4 Thesis Outline
SiO2, in the gate capacitance density. This lowers the threshold voltage and improves both the
gate-leakage current and breakdown field, since the thickness of the high dielectric constant layer can be increased. And PVD (Physical Vapor Deposition) process is not higher than 600oC, which is very suitable for TFTs process.
1.4 Thesis Outline
This thesis is organized into the following chapters:
In chapter 1, firstly, a brief overview of poly-Si TFTs technology and its various applications are introduced. Then, we will describe the high-κ material in the development of CMOS, paving the way for applying it in the field of thin film transistor. Finally, we give the motivation for the necessity of high-κ insulated thin film transistors.
In chapter 2, some basis about semiconductor and thin film transistor are briefly introduced. Besides, some critical process related to thin film transisitor are also included in this chapter.
In chapter 3, the preparation of devices in our work is described, including the step of poly-Si TFTs fabrication process, measuring tools we used to evaluate our performance and methods to extract device parameters such as threshold voltage, subthreshold swing, field effect mobility, and ON/OFF current ratio.
In chapter 4, results of this experiment are shown including ON/OFF ratio, typical transfer (ID-VG) and output (ID-VD) characteristics for different Lanthanide content in the high-κ insulator.
At last, the conclusions of our work are given in the chapter 5.
Chapter 2
Basic Device Physics
2.1 Energy band in silicon
In a silicon crystal each atom has four valence electrons to share with its four nearest neighboring atom. The valence electrons are shared in a paired configuration called a covalent bond. The most important result of the application of quantum mechanics to the description of electrons in a solid is that the allowed energy levels of electrons will be grouped into bands (Kittel, 1976). The bands are separated by regions of energy that the electrons in the solid cannot possess: forbidden gaps. The highest energy band that is completely filled by electrons at 0 oK is called the valence band. The next higher energy band, separated by a forbidden gap from the valence band, is called the conduction band, as shown in Fig 2.1. , the energy of the electrons in the conduction band increases upward, while the energy of the holes in the valence band increases downward. The bottom of the conduction band is designated Ec, and the top of the valence band Ev. Their separation, or the bandgap, is Eg = Ec – Ev. For silicon, Eg is 1.12eV at room temperature or 300 oK. The bandgap decreases slightly as the temperature increases, with a temperature increases, with a temperature coefficient of dEg / dT ≒ - 2.73 × 10-4 eV/oK for silicon near 300 oK (Arora, 1993).
2.2 n-type and p-type silcon
Intrinsic silicon at room temperature has an extremely low free-carrier concentration; therefore, its resistivity is very high. In practice, intrinsic silicon hardly exists
at room temperature, since it would require materials with an unobtainably high purity. Most impurities in silicon introduce additional energy levels in the forbidden gap and can be easily ionized to add either electrons to the conduction band or holes to the valence, depending on where the impurity level is (Kittel, 1976). The electrical conductivity of silicon is then dominated by the type and concentration of the impurity atoms, or dopants, and the silicon is called extrinsic.
Silicon is a column-IV element with four valence electrons per atom. There are two types of impurities in silicon that are electrically active: those from column-V such as arsenic or phosphorus, and those from column-III such as boron. As is shown in Fig 2.2, a column-V atom in a silicon lattice tends to have one extra electron loosely bonded after forming covalent bonds with other silicon atoms. In most cases, the thermal energy at room temperature is sufficient to ionize the impurities are called donors; they become positively charged when ionized. Silicon material doped with column-V impurities or donors is called n-type silicon, and its electrical conductivity is dominated by electrons in the conduction band. On the other hand, a column-III impurity atom in a silicon lattice tends to be deficient by one electron when forming covalent bonds with other silicon atoms (Fig 2.2). Such an impurity atom can also be ionized by accepting an electron from the valence band, which leaves a free-moving hole that contributes to electrical conduction. These impurities are called acceptors; they become negatively charged when ionized. Silicon material doped with column-III impurities or acceptors is called p-type silicon, and its electrical conductivity is dominated by holes in the valence band. It should be noted that impurity atoms must be in a substitutional site (as opposed to interstitial) in silicon in order to be electrically active.
In terms of the energy-band diagrams in Fig 2.3 (a) and Fig 2.3 (b), donors add allowed electron states in the band-gap close to the conduction-band edge, while acceptors add allowed states just above the valence-band edge. Donor levels contain positive charge
when ionized (emptied). Acceptor levels contain negative charge when ionized (filled). The ionization energies are denoted by Ec – Ed for donors and Ea – Ev for acceptors, respectively.
Phosphorus and arsenic are commonly used donors, or n-type dopants, with low ionization energies on the order of 2kT, while boron is a commonly used acceptor or p-type dopant with a comparable ionization energy. Arsenic, boron, and phosphorus have the highest solid solubility among all the impurities, which makes them the most important doping species in VLSI technology.
2.3 Energy-band diagram of an MOS system
The metal-oxide-semiconductor (MOS) structure is the basis of CMOS technology.
The Si-SiO2 MOS system has been studied extensively(Nicollian and Brews, 1982) because it is directly related to most planar devices and integrated circuits.
The cross section of an MOS capacitor is shown in Fig 2.4. It consists of a conducting gate electrode (metal or heavily doped polysilicon) on top of a thin layer of silicon dioxide grown on a silicon substrate. The energy-band diagrams of the three components are shown in Fig 2.5 Silicon dioxide is an insulator with a large energy gap in the range of 8-9eV.
It is convenient to relate the band structures of all three materials to a common reference potential, the vacuum level. The vacuum level is defined as the energy level at which the electron is free, i.e., no longer bonded to the lattice. In silicon, the vacuum level is 4.05eV above the conduction band. In other words, an electron at the conduction-band edge
must gain a kinetic energy of 4.05eV (called the electron affinity, χ) in order to break loose from the crystal field of silicon. In silicon dioxide, the vacuum level is 0.95eV above its conduction band, which means that the potential barrier is 4.05eV－0.95eV = 3.1eV between the conduction bands of silicon and silicon dioxide. This figure has important significance when discussing the reliability of Si-SiO2 systems.
In metals, the energy difference between the vacuum level and the Fermi level is called the work function of the metal. Different metals have different work functions.
2.4.1 Flat band and accumulation
When there is no applied voltage between the metal and silicon, their Fermi levels line up. Since the work functions are equal, their vacuum levels line up as well, and the bands in both the silicon and oxide are flat, as shown in Fig 2.6(a). This is called the flat-band condition. There is no charge, no field, and the carrier concentration is at the equilibrium value throughout the silicon. Now consider the case when a negative voltage is applied to the gate of a p-type MOS capacitor, as shown in Fig 2.6(b). This raises the metal Fermi level with respect to the silicon surface in the same direction as the oxide field. Because of the low carrier concentration in silicon (compared with metal), the bands bend upward toward the
oxide interface. The Fermi level stays flat within the silicon, since there is no net flow of conduction current. The potential at the silicon surface is called the surface potential. Due to the band bending, the Fermi level at the surface is much closer to the valence band than is the Fermi level in the bulk silicon. This is referred to as the accumulation condition. One can think of the equal amount of negative charge appears on the metal side of the MOS capacitor, as required for charge neutrality.
2.4.2 Depletion and Inversion
On the other hand, if a positive voltage is applied to the gate of a p-type MOS capacitor, the metal Fermi level moves downward which creates an oxide field in the direction of accelerating a negative charge toward the metal electrode. A similar field is induced in the silicon, which causes the bands to bend downward toward the surface, as shown in Fig 2.6(c).
Since the valence band in the bulk, the hole concentration at the surface is lower than the concentration in the bulk. This is referred to as the depletion condition. One can think of the holes as being repelled away from the surface by the positive gate voltage. The depletion of holes at the surface leaves the region with a net negative charge arising from the unbalanced acceptor ions. An equal amount of positive charge appears on the metal side of the capacitor.
As the positive gate voltage increases, the band bending also increases, resulting in a wider depletion region and more (negative) depletion charge. This goes on until the bands bend downward so much that the intrinsic potential (near the mid-gap) at the surface becomes lower than the Fermi potential, as shown in Fig 2.6(d). When this happens, all the holes are depleted from the surface, and the surface potential is such that it is energetically favorable for electrons to populate the conduction band. Note that this n-type surface is formed not by doping, but instead by inverting the original p-type substrate with an applied electric field.
This condition is called inversion. The negative charge in the silicon consists of both the ionized acceptors and the thermally generated electrons in the conduction band. Again, it is balanced by an equal amount of positive charge on the metal gate. The surface is inverted as soon as Ei = (Ec+Ev) / 2 crosses Ef. This is called weak inversion because the electron concentration remains small until Ei is considerably below Ef. If the gate voltage is increased further, the concentration of electrons at the surface will be equal to, and then exceed, the hole concentration in the substrate. This condition is called strong inversion.
2.5 MOSFET Devices
The metal-oxide-semiconductor field effect transistor is the building block of VLSI circuit in microprocessors and dynamic memories. The basic structure of a MOSFETs is shown in Fig 2.7. It is a four terminal devices with the terminals designated as gate, source,
drain, and body. A n-channel MOSFETs consists of a p-type silicon substrate into which two n+ regions, the source and the drain are formed. The gate electrode is usually made of metal or heavy doped polysilicon and is separated from the substrate by a thin silicon oxide. The surface region under the gate oxide between the source and drain is called channel region and is critical for current conduction in MOSFETs. The basic operation of a MOSFETs device can be easily understood from the MOS capacitor discussed in the previous section. When there is no voltage applied to the gate, there is no current flow between the source and drain. When a sufficiently large positive voltage in applied to the gate, the silicon surface is inverted to n-type, which form a conduction channel between the n+ source and drain. If there is a voltage between them, an electron current will flow from the source to the drain.
2.6 Thin Film Transitor Devices
The main difference between the TFTs and MOSFETs is the channel material. The former is made of amorphous silicon or polycrystalline silicon while the latter is made of single crystalline material. The a-Si or poly-Si exist many crystallites that has any type of orientation that means a break in the crystal form one crystallite to the other. The atoms at the border of a crystallite are also linked to the neighbor crystallite ones. However, these atoms bonds are disoriented rather than a prefect lattice of silicon. This border is called a grain boundary. The break in the lattice at grain boundary creates a break in the periodicity of the potential in the material, and create new energy states in the band gap of silicon, which can govern the electrical behavior of the film and consequently of the devices based on the polycrystalline material. The grain boundaries act as energy barriers that the carriers have to overcome. The smaller the grain are, the more grain boundary the film contains and the lower the conductivity becomes. For better performance, the a-Si of the active region need to be
transform to poly-Si. We call this process “poly-Si recrystallization.
2.7 Poly-Silicon Recrystallization
In order to increase TFTs performance, various techniques have been used for crystallize a-Si. Historically, solid phase crystallization was the first technology to produce poly-Si films for display applications, followed by rapid thermal annealing crystallization process, metal-induce lateral crystallization process, and laser annealing crystallization. These four major methods of recrystallization are describe as follow:
2.7.1 Solid-Phase Crystallization Process Technology
The most direct method of obtaining poly-Si films from initially amorphous precursor-Si films is via SPC (Solid-Phase Crystallization) in a furnace environment.
Amorphous silicon is a thermodynamically metastable phase possessing a driving force for transformation to polycrystalline phase given sufficient energy to overcome the initial energy barrier. Solid-phase crystallization can be accomplished within a wide annealing temperature range that requires a similarly wide range of annealing times. The relationship between annealing upon the microstructural details of the precursor-Si film, different annealing times have been observed at the same annealing temperature. A key factor affecting crystallization is the nucleation rate in the precursor-Si film. The nucleation rate is strongly influenced by the selected deposition method and conditions. The structural order/disorder in the precursor film
affects the ability of the film to form supercritical nuclei when subjected to thermal annealing.
The structural order is, in turn, affected by deposition parameters such as temperature and deposition rate. As the temperature decreases and the deposition rate decreases, films are formed having a higher degree of structural disorder.
Despite the successes of traditional SPC methods in increasing grain size and reducing crystallization temperature, the crystallization time typically required for complete transformation tends to be rather long. The crystallization-time issue is further compounded by the use of PECVD as the deposition method for the precursor-Si film. The selection of this technique, even though suboptimal, has been driven by the prior application of PECVD technology in a-Si TFT fabrication.
2.7.2 Metal-Induce Lateral Crystallization Process Technology
Recently, the metal-induced lateral crystallization (MILC) process has been studied widely for polycrystalline silicon thin film transistor applications. Compared with the conventional solid-phase crystallization process of amorphous silicon, MILC process offers the advantages of lower annealing temperature and better crystallization film. In addition, poly-Si films crystallized by the MILC process can be used as the basis for developing the low cost integrated circuits on glass substrate. At present, nickel and palladium have been used to induce lateral crystallization of a-Si:H film. Experimental annealing temperatures and MILC rates obtained for Ni and Pd, respectively. However, the annealing temperature
( <=500oC) is still too high for poly-Si TFT devices to be fabricated on conventional glass substrate, and the low MILC rate, gold (Au) has been employed to induce lateral crystallization of a-Si:H film owing its lower eutectic temperature (363oC). The crystallization of Au/a-Si:H film is observed starting from annealing treatment at 175oC, which is a much lower crystallized temperature than for Ni and Pd (500oC). After the discovery of Au-MILC where microtwin-free Si grains are obtained, MILC also has been successfully applied to the low-temperature fabrication of high-mobility N-channel TFTs.
2.7.3 Rapid Thermal Annealing Crystallization Process Technology
To obtain the poly-Si crystalline phase, laser crystallization can be used with very good results, but the process is expensive and difficult to control. On the other hand, for similar results, furnace annealing requires lower temperature and is much simple, can be better checked, and is cheaper. So, to achieve desirable material properties for the poly-Si films, RTA has been used in this work, thermal crystallization of amorphous silicon. For the Si films annealed at 750oC or higher, using RTA, the grain average sizes are reduced whereas the electron/hole mobility are increased. This indicates that the poly-Si film electrical properties depend not only on the grain size, but also on the crystalline quality of the grains.
Moreover, it appears that the large amount of crystalline defects remaining in the so-called
“grains” of the films annealed at 600oC (SPC) are partially annihilated when the films are annealed at higher temperatures. With regards to the TFTs electrical characteristics, the work suggests combining SPC and RTA steps to obtain TFTs with improved electrical performance.
2.7.4 Excimer Laser Annealing Crystallization Process Technology
Pulsed excimer laser annealing is also being investigated as an alternative crystallization technique to replace furnace annealing. For fabricating high performance poly-Si TFTs on a glass substrate, excimer laser crystallization method is very promising for the following reasons. First, it is a low-temperature process introduced no serious thermal shrinkage of the glass substrate caused by the effects of the short pulse and large absorption coefficient of silicon in the UV light regime. Secondly, it can crystallize the film selectively by partially irradiating the film surface, so both poly-Si TFTs and amorphous Silicon TFTs can be formed on the same substrate. The laser process heats the thin silicon film to the melting point on a short time scale (tens of nanoseconds) that allows the film to melt and recrystallized without significantly heating the glass substrate. Since this process achieves higher annealing temperatures than a conventional furnace annealing, significantly
higher-quality poly-Si films can be obtained.
2.8 Dielectric Material for Poly-Silicon Applications
Dielectric materials control many essential functions in the fabrication, the operation, and the reliability of gate insulated field effect transistors (FETs), such as MOSFETs and especially for a TFT that fabricated on a glass substrate. Dielectrics of various properties are prepared for different applications, such as diffusion barrier, thermal barrier, and electrical insulator. A good insulator material should satisfy at least two requirement. The first requirement is its electrical insulation property. Ideally, the conductance has to be null. In reality, electrical charges can flow through the insulator under various conditions, which correspond to the leakage current in the device. The other requirement is good dielectric performance under operation condition. The TFT’s threshold voltage, subthreshold slope and field effect mobility depend directly on charges present in the bulk of the gate insulator and at
Dielectric materials control many essential functions in the fabrication, the operation, and the reliability of gate insulated field effect transistors (FETs), such as MOSFETs and especially for a TFT that fabricated on a glass substrate. Dielectrics of various properties are prepared for different applications, such as diffusion barrier, thermal barrier, and electrical insulator. A good insulator material should satisfy at least two requirement. The first requirement is its electrical insulation property. Ideally, the conductance has to be null. In reality, electrical charges can flow through the insulator under various conditions, which correspond to the leakage current in the device. The other requirement is good dielectric performance under operation condition. The TFT’s threshold voltage, subthreshold slope and field effect mobility depend directly on charges present in the bulk of the gate insulator and at