Chapter 2: Basic Device Physics
3.1 Device Fabrication Process
In this study we use a silicon wafer with 500nm wet oxide on it, which is to demonstrate the glass substrate. Fabrication of the TFTs started with the formation of a Poly-Silicon film, by depositing 100nm amorphous Silicon on SiO2/Si wafers (using LPCVD at 550oC ). After a 600 oC and 20 hours annealing in N2 ambient, amorphous silicon was recrystallization to become poly-Si. For device isolation, 500nm oxide was deposited by PECVD and device active region was defined by photolithography and wet etching in BOE for about 5 min. The source and drain regions in the active device region were formed by ion-implantation with phosphorus (35KeV at 5×1015 cm-2) and activated at 600 oC for 12 hours annealing in N2 ambient. The second mask was used to remove the PECVD oxide in the gate region, and again RCA clean was done to assure the high-κ/poly-Si interface. 50nm thick HfLaO was deposited by PVD as the gate dielectric, following by a 500 oC Post deposition annealing (PDA). Then gate was formed by depositing 150nm Al using PVD. Finally, the TFTs devices were completed by gate definition with lift-off process after electrode formation.
The completed devices were under 400 oC sintering for 30 min in N2 ambient to enhance the device performance. The fabricated device has gate length and width of 10 µm and 100 µm, respectively.
3.2 Measurement Tools
In this study, devices were put on the stage of probe station (Fig 3.14) to be measured. Capacitance-voltage(C–V) and current-voltage(I–V) characteristics were obtained using HP4284 (Fig 3.15) and HP4156 (Fig 3.16), respectively. The current – voltage characteristic measurement of thin film transistor devices was performed by HP4156 semiconductor parameter analyzer with source grounded and body floating. The thickness of dielectric is measured by Ellipometer.
3.3 Parameter Extraction
In this section, the methodology we use to extract typical parameters in TFTs such as threshold voltage, subthreshold swing, field-effect mobility µFE, and the on/off current ratio for device characteristics are briefly introduced.
3.3.1 Determination of Threshold Voltage
Threshold voltage (Vth) is an important parameter because it affect the drain current and device drivability drastically. There are several methods to determine the threshold voltage of thin film transistors. Two of most commonly used extraction methods are the
constant drain current method and the maximum transconductance method. The constant drain current method define the voltage at a specific drain current as the threshold voltage.
Typically, the threshold current is specified at (W/L) ×10nA for VDS=0.1V and (W/L) × 100nA for VDS =5V in most papers to extract the threshold voltage of TFTs. , where W and L are channel width and channel length, respectively. However, in this thesis we use maximum transconductance method to get our threshold voltage because it is more accurate.
This techniques is the linear extrapolation method with the drain current measured as a function of gate voltage at a low drain voltage of 50~100mV to ensure operation in the linear region, and the drain current as a function of gate voltage can be reduced to
( )
The drain current is not zero when VGS below threshold voltage and approaches zero asymptotically. Hence the IDS versus VGS curve can be extrapolated to ID=0, and the Vth is determined from the extrapolated intercept of gate voltage Equation (4.1) is strictly only valid for negligible series resistance. Fortunately series resistance is usually negligible at the low drain current when threshold voltage measurements are made. The IDS-VGS curve deviates from a straight line at gate voltage below Vth due to sub-threshold current and above Vth due to series resistance and mobility degradation effects. It is common practice to find the point of maximum slope of the IDS-VGS curve and fit a straight line to extrapolate to ID=0 by means of
finding the point of maximum of transconductance (Gm).
3.3.2 Determination of Field Effect Mobility
The field-effect mobility (µFE) is determined from the transconductance gmat low drain voltage. Usually, the maximum value of transconductance (Gm) are used to represent the device performance. The transfer characteristics of Poly-Silicon TFTs are similar to those of conventional MOSFETs, so that the first order of I-V relation in the bulk Si MOSFETs can be applied to Poly-Silicon TFTs. The drain current in linear region (VDS＜VGS－Vth) can be approximated as the following equation:
( )
⎥⎦⎤where Cox is the gate oxide capacitance per unit area, Vth is the threshold voltage, and W and L are channel width and channel length, respectively. Therefore, the transconductance is given by
Therefore, the field-effect mobility is
(max) →0
3.3.3 Determination of Sub-threshold Slope
Sub-threshold slope (S.S.) is a typical parameter to describe the control ability of gate toward channel, which reflects the turn on/off speed of a device. It is defined as the amount of gate voltage required to increase/decrease drain current by one order of magnitude.
The S.S. should be independent of drain voltage and gate voltage. However, in reality, the S.S.
increases with drain voltage due to channel shortening effect such as charge sharing, avalanche multiplication and punchthrough effect. The sub-threshold slope is also related to gate voltage due to undesirable and inevitable factors such as the serial resistance and interface states. In this thesis, the S.S. is defined as one-third of the gate voltage required to decrease the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.
3.3.4 Determination of ON/OFF Current Ratio
On/Off current ratio is one of the most important parameters of poly-Si TFTs especially in the application of LCD because It affects the bright and dark states of TFTs screens drastically. The leakage current mechanism in poly-Si. TFTs is like that in MOSFETs.
But, in MOSFETs, the channel is composed of single crystalline Si and the leakage current is due to the tunneling of minority carrier from drain region to accumulation layer located in channel region. In poly-Si TFTs, the channel is composed of poly-Si. A large amount of trap state densities in grain structure attribute a lot of defect states in energy band gap to enhance the tunneling effect. Therefore, the leakage current is much larger in poly-Si TFTs than in MOSFETs. When the voltage drops between gate voltage and drain voltage increases, the band gap width decreases and the tunneling effect becomes much more severe. Normally we can find this effect in typical Poly-Silicon TFT’s IDS-VGS characteristics where the magnitude of leakage current will reach a minimum and then increase as the gate voltage decreases/increases for n/p-channel TFTs. There are a lot of ways to specify the on and off-current. In this chapter, take n-channel poly-Si TFTs for examples, the on-current is defined as the drain current when gate voltage at the maximum value and drain voltage is 0.1V. The off-current is specified as the minimum current when drain voltage equals to 0.1V.
V
1. Silicon substrate (RCA Clean)
Fig 3.1 Step1
2. Wet oxide growth ( 500nm )
Fig 3.2 Step2
3. Amorphous Silicon deposition by LPCVD at 550 oC
Fig 3.3 Step3
4. Poly-Silicon recrystallization by annealing in N2 at 600 oC for 20hr in furnace
Fig 3.4 Step4
5. Isolation oxide deposition by PECVD ( 500nm )
Fig 3.5 Step5
6. Source and Drain region define, patterning, etching(MASK-1)
Fig 3.6 Step6
7. Source and Drain implantation with phosphorus(35kev at 5E15 cm-2)
Fig 3.7 Step7
8. Activation in N2 at 600oC for 12hr.
9. Removing Silicon oxide on gate region ( MASK-2)
Fig 3.8 Step8
10. HfLaO deposition by PVD and 500oC PDA
Fig 3.9 Step9
11. Contact hole, patterning, etching (MASK-3)
Fig 3.10 Step10
12. Photoresist deposition
Fig 3.11 Step11
13. Metal region definition ( lift-off, MASK-4 )
Fig 3.12 Step12
14. PVD-Al deposition ( 150nm )
Fig 3.13 Step13
15. Removing PR
Fig 3.13 Step14
Fig 3.14 Probe station
Fig 3.15 Agilent 4284
Fig 3.16 Agilent 4156
Chapter 4
Result & Discussion
4.1 Experimental Data Result & Discussion
The electrical characteristics of fabricated devices were measured by Agilent 4156 Precision Semiconductor Parameter Analyzer and Agilent 4284 LCR meter. The physical thickness of these high-κ films were confirm by Ellipsometer. The first three Figures (Fig 4-1
~ Fig 4-3) show C-V characteristic of Al/HfLaO/Si capacitors with La ratio from 20% ~ 40%.
From the C-V curve, we get the EOT of HfLaO is around 8.5 ~ 9.1 nm, which is the thinnest reported EOT in the application of TFTs so far. Combining the EOT with a physical thickness of 50 nm, the dielectric constant of this PVD HfLaO is about 22, which is a high value to overcome the more severe gate leakage current problem compared to MOSFETs. The normalized C-V curve of Al/HfLaO/Si capacitors different La ratio from 20% ~ 40% were shown in Fig. 4.4. It is obvious that the flatband voltage was more negative with the increase of contained La. The output characteristics (Id-Vd) of the Al/HfLaO TFTs with channel length of 10 µm are shown from Fig. 4.5 to Fig. 4.7 . The large drive current of 800 ~ 1200 µA at 5V is attractive for high-speed display ICs. The threshold voltage of our devices were extracted using the method of tangent line on the Id-Vg curve at the point of maximum transconductance (Fig 4.8 ~ Fig4.10). For each devices of La concentration 20%, 30%, 40% respectively, the
threshold voltage were 1.13V, 1V, 0.835V which is better than the threshold voltage of the device with different dielectric materials which were reported before ( Table 4.1 ). The threshold voltage decreases because that La in the dielectric makes the more negative flatband voltage . Base on the threshold voltage equation:
( )
More negative VFB makes lower threshold voltage. And in Fig 4.11 ~ Fig 4.13, we can see the sub-threshold slope of nearly 500 mV/decade, giving the good electron field-effect mobility of 30.79 cm2/Vs (for La/La+Hf = 40%) for all these devices. The good sub-threshold swing and mobility indicate a low interface trap density. The Ion / Ioff ratio of the Al/HfLaO TFT is about 106, even without performing hydrogen passivation. This good performance is related to the lower threshold voltage and the high gate-capacitance of from C-V measurements, which gives a small equivalent-oxide thickness (EOT) and a high κ value ,
And the high drive current is higher than compared to other reported thin film transistor (Table 1). It is because the Lanthanide in the high-κ layer makes the flat band voltage very lower even using aluminum as the gate electrode which work function is 4.1eV. So the data affirm our conception. Our design also provides an alternative way to create high drive current, along with existing approaches such as excimer-laser crystallization (ELC), metal-induced lateral crystallization and electric field enhanced crystallization. It shows that good uniformity is also obtained due to the furnace crystallization, in contrast with the narrow
process window and poor uniformity in ELC TFTs. The field dependence of the gate current density is showed in Fig 4.14 ~ Fig 4.16 shows a gate dielectric breakdown electric field can up to 7 MV/cm. This is high enough to drive a liquid crystal display. This high breakdown field is comparable with or better than that for PECVD TEOS oxide. This is important for achieving good dielectric reliability. It may arise from the robust quality of HfLaO film and the plasma-free process used, which does not damage the gate dielectric. Hence integrating high-κ gate dielectrics HfLaO into TFT-NMOS should not degrade the TFT device reliability, often dominated by the grain-boundary related hot-carrier degradation. The important device parameters are summarized in Table 1. The better device performance of the Al/HfLaO TFTs that compared with other structure is due to the lower threshold voltage which results from the higher capacitance density combining with the plasma-free process.
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0
0.1 0.2 0.3 0.4 0.5
La/La+Hf= 20%
Capacitance
(
uF/cm2)
Voltage (V)
Al/HfLaO/Si
Fig 4.1 C-V of Al/HfLaO/Si capacitor with La ratio of 20%
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0
0.1 0.2 0.3 0.4 0.5
Al/HfLaO/Si La/La+Hf= 30%
Capacitance
(
uF/cm2)
Voltage (V)
Fig 4.2 C-V of Al/HfLaO/Si capacitor with La ratio of 30%
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0
0.1 0.2 0.3 0.4 0.5
Al/HfLaO/Si La/La+Hf= 40%
Capacitance
(
uF/cm2)
Voltage (V)
Fig 4.3 C-V of Al/HfLaO/Si capacitor with La ratio of 40%
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 0.0
0.2 0.4 0.6 0.8 1.0
La/La+Hf= 20%
La/La+Hf= 30%
La/La+Hf= 40%
Capacitance
(
uF/cm2)
Voltage (V)
Fig 4.4 Normalized C-V of Al/HfLaO/Si capacitor with different La ratio from 20% ~ 40%
0 1 2 3 4 5 6 0.0
0.2 0.4 0.6 0.8 1.0
VG=5 V VG=3 V VG=1 V La/La+Hf= 20%
W/L= 100 um/10 um
Drain Current (mA)
Drain Voltage (V)
Fig 4.5 Id-Vd characterisitic of Al/HfLaO/Si TFT with La ratio of 20%
0 1 2 3 4 5 6 0.0
0.2 0.4 0.6 0.8 1.0 1.2
VG=5 V VG=3 V VG=1 V La/La+Hf= 30%
W/L= 100 um/10 um
Drain Current (mA)
Drain Voltage (V)
Fig 4.6 Id-Vd characterisitic of Al/HfLaO/Si TFT with La ratio of 30%
0 1 2 3 4 5 6 0.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
La/La+Hf= 40%
W/L= 100 um/10 um
Drain Current (mA)
Drain Voltage (V)
VG=5 V VG=3 V VG=1 V
Fig 4.7 Id-Vd characterisitic of Al/HfLaO/Si TFT with La ratio of 40%
0 1 2 3 4 5
Fig 4.8 Id-Vd and transconductacne characterisitic of Al/HfLaO/Si TFT with La ratio of 20%
0 1 2 3 4 5
Fig 4.9 Id-Vd and transconductacne characterisitic of Al/HfLaO/Si TFT with La ratio of 30%
0 1 2 3 4 5
Fig 4.10 Id-Vd and transconductacne characterisitic of Al/HfLaO/Si TFT with La ratio of 40%
-2 -1 0 1 2 3 4 5 10-11
10-10 10-9 10-8 10-7 10-6 10-5
10-4 La/La+Hf= 20%
W/L= 100 um/10 um Vd = 0.1 V
Drain Current (A)
Gate Voltage (V)
Subthreshold Swing ~ 530 mV/dec On/Off ratio ~ 1.2 x 106
Fig 4.11 The low subshreshold slope of Al/HfLaO/Si TFT with La ratio of 20%
-2 -1 0 1 2 3 4 5 10-11
10-10 10-9 10-8 10-7 10-6 10-5
10-4 La/La+Hf= 30%
W/L= 100 um/10 um Vd = 0.1 V
Drain Current (A)
Gate Voltage (V)
Subthreshold Swing ~ 518 mV/dec On/Off ratio ~ 1.01 x 106
Fig 4.12 The low subshreshold slope of Al/HfLaO/Si TFT with La ratio of 30%
-2 -1 0 1 2 3 4 5 10-11
10-10 10-9 10-8 10-7 10-6 10-5
10-4 La/La+Hf= 40%
W/L= 100 um/10 um Vd = 0.1 V
Drain Current (A)
Gate Voltage (V)
Subthreshold Swing = 508 mV/dec On/Off ratio = 1.3 x 106
Fig 4.13 The low subshreshold slope of Al/HfLaO/Si TFT with La ratio of 40%
0 1 2 3 4 5 6 7 8 10-7
10-6 10-5 10-4 10-3 10-2 10-1 100 101
Al/HfLaO/Si La/La+Hf= 20%
Current Density(A/cm2 )
Electrical Field (MV/cm) Breakdown Field ~ 7 MV/cm
Fig 4.14 The breakdown voltage of Al/HfLaO/Si TFT with La ratio of 20%
0 1 2 3 4 5 6 7 8 10-7
10-6 10-5 10-4 10-3 10-2 10-1 100 101
Al/HfLaO/Si La/La+Hf= 30%
Breakdown Field ~ 6.8 MV/cm
Current Density
(
A/cm2)
Electrical Field (MV/cm)
Fig 4.15 The breakdown voltage of Al/HfLaO/Si TFT with La ratio of 30%
0 1 2 3 4 5 6 7 8 10-7
10-6 10-5 10-4 10-3 10-2 10-1 100 101
Al/HfLaO/Si La/La+Hf= 40%
Breakdown Field ~ 6.6 MV/cm
Current Density
(
A/cm2)
Electrical Field (MV/cm)
Fig 4.16 The breakdown voltage of Al/HfLaO/Si TFT with La ratio of 40%
Gate
electrode Aluminum Poly-Si Poly-Si Poly-Si Poly-SiGe
Vth(V) 0.835 5.6 8.14 Not
Chapter 5 Conclusion
A new high-κ dielectric TFT with HfLaO as the gate insulator structure has been
proposed and successfully fabricated. The process is simple and compatible to conventional LTPS process. Our experimental data show that the new new high-κ dielectric TFT has higher
turn-on current, on/off current ratio and excellent current saturation characteristics at high bias, compared to the conventional TFT. That is due to the high-κ value and robust quality of HfLaO film itself and the plasma-free process used, which does not damage the gate dielectric.
The new structure is therefore ideally suitable for implementing high-density and high-performance driver circuits on the glass panel for AM-LCD applications. This is because that our TFT device has lower threshold voltage, low subthreshlod slope, high field effect mobility lower leakage current, good breakdown voltage, higher turn-on current and on/off current ratio.
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