To overcome the ESD design constraints in mixed-voltage I/O interfaces, and high-voltage CMOS process, the novel on-chip ESD protection designs are developed and verified in this thesis.
This thesis contains seven chapters. Chapter 1 presents the basic design concept of ESD protection design for commercial IC products in CMOS technology. Moreover, ESD protection design for mixed-voltage I/O interfaces should be concerned about the gate-oxide reliability issue and leakage current path. ESD protection design for high-voltage CMOS process should be concerned about the quite weak ESD robustness due to the ultra-high operating voltage.
In chapter 2, presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. To improve ESD level of the mixed-voltage I/O circuits, the ESD protection design without increasing the process complexity is strongly requested by the mixed-voltage I/O circuits in consumer IC products. Such ESD protection design in the mixed-voltage I/O circuits still meets the gate-oxide reliability constraints, and needs to prevent the undesired leakage current paths during normal circuit operating condition. Under ESD stress condition, the ESD protection circuit should be quickly triggered on to discharge ESD current.
In chapter 3, presents a new ESD protection design with the low-voltage-triggered PNP (called as LVTPNP) device to protect the I/O interfaces with input voltage levels higher than VDD or lower than VSS. Comparing to the traditional PNP device in CMOS process, the new proposed LVTPNP with a low breakdown voltage, by avalanche breakdown across the P+/N-well or N+/P-sub junctions, provides effective discharging path to protect the mixed-voltage I/O interfaces against ESD stresses. Under normal circuit operation conditions, the LVTPNP device is kept off without causing current leakage between the chips.
Furthermore, layout optimization on the LVTPNP device to increase its ESD robustness per
silicon area has been also studied. The multi-finger layout style is used to improve ESD robustness of the LVTPNP device. Moreover, the input stage of ADSL protected by the LVTPNP device has been practically implemented in a 0.25-μm salicided CMOS process to achieve a better ESD robustness.
In chapter 4, presents a new ESD protection scheme with an ESD_BUS and a high-voltage-tolerant ESD clamp circuit, which is designed to protect the mixed-voltage I/O interfaces against ESD stresses without suffering the gate-oxide reliability issue. The proposed high-voltage-tolerant ESD clamp circuit, which combines the stacked-NMOS of 1.2-V gate oxide with the substrate-triggered technique, is designed to protect the 1.2/2.5 V mixed-voltage I/O interfaces. This high-voltage-tolerant ESD clamp circuit has higher ESD robustness and a faster turn-on speed, which has been successfully verified in a 0.13-μm 1.2-V CMOS process.
In chapter 5, presents a new ESD protection structure with the embedded high-voltage p-type SCR (HVPSCR) into the high-voltage PMOS device to protect the vacuum fluorescent display (VFD) in automotive instrumentation. Only an additional N+ diffusion is added into the HVPMOS to form the HVPSCR for ESD protection. The HVPSCR device structure can greatly improve HBM ESD robustness of the VFD driver IC up to 8kV in the specific 0.5-µm high-voltage CMOS process for automotive electronics applications without suffering latchup issue.
In chapter 6, presents ESD robustness of MOSFETs in a 40-V CMOS process with or without drift implant. In addition, the layout spacing from the drain diffusion to polygate is split to find its dependence on ESD robustness. To improve ESD robustness of HV NMOS in a limit layout area, a specific structure of HV n-type SCR (HVNSCR) can be built in the HV NMOS by replacing part of the drain region with P+ diffusion. ESD robustness of HVNSCR is also verified with or without the N-drift implant under different layout spacings from the drain region to polygate. All test chips have been fabricated in a 0.35-μm 40-V CMOS technology.
Finally, the main results of this thesis are summarized in chapter 7. Some suggestions for the future works are also addressed in this chapter.
(a) (b)
(c) (d)
Fig. 1.1 The four pin-combination modes for ESD test on an IC product: (a) positive-to-VSS (PS-mode), (b) negative-to-VSS (NS-mode), (c) positive-to-VDD (PD-mode), and (d) negative-to-VDD (ND-mode).
Fig. 1.2 Typical on-chip ESD protection circuits in a CMOS IC.
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(b)
Fig. 1.3 Typical circuit diagrams for (a) the traditional CMOS I/O buffer, and (b) the mixed-voltage I/O circuits with the stacked-NMOS and the N-well self-biased PMOS.
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Fig. 1.4 The ESD current paths of (a) the traditional I/O pad with power-rail ESD clamp circuit, and (b) the mixed-voltage I/O pad with power-rail ESD clamp circuit, under the positive-to-VSS (PS-mode) ESD stress. The ESD current paths are indicated by the dashed lines.
Fig. 1.5 The I-V curves in high-current region of single NMOS and stacked-NMOS.
Fig. 1.6 The input signals with voltage levels higher than VDD and lower than VSS in some mixed-voltage I/O interfaces.
CHAPTER 2
OVERVIEW ON ESD PROTECTION DESIGN FOR MIXED-VOLTAGE I/O CIRCUITS
ESD protection design for mixed-voltage I/O interfaces has been one of the key challenges of SOC implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. In this chapter, an overview on the design concept and circuit implementations of ESD protection designs is presented for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.
2.1 Substrate-Triggered Stacked-NMOS Device
The snapback operation of the parasitic n-p-n BJT in the stacked-NMOS structure can be controlled by its substrate potential. The substrate-triggered technique [42] can be used to generate the substrate current (Isub) in ESD protection circuits. With the substrate-triggered current (Itrig), the trigger voltage of the stacked-NMOS device in mixed-voltage I/O circuits can be reduced for more effective ESD protection.
The finger-type layout pattern and the corresponding cross-sectional view of the substrate-triggered stacked-NMOS device are shown in Figs. 2.1(a) and 2.1(b), respectively.
As shown in the layout top view, an additional p+ diffusion is inserted into the center drain region of stacked-NMOS device as the substrate-triggered node. The trigger current is provided by the substrate-triggered circuit. An n-well structure is further diffused under the source region, which is also surrounding the whole device, to form a higher equivalent substrate resistance (Rsub) for improving turn-on efficiency of the parasitic lateral BJT in the stacked-NMOS device. The substrate-triggered circuit should be designed to avoid electrical
overstress on the gate oxide and to prevent the undesired leakage current paths during normal circuit operating condition. During ESD stress condition, the substrate-triggered circuit should generate large enough trigger current to effectively improve the turn-on efficiency of parasitic n-p-n BJT in stacked-NMOS device.
The substrate-triggered circuit I for stacked-NMOS device in the mixed-voltage I/O circuits is shown in Fig. 2.2 [43]. The substrate-triggered circuit I is composed of the diode string, a PMOS Mp1, and an NMOS Mn1, to provide the substrate current for triggering on the parasitic n-p-n BJT in the stacked-NMOS device during ESD stress. Under normal circuit operating condition, the turn-on voltage of the substrate-triggered circuit roughly equals to Vpad ≧ Vstring(I)+|Vtp|+VDD, where Vstring(I) is the total voltage drop across the diodes and Vtp is the threshold voltage of the PMOS. To satisfy the requirement in the 2.5V/3.3V mixed-voltage application, the number of the diodes in the diode string should be adjusted to make the turn-on voltage greater than 3.3V. When a 3.3-V input voltage is applied at I/O pad, Mp1 is kept off, and the local substrate of the stacked NMOS is biased at VSS by the turned-on Mn1. With the diode string to block the 3.3-V input voltage at the I/O pad, the Mp1 with thin gate oxide has no gate-oxide reliability issue under normal circuit operating condition. The Mp1 in conjunction with the diode string is used to reduce the leakage current through the substrate-triggered circuit in normal operating condition. If a lower input leakage is desired, the numbers of the diodes in the diode string should be increased. Under PS-mode ESD stress condition, the gate of the Mp1 has an initial voltage level of ~0V, while the VSS pin is grounded but the VDD pin is floating. The substrate-triggered circuit will provide the trigger current flowing through the diode string and the Mp1 into the p-substrate, when Vpad
≧Vstring(I)+ |Vtp|. The trigger current provided by the substrate-triggered circuit is determined by the diode string and the size of Mp1. Once the parasitic n-p-n BJT in the stacked-NMOS device is triggered on, the ESD current will be discharged from the I/O pad to VSS.
Another substrate-triggered circuit II for stacked-NMOS device in the mixed-voltage I/O circuits is shown in Fig. 2.3 [44]. The substrate-triggered circuit II is composed of the PMOS Mp1, PMOS Mp2, NMOS Mn1, and NMOS Mn2, to provide the substrate current for triggering on the parasitic n-p-n BJT in the stacked-NMOS device during ESD stress. In the 2.5V/3.3V mixed-voltage IC application, the gates of Mp1 and Mp2 are biased at 2.5-V VDD supply through a resistor Rd under normal circuit operating condition. When the input voltage transfers from 0V to 3.3V at the I/O pad, the gate voltage of Mn1 could be increased through the coupling capacitor C. However, the Mn2 and Mp2 can clamp the gate voltage of
Mn1 between VDD-Vtn and VDD+|Vtp|, where Vtn is the threshold voltage of NMOS. Once the gate voltage of Mn1 is over VDD+|Vtp|, the Mp2 will turn on to discharge the over-coupled voltage and to keep the gate voltage within VDD+|Vtp|. Since the upper boundary on the gate voltage of Mn1 is within VDD+|Vtp|, the source voltage of Mp1 is clamping below VDD, which keeps the Mp1 always off under normal circuit operation condition. The Mn2 and Mp2 can further clamp the gate voltage of Mn1 to avoid gate-oxide reliability issue in the substrate-triggered circuit, even if the I/O pad has a high input voltage level. Under PS-mode ESD-stress condition, the gates of Mp1 and Mp2 have an initial voltage level of ~0V, while the VSS pin is grounded but the VDD pin is floating. The positive ESD transient voltage on the I/O pad is coupled through the capacitor C to the gate of Mn1. In this situation, both of the Mn1 and Mp1 are operated in the turned-on state.
Therefore, the substrate-triggered circuit II will conduct some ESD current flowing from I/O pad through Mn1 and Mp1 into the p-substrate. The trigger current provided by the substrate-triggered circuit II is determined by the size of Mn1, Mp1, and the capacitor C.
Once the parasitic n-p-n BJT in the stacked-NMOS device is triggered on, the ESD current can be mainly discharged from the I/O pad to VSS.
Both two substrate-triggered designs can significantly reduce the trigger voltage and ensure effective ESD protection for the mixed-voltage I/O circuits. By using such substrate-triggered designs, the gates of stacked-NMOS in the mixed-voltage I/O circuits can be fully controlled by the pre-driver of I/O circuits without conflict to the ESD protection circuits. The main ESD discharge device is the parasitic n-p-n BJT in the stacked-NMOS device. Therefore, the ESD robustness of mixed-voltage I/O circuits can be effectively improved without occupying extra silicon area to realize the additional stand-alone ESD protection device into the mixed-voltage I/O cells.
2.2 Extra ESD Protection Device Between I/O Pad and VSS
To improve ESD level of the mixed-voltage I/O circuits, the extra ESD device was added between I/O pad and VSS power line [45], [46]. The ESD current at the I/O pad under PS-mode ESD stress is designed to be directly discharged through this additional ESD device to the grounded VSS. The ESD current at the I/O pad under the PD-mode ESD stress can be discharged through this ESD device to VSS power line, and then through the parasitic diode of power-rail ESD clamp circuit to the grounded VDD.
One ESD protection design with the additional substrate-triggered lateral n-p-n BJT device has been used to protect the mixed-voltage I/O circuits in a fully salicided, 0.35-μm, thin-epi CMOS process [45]. The ESD protection design with substrate-triggered circuit and the lateral n-p-n BJT device for the mixed-voltage I/O circuits is re-drawn in Fig. 2.4(a). The substrate-triggered circuit should meet the design constraints for providing effective ESD protection to the mixed-voltage I/O circuits, but without suffering the gate-oxide reliability issue. In this design, the substrate-triggered circuit is mainly composed of the diode string and a PMOS Mp1 to provide the substrate current for triggering on the lateral n-p-n BJT during ESD stress. A positive feedback network is formed with Mp2, Mn1, and R1, which maintains Mp1 in a highly conductive state to provide the substrate current during ESD stress.
Moreover, to improve the turn-on efficiency of lateral n-p-n BJT device in a thin-epi CMOS process with much smaller substrate resistance (Rsub), the device structure of lateral n-p-n BJT is specifically designed in Fig. 2.4(b). The lateral n-p-n BJT device consists of an n+
diffusion (emitter), an n-well (collector), and a p+ diffusion as its base. A dummy gate is formed between the p+ base and n+ emitter regions. The collector n-well encloses a portion of the p+ base region. In this design, the HBM ESD level of the mixed-voltage I/O circuits has been verified greater than 2kV in a fully-salicided thin-epi CMOS process.
Another ESD protection design, by using the additional stacked-NMOS triggered silicon controlled rectifier (SNTSCR), has been reported to protect the mixed-voltage I/O circuits [46]. The ESD protection design with the additional SNTSCR device for protecting the mixed-voltage I/O circuits is shown in Fig. 2.5(a). The device structure of SNTSCR and the corresponding ESD detection circuit are shown in Fig. 2.5(b). The ESD detection circuit, designed by using the gate-coupled technique with consideration of the gate-oxide reliability issue, is used to provide suitable gate bias to trigger on the SNTSCR device under ESD stress condition. On the contrary, this ESD detection circuit must keep the SNTSCR off when the IC is under normal circuit operating condition. During normal circuit operating condition, the Mn3 in Fig. 2.5(b) acts as a resistor to bias the gate voltage (Vg1) of Mn1 at VDD. But, the gate of Mn2 is grounded through the resistor R2 and Mn4. So, all the devices in the ESD protection circuit can meet the electrical-field constraint of gate-oxide reliability under normal circuit operating condition. Under PS-mode ESD stress condition, the Mp1 is turned on but Mn3 is off since the initial voltage level on the floating VDD line is ~0V. The capacitors C1 and C2 are designed to couple ESD transient voltage from the I/O pad to the gates of Mn1 and Mn2, respectively. The coupled voltage should be designed greater than the threshold voltage of NMOS to turn on Mn1 and Mn2 for triggering on the SNTSCR device,
before the devices in the mixed-voltage I/O circuit are damaged by ESD stress. With the gate-coupled circuit technique, the trigger voltage of SNTSCR can be significantly reduced, so the SNTSCR can be quickly triggered on to discharge ESD current. By changing the connection of the ESD protection circuit from the I/O pad to the floating n-well of the pull-up PMOS in the mixed-voltage I/O circuit, the SNTSCR device can have a high enough noise margin to the overshooting glitch on the I/O pad, during the normal circuit operating condition. From the experimental results in a 0.35-μm CMOS process, the HBM ESD level of the mixed-voltage I/O circuits with this ESD protection design has been greatly improved up to 8kV, as compared with that (~2kV) of the original mixed-voltage I/O circuits with only stacked NMOS device.
2.3 Extra ESD Protection Device Between I/O Pad and VDD
To improve ESD level of the mixed-voltage I/O circuits, the extra ESD device was added between I/O pad and VDD power line [47]–[49]. The ESD current at the I/O pad under PS-mode ESD stress is designed to be discharged through this additional ESD device to VDD power line, and then through the power-rail ESD clamp circuit to the grounded VSS. The ESD current at the I/O pad under the PD-mode ESD stress can be directly discharged through this additional ESD device to the grounded VDD.
Because the diode in forward-biased condition can sustain much higher ESD current, the diode string has been used for protecting the mixed-voltage I/O circuits [47], [48], or used to realize the power-rail ESD clamp circuit [50]. The ESD protection design with the diode string connected between the I/O pad and VDD power line for the mixed-voltage I/O circuits is shown in Fig. 2.6. The number of diodes in the diode string is determined by the voltage difference between the maximum input voltage at I/O pad and the VDD supply voltage. To reduce the turn-on resistance from I/O pad to VDD during ESD stress, the area of such diodes has to be scaled up by the number of the diodes in stacked configuration. The major concern of using the diode string for ESD protection in the mixed-voltage I/O circuits is the leakage current. While the mixed-voltage I/O circuit is operating at a high-temperature environment with a high-voltage input signal, the forward-biased leakage current from the I/O pad to VDD through the stacked diodes could trigger on the parasitic vertical p-n-p BJT devices in the diode string. The Darlington bipolar amplification of these parasitic p-n-p BJT devices in the diode string will induce a large leakage current into the substrate. In Fig. 2.6, an additional
snubber diode (SD) was used to reduce the leakage current due to the Darlington bipolar amplification in the diode string [47], [48].
Another ESD protection design, by using the gated p-n-p BJT as the additional ESD device connected between I/O pad and VDD, has been designed to protect the mixed-voltage I/O circuits [49], as that shown in Fig. 2.7. In this ESD protection design, the PMOS Mp1 acting as ESD clamp device should be kept off to avoid the leakage current path during normal circuit operating condition. Under PD-mode ESD stress condition, the parasitic lateral p-n-p BJT in the device structure of Mp1 is turned on to discharge ESD current. In the 3.6V/5V mixed-voltage IC application, when the input voltage at I/O pad is 0V, the n-well voltage and gate voltage of Mp1 is clamped at VDD (3.6V) through the turn-on of Mp2 and Mp4. When the input voltage at I/O pad is 5V, the n-well voltage of Mp1 is maintained at 5-Vd (where Vd is the cut-in voltage of the parasitic drain-to-well diode), and the gate voltage of Mp1 is clamped at 5V through the turn-on of Mp3. Therefore, this design can meet the gate-oxide reliability constraints without leakage current path from I/O pad to VDD during normal circuit operating condition. Under ESD stress condition, the parasitic lateral p-n-p BJT in Mp1 is turned on to discharge ESD current by avalanche breakdown. Such a
Another ESD protection design, by using the gated p-n-p BJT as the additional ESD device connected between I/O pad and VDD, has been designed to protect the mixed-voltage I/O circuits [49], as that shown in Fig. 2.7. In this ESD protection design, the PMOS Mp1 acting as ESD clamp device should be kept off to avoid the leakage current path during normal circuit operating condition. Under PD-mode ESD stress condition, the parasitic lateral p-n-p BJT in the device structure of Mp1 is turned on to discharge ESD current. In the 3.6V/5V mixed-voltage IC application, when the input voltage at I/O pad is 0V, the n-well voltage and gate voltage of Mp1 is clamped at VDD (3.6V) through the turn-on of Mp2 and Mp4. When the input voltage at I/O pad is 5V, the n-well voltage of Mp1 is maintained at 5-Vd (where Vd is the cut-in voltage of the parasitic drain-to-well diode), and the gate voltage of Mp1 is clamped at 5V through the turn-on of Mp3. Therefore, this design can meet the gate-oxide reliability constraints without leakage current path from I/O pad to VDD during normal circuit operating condition. Under ESD stress condition, the parasitic lateral p-n-p BJT in Mp1 is turned on to discharge ESD current by avalanche breakdown. Such a