Summary

A comprehensive overview on the ESD protection designs have been discussed for the mixed-voltage I/O circuits without suffering the gate-oxide reliability issue. To improve ESD level of the mixed-voltage I/O circuits, the ESD protection design without increasing the process complexity is strongly requested by the mixed-voltage I/O circuits in consumer IC products. Such ESD protection design in the mixed-voltage I/O circuits still meets the gate-oxide reliability constraints, and needs to prevent the undesired leakage current paths during normal circuit operating condition. Under ESD stress condition, the ESD protection circuit should be quickly triggered on to discharge ESD current. To design the efficient ESD protection circuit for the mixed-voltage I/O circuits with low parasitic capacitance for high-speed I/O applications and low standby leakage current for low-power applications will continually be an important challenge to SOC implementation in the nanoscale CMOS technology.

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Fig. 2.1 (a) Finger-type layout pattern, and (b) the corresponding cross-sectional view, of the substrate-triggered stacked-NMOS device for mixed-voltage I/O circuits.

Fig. 2.2 Schematic circuit diagram of the substrate-triggered stacked-NMOS device with substrate-triggered circuit I for the mixed-voltage I/O circuits.

Fig. 2.3 Schematic circuit diagram of the substrate-triggered stacked-NMOS device with substrate-triggered circuit II for the mixed-voltage I/O circuits.

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Fig. 2.4 (a) ESD protection design with substrate-triggered lateral n-p-n BJT device to protect the mixed-voltage I/O circuits. (b) Cross-sectional view of the lateral n-p-n BJT device in a thin-epi CMOS process.

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Fig. 2.5 (a) ESD protection circuit with the SNTSCR device to protect the mixed-voltage I/O circuits. (b) Realizations of the SNTSCR device and the ESD detection circuit with the gate-coupling technique to trigger on the SNTSCR device.

Fig. 2.6 ESD protection design with the diode string connected between the I/O pad and VDD power line to protect the mixed-voltage I/O circuits.

Fig. 2.7 ESD protection design with gated p-n-p BJT as the ESD clamp device connected between I/O pad and VDD to protect the mixed-voltage I/O circuits.

Fig. 2.8 The ESD protection network with the additional ESD bus line for the mixed-voltage I/O circuits. One power-rail ESD clamp circuit is connected between VDD power line and VSS power line. A second power-rail ESD clamp circuit is connected between ESD bus line and VSS power line.

Fig. 2.9 High-voltage-tolerant ESD protection design with the forward-biased diode in series with one stacked NMOS for analog ESD protection to reduce the input parasitic capacitance.

CHAPTER 3

ESD PROTECTION DESIGN WITH

LOW-VOLTAGE-TRIGGERED PNP (LVTPNP) DEVICES FOR MIXED-VOLTAGE I/O

INTERFACE

In this chapter, ESD protection design for mixed-voltage I/O interfaces with the low-voltage-triggered PNP (LVTPNP) device in CMOS technology is proposed [57]. The LVTPNP, by inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the PNP device, is designed to protect the mixed-voltage I/O interfaces for signals with voltage levels higher than VDD (over-VDD) and lower than VSS (under-VSS). The LVTPNP devices with different structures have been investigated and compared in CMOS processes.

The experimental results in a 0.35-μm CMOS process have proven that the ESD level of the proposed LVTPNP is higher than that of the traditional PNP device. Furthermore, layout on LVTPNP device for ESD protection in mixed-voltage I/O interfaces is also optimized in this work. The experimental results verified in both 0.35-μm and 0.25-μm CMOS processes have proven that the ESD levels of the LVTPNP drawn in the multi-finger layout style are higher than that drawn in the single finger layout style. Moreover, one of the LVTPNP devices drawn with the multi-finger layout style has been used to successfully protect the input stage of an ADSL IC in a 0.25-μm salicided CMOS process [57].

3.1 ESD Protection with LVTPNP Device

Due to the limitation on placing ESD diode between the input pad and VDD/VSS power lines for the mixed-voltage I/O interface with over-VDD and under-VSS signal levels, a new ESD protection design with LVTPNP device is shown in Fig. 3.1. The LVTPNP device is connected between the input pad and VSS power line, which provides ESD protection for

such mixed-voltage I/O interface. With the help of power-rail ESD clamp circuit [8], the positive-to-VSS (PS-mode), negative-to-VSS (NS-mode), positive-to-VDD (PD-mode), and negative-to-VDD (ND-mode) ESD stresses on the input pin can be discharged through the LVTPNP to VSS or VDD with the cooperation of power-rail ESD clamp circuit.

3.1.1 Device Structures and TLP-Measured I-V Characteristics

The cross-sectional view of the traditional PNP device in N-well/P-substrate CMOS process is shown in Fig. 3.2(a), where the N-well is floating in this structure to avoid the leakage path from the pad to grounded P-substrate. The P+ diffusion (emitter) in the floating N-well is connected to the I/O pad for ESD protection. By inserting N+ or P+ diffusion across the junction between N-well and P-substrate of the traditional PNP device, five new different structures of LVTPNP devices in Figs. 3.2(b) ~ 3.2(f) are proposed and investigated to find the optimized design for ESD protection [57]–[59].

Compared to the breakdown voltage of gate oxide, the junction between P+ diffusion and N-well in the traditional PNP device has a low breakdown voltage since the P+ diffusion region is heavily doped. But, the junction between N-well and P-substrate has high breakdown voltage since both of them are lightly doped. The junction between N-well and P-substrate with high breakdown voltage is disadvantageous to ESD protection. In Fig. 3.2(b), an N+ diffusion is inserted across the junction between the N-well and P-substrate. This structure is similar to the traditional PNP device but with a lower breakdown voltage across the base-collector junction, which is called as the type1 LVTPNP. The inserted N+ diffusion is floated to avoid the leakage current paths from the pad to VSS or VDD for application in the mixed-voltage I/O interfaces. Thus, under the normal circuit operation condition, only one of the P/N or N/P junctions in the LVTPNP device could be forward biased to eliminate current leakage path. The inserted N+ diffusion with n-type heavily doped region to the P-substrate has a lower breakdown voltage, which avalanches earlier than the junction between N-well and P-substrate to discharge ESD current.

In Fig. 3.2(c), the P+ diffusion instead of N+ diffusion is inserted in the PNP structure to become the type2 LVTPNP, where the P+ diffusion across the N-well/P-substrate junction is used to reduce the breakdown voltage across the base-collector junction of the LVTPNP.

Because of the floating base (N-well), the two separated P+ diffusions in Fig. 3.2(c) can be further merged into one single P+ diffusion to form the type3 LVTPNP in Fig. 3.2(d). The heavily doped P+ diffusion across the N-well/P-substrate junction in Fig. 3.2(d) is also used

as the contact region for P-substrate.

In Fig. 3.2(e), compared with the type1 LVTPNP in Fig. 3.2(b), the field-oxide region between N+ diffusion and P+ diffusion in P-substrate is replaced by a floating polygate to become the gated1 LVTPNP. In general CMOS process, the minimum design rule of the polygate is shorter than that of the field oxide isolation. With the dummy polygate, the clearance (marked as L1) between the N+ and P+ diffusions can be realized with the minimum design rule. Moreover, the replacement of field oxide with polygate can change the current path from the bottom of field oxide to the surface of the channel under the polygate.

This will result in a smaller turn-on resistance to quickly discharge ESD current. In Fig. 3.2(f), compared with the gated1 LVTPNP in Fig. 3.2(e), the field oxide between N+ diffusion and P+ diffusion in N-well is replaced by another floating polygate (marked with a gate length of L2) to become the gated2 LVTPNP. The replacement of field oxide with polygate between the base and emitter will obtain a smaller turn-on resistance for ESD protection.

With the same device dimension of 30μm×30μm (the width is defined as 30μm) for all devices, the corresponding TLP-measured I-V curves among those devices under PS-mode and NS-mode ESD-stress conditions are shown in Fig. 3.3(a) and 3.3(b), respectively. The first breakdown voltage (Vt1), the first breakdown current (It1), the second breakdown voltage (Vt2), and the second breakdown current (It2) of these devices are summary at Table 3.1. Under PS-mode ESD-stress condition, the Vt1 of the LVTPNP devices is indeed lower than that of the traditional PNP device. The It2 of LVTPNP devices is indeed higher than that of the traditional PNP device. Under NS-mode ESD-stress condition, the Vt1 of the LVTPNP devices and the traditional PNP device are almost the same because the breakdown region of all the devices occurs at the E-B junction (P+/N-well). The It2 among theses devices are somewhat different, which could be caused from the different current distribution along the devices of different structures during ESD stress. Basically, the device with the more effective device width will present a higher ESD robustness. To further improve ESD level of such LVTPNP devices, the layout to increase effective device width will be studied and optimized in the next section.

3.1.2 Layout Parameters of LVTPNP Devices on HBM ESD Levels

Under 0.35-μm CMOS process without any extra mask layer, the ESD levels among the proposed LVTPNP devices with different layout parameters are compared in Figs. 3.4(a) ~ 3.4(g). The layout parameters include the width or spacing, LE, LC, X, Y, S, L1, and L2, which

have been indicated in Figs. 3.2(a) ~ 3.2(f). For the gated2 LVTPNP device, the L1 and L2 are changed simultaneously in the layout.

In Figs. 3.4(a) and 3.4(b), as the width of the LVTPNP devices increasing, the HBM ESD levels are improved under both positive-to-VSS and negative-to-VSS ESD-stress conditions. This confirms that when the area of effective ESD current flow from emitter to collector is increased, the heat will be dissipated through the larger region. Therefore, the device can sustain a higher ESD level.

In Fig. 3.4(c), as the spacing X of the type1 LVTPNP or the spacing Y of the type2 LVTPNP increasing, the HBM ESD level is improved under the positive-to-VSS ESD-stress condition. Here, the LVTPNP devices with the increase of X or Y will have a wider field oxide region in the device structures, but the N+ or P+ diffusion across the N-well/P-substrate junction is kept to have the same diffusion layout spacing of 1.2 μm. The TLP-measured I-V curves of the type1 LVTPNP with different X spacings and the type2 LVTPNP with different Y spacings are shown in Figs. 3.5(a) and 3.5(b), respectively. As these spacings increase, the clamped voltage across the devices will be increased due to the increased turn-on resistances.

The voltage drop across the base-collector (B-C) junction will increase to cause the emitter-base (E-B) potential barrier to be lowered. The lowering potential barrier at the E-B junction produces a large increase in current with a very small increase in B-C voltage. This effect is the so-called punch-through breakdown phenomenon [60], which will occur before the avalanche breakdown. In Fig. 3.4(d), as the spacing S of the LVTPNP increasing, the HBM ESD level is improved under the negative-to-VSS ESD-stress condition. In this ESD-stress condition, however, the parameters S play the same role as parameters X and Y in positive-to-VSS ESD-stress condition. Because these spacings increase, the voltage drop across the base-emitter (B-E) junction will increase to cause the collector-base (C-B) potential barrier to be lowered. Therefore, the lowering potential barrier at the C-B junction produces a large increase in current but with a very small increase in B-E voltage. From such results, these spacings in LVTPNP devices can be further optimized in layout to improve ESD robustness for applications in such mixed-voltage I/O interfaces.

In Fig. 3.4(e), as the LE of the LVTPNP devices increasing, the HBM ESD level is improved under negative-to-VSS ESD-stress condition. Because the heat will be located around the B-E junction, as the emitter junction area is increased, the heat will be dissipated through the larger region. However, under positive-to-VSS ESD-stress condition, this parameter has no influence to ESD level, because the heat will be located around the B-C

junction with the same area in the test chips.

The parameter LC of the LVTPNP devices almost has no influences to HBM ESD level.

Under both positive-to-VSS and negative-to-VSS ESD-stress conditions, the heat will be located around B-C junction and B-E junction, respectively. However, the heat will not be located around the P+ diffusion in P-substrate.

In Fig. 3.4(f), as L1 of the gated1 LVTPNP (L1 and L2 of the gated2 LVTPNP) increasing, the ESD level is improved under the positive-to-VSS ESD-stress condition. In Fig.

3.4(g), as L1 and L2 of the gated2 LVTPNP increasing, the ESD level is improved under the negative-to-VSS ESD-stress condition. However, in such ESD stress mode, the L1 has no influence to ESD level of both gated1 LVTPNP and gated2 LVTPNP. Such layout parameters L1 (L2) in the gated LVTPNP play the same role as that of the parameters X (S) in the type1 LVTPNP, so as the parameters Y (S) in the type2 LVTPNP. By correctly adjusting the layout parameters, the desired ESD level of the mixed-voltage I/O interface can be achieved by the proposed LVTPNP devices with the optimized layout parameters.

3.1.3 Multi-Finger Layout Style for LVTPNP

The ESD robustness of LVTPNP device with the single finger layout style, which is shown in Fig. 3.6(a) and its cross-sectional view shown in Fig. 3.6(b), can’t meet the ESD specification of 2-kV HBM ESD level in a limited silicon area. Therefore, based on the dependence of ESD levels on the layout parameters (including the width, LE, LC, X, Y, and S) of LVTPNP devices, the ESD level mainly depends on the effective device width from its emitter to its collector in both PS- and NS- mode ESD stresses. On the other hand, LE affects only NS-mode ESD level and LC doesn’t affect the ESD level. However, comparing the PS- and NS-mode ESD levels, the PS-mode ESD level is critical. Considering the parameters of effective device width, LE, and LC, LE and LC are less sensitive to ESD level than the effective device width. Therefore, a more compact realization of the LVTPNP can be implemented by using the minimum spacing of the design rules for LE and LC in each finger layout. The LVTPNP realized by the multi-finger layout style is shown in Fig. 3.7(a), and its cross-sectional view is shown in Fig. 3.7(b), which will have more effective current flow for ESD protection. Here, due to complicated layout structure, the gated1 and gated2 LVTPNP devices are difficult to realize with multi-finger layout style. Hence, only the type 1, 2, and 3 LVTPNP devices were chosen to realize the multi-finger layout style

The LVTPNP devices drawn with the single finger layout style and the new proposed

multi-finger layout style have been fabricated in both 0.35-μm polycided and 0.25-μm salicided CMOS processes without any extra additional mask layer. Under the positive-to-VSS ESD-stress condition, the HBM ESD levels of the LVTPNP devices with the singer finger layout style and the multi-finger layout style are compared in Table 3.2. In almost the same layout area (36µm×32µm v.s. 33.6µm×36.5µm), the LVTPNP devices with the multi-finger layout style have much higher ESD robustness than those with the single finger layout style in both 0.35-μm polycided and 0.25-μm salicided CMOS processes.

Especially, the type3 LVTPNP with multi-finger layout has the highest ESD robustness, which can sustain HBM ESD stress of 3.6kV in the 0.35-μm polycided CMOS process and 1.4kV in the 0.25-μm salicided CMOS process. Furthermore, within unit layout area, the ESD robustness of type3 LVTPNP is increased from 0.5 V/μm² to 2.94V/μm² in the 0.35-μm polycided CMOS process and from 0.68 V/μm² to 1.14 V/μm² in the 0.25-μm salicided CMOS process.

Under the negative-to-VSS ESD-stress condition, the HBM ESD levels of the LVTPNP devices with the single finger layout style and the new multi-finger layout style are compared in Table 3.3. In almost the same layout area, the LVTPNP devices with the multi-finger layout style have much higher ESD robustness than those with the single finger layout style in both 0.35-μm polycided and 0.25-μm salicided CMOS processes. Especially, the type3 LVTPNP with multi-finger layout has the highest ESD robustness, which can sustain HBM ESD stress of a 3.3kV in the 0.35-μm polycided CMOS process and 3.8kV in the 0.25-μm salicided CMOS process. Furthermore, within unit layout area, the ESD robustness of type3 LVTPNP is increased from 0.59 V/μm² to 2.69V/μm² in the 0.35-μm polycided CMOS process and from 1.71 V/μm² to 3.10 V/μm² in the salicided 0.25-μm CMOS process. With suitable selection on the LVTPNP devices and layout style, the overall ESD robustness of the mixed-voltage I/O interfaces can be designed to meet the ESD specification of 2-kV HBM ESD level within a smaller silicon area. Especially, the LVTPNP in the type3 device structure with multi-finger layout style has the excellent ESD performance.

Because the doping concentration in the 0.25-μm salicided CMOS process is higher than that in the 0.35-μm polycided CMOS process, the junctions have slightly lower breakdown voltages in the 0.25-μm CMOS process than that in the 0.35-μm CMOS process.

With the single finger layout style, HBM ESD levels of the LVTPNP devices in the 0.25-μm CMOS process are higher than those of the LVTPNP devices in the 0.35-μm CMOS process under both positive-to-VSS and negative-to-VSS ESD-stress conditions. Moreover, HBM

ESD levels of the LVTPNP devices in the 0.25-μm CMOS process are higher than those of the LVTPNP devices in the 0.35-μm CMOS process under negative-to-VSS ESD-stress condition, when they are drawn with the multi-finger layout style. However, HBM ESD levels of the LVTPNP devices in the 0.25-μm salicided CMOS process are lower than those of the LVTPNP devices in the 0.35-μm polycided CMOS process under positive-to-VSS ESD-stress condition for the multi-finger layout style. The silicided diffusion in the 0.25-μm salicided CMOS process causes degradation on ESD robustness of the LVTPNP device drawn in multi-finger layout style [61]. Under ESD stress condition, the silicide diffusion on the device will cause the current crowded on the surface of the device and the heat will be located in the local area. To further increase ESD level of the LVTPNP device in the 0.25-μm salicided CMOS process, the optional silicide-blocking mask layer can be used to block the silicide formation around the perimeter of emitter region of the LVTPNP device.

Moreover, the TLP-measured I-V curves of LVTPNP devices with the single finger layout style and the multi-finger layout style in 0.25-μm salicided CMOS process under PS-mode and NS-mode stress conditions are compared in Figs. 3.8(a) and 3.8(b), respectively.

Due to the increase of total effective device width and the decrease of the length from its emitter to its collector, the LVTPNP devices with the multi-finger layout style have lower turn-on resistances than those with the single finger layout style in the same layout area.

Hence, the It2 of LVTPNP devices with multi-finger layout style is higher than those with single finger layout style. For single finger layout style, however, because the turn-on resistance of the type3 LVTPNP is lower than those of the type1 and type2 LVTPNP, there will be a factor differences in the improved ESD levels of different types of LVTPNP in multi-finger layout. Hence, correlating with the same increase of effective device fingers will result in different increase factors of It2 of the type1 (type2) LVTPNP and type3 LVTPNP.

3.2 Application in ADSL Interface

3.2.1 ESD Protection Design with the LVTPNP for the Input Stage of ADSL The LVTPNP devices are used in the input ESD protection circuit for the ADSL interface, which has a high-voltage signal level of 5V and a low-voltage signal level of -1V.

3.2.1 ESD Protection Design with the LVTPNP for the Input Stage of ADSL The LVTPNP devices are used in the input ESD protection circuit for the ADSL interface, which has a high-voltage signal level of 5V and a low-voltage signal level of -1V.