To improve circuit operating speed and performance, the device dimension of MOSFET has been shrunk in the advanced CMOS ICs. With the scaled-down device dimension in advanced CMOS technology, the power supply voltage is also scaled down to reduce the power consumption and to meet the gate-oxide reliability. However, most microelectronic systems nowadays consist of mix semiconductor chips fabricated in different CMOS
technologies. Therefore, the microelectronic systems often require the interfaces between semiconductor chips or sub-systems which have different internal power supply voltages.
With the different power supply voltages in a microelectronic system, chip-to-chip I/O interface circuits must be designed to avoid electrical overstress across the gate oxide [9], to avoid hot-carrier degradation [10] on the output devices, and to prevent the undesired leakage current paths between the chips [11], [12]. For example, a chip which operates with internal power supply voltage of 1.2V may have the I/O signals of 2.5V. The traditional CMOS I/O buffer with VDD of 1.2V and 1.2-V gate oxide devices is shown in Fig. 1.3(a) with both input and output stages. When an external 2.5-V signal is applied to the I/O pad, the channel of the pull-up PMOS and the parasitic drain-to-well junction diode in the pull-up PMOS will cause the leakage current paths from I/O pad to VDD, as the dashed lines shown in Fig. 1(a).
Moreover, the 1.2-V gate oxides of the pull-down NMOS and the input inverter will be over-stressed by the 2.5-V input signal to suffer the gate-oxide reliability issue. By using the additional thick gate-oxide process (or called as dual gate-oxide CMOS process [13], [14]), the gate-oxide reliability issue can be avoided. However, the process complexity and fabrication cost are increased.
To solve the gate-oxide reliability issue without using the additional thick gate-oxide process, the stacked-NMOS configuration has been widely used in the mixed-voltage I/O circuits [15]–[21]. The typical 1.2V/2.5V-tolerant mixed-voltage I/O circuit is shown in Fig.
1.3(b). The independent control on the top and bottom gates of stacked-NMOS device allows the devices to meet reliability limitations during normal circuit operation. Therefore, the stacked-NMOS can be operated within the safe range for both dielectric and hot-carrier reliability limitations. The pull-up PMOS, connected from the I/O pad to the VDD power line, has the gate tracking circuits for tracking the gate voltage and the N-well self-biased circuits for tracking N-well voltage, which are designed to ensure that the pull-up PMOS does not conduct current when the 2.5-V input signals enter the I/O pad. In such mixed-voltage I/O circuits, the on-chip ESD protection circuits will meet more design constraints and difficulty.
The ESD protection design of I/O pad cooperating with power-rail ESD clamp circuit is shown in Fig. 1.4(a), where a PS-mode ESD pulse is applied to the I/O pad. The ESD current paths (IESD), including IESD1 and IESD2, along the traditional CMOS output buffer are also illustrated by the dashed lines in Fig. 1.4(a), where most of ESD current (IESD1) is discharged through the parasitic diode of the PMOS and the VDD-to-VSS ESD camp circuit to ground.
Therefore, the traditional CMOS output buffer can sustain a higher ESD stress with cooperation of active power-rail ESD clamp circuit. But, due to the leakage current issue in
the mixed-voltage I/O circuits, there is no diode connected from the I/O pad to VDD power line in the mixed-voltage I/O circuits. Without the diode connected from the I/O pad to VDD in the mixed-voltage I/O circuits, the ESD current at I/O pad under PS-mode ESD stress cannot be discharged from the I/O pad to VDD power line, and cannot be discharged through the additional VDD-to-VSS ESD clamp circuit. Therefore, the power-rail ESD clamp circuit did not help to pull up ESD level of the mixed-voltage I/O pad under the PS-mode ESD stress.
The ESD current path in the mixed-voltage I/O circuits with power-rail ESD clamp circuit under PS-mode ESD stress in illustrated in Fig. 1.4(b). Such ESD current at the I/O pad is mainly discharged through the stacked-NMOS by snapback breakdown. Besides, comparing the single NMOS and the stacked-NMOS in the high-current snapback region, the stacked-NMOS will have a higher trigger voltage (Vt1), a higher snapback holding voltage (Vsb), slower turn-on speed, and a lower secondary breakdown current (It2), as shown in Fig.
1.5. Therefore, such mixed-voltage I/O circuits with stacked-NMOS often have much lower ESD level under the PS-mode ESD stress, as compared to the traditional I/O circuits with a single NMOS [22], [23]. In addition, without the diode connected from the I/O pad to VDD, the mixed-voltage I/O circuit also has a lower ESD level for I/O pad under PD-mode ESD stress. The absence of the diode between I/O pad and VDD power line in the mixed-voltage I/O circuits will seriously degrade ESD performance of the I/O pad under the PS-mode and PD-mode ESD stresses. By using extra process modification such as ESD implantation, the ESD robustness of stacked-NMOS device can be further improved [24], [25], but the process complexity and fabrication cost are increased. In addition, the induced high voltage on the gate of top NMOS transistor under ESD stress will cause high-current crowding effect in the channel region to seriously degrade ESD robustness of stacked-NMOS device in the mixed-voltage I/O circuits [26]. Therefore, effective ESD protection design without increasing process complexity is strongly requested by the mixed-voltage I/O circuits in the scaled-down CMOS processes.
One of the mixed-voltage circuit applications, such as the interface in ADSL which has input signals with voltage levels higher than VDD and lower than VSS, is shown in Fig. 1.6 The traditional on-chip ESD protection circuits are not suitable for such mixed-voltage interfaces. The ESD diode Dp (Dn) will be forward biased when the input signal levels are higher than VDD (lower than VSS). This ESD protection circuit will cause current leakage between the chips of the mixed-voltage I/O interface. Moreover, traditional on-chip ESD protection with NMOS/PMOS will also cause the same leakage issue and suffer the gate-oxide reliability issue when the over-VDD or under-VSS external signals reach to the
input pad. To meet such mixed-voltage I/O interface, the SCR device with floating P-well structure in an N-substrate CMOS process had been used as on-chip ESD protection device [27]. However, the SCR device with a floating well structure is very sensitive to latchup [28], [29]. The mixed-voltage I/O interfaces in the system applications often have serious overshooting or undershooting signal transition, which could trigger on the SCR device in the ESD protection circuit of I/O pad to induce latchup troubles to the chip [27].