Chapter 1 Introduction
1.3 Thesis Organization
In this thesis, one fully integrated integer-N type frequency synthesizer and one wide tuning range voltage-controlled oscillators (VCO) are realized in TSMC RF 1P6M 0.18 μm
CMOS technology.
Chapter 2 will introduce a multi-band voltage-controlled oscillator and its frequency divider. The characteristic of very wide tuning range supports for MB-OFDM UWB system.
Both the simulation and the measurement result are discussed.
Chapter 3 will introduce a fully integrated, fast-locked, and low power integer-N frequency synthesizer for MB-OFDM UWB wireless communication. The architecture will be discussed and compared to other synthesizers for the same application. The simulation of each building block is also presented.
Finally, Chapter 4 will give the summary and conclusions of these circuits. Also the future work will be mentioned.
Chapter 2 Wideband Voltage-Controlled Oscillator
and Its Frequency Divider for MB-OFDM UWB system
In this chapter, a wide tuning range voltage-controlled oscillator (VCO) and a divider-by-2 circuit are combined together to fulfill a local oscillator for the UWB system application. Besides, a 2-to-1 multiplexer is used to select which path the output signal is from. This circuit is implemented in TSMC RF 1P6M 0.18 μm CMOS technology and fabricated in February 2006. In the following sections, three blocks of this circuit will be explained individually. In addition, both the simulation and measurement results will also be discussed.
2.1 Circuit Design Consideration
In MB-OFDM UWB system, carrier frequencies are distributed in a spectrum of 3.1~10.6 GHz and with 528 MHz apart from each other. To meet this specification a voltage-controlled oscillator is necessary to have very wide tuning range. However, it’s difficult for LC-VCO to cover such a wide range. Therefore a 6~9 GHz VCO and its frequency divider are designed to provide carrier frequencies for Band Group #1, #3 and #4 in MB-OFDM UWB system[3]. The Band Group #2 is bypassed because occupied by 802.11a and HiperLAN devices. The architecture is shown in Fig. 2-1.
Fig. 2-1 Architecture of VCO and its divider
2.1.1 Multi-Band Voltage-Controlled Oscillator
The model of LC-resonant oscillators is shown in Fig. 2-2. The oscillation frequency is decided by the equivalent inductance Leq and capacitance Ceq in the tank. For the purpose of frequency tuning, it is common to use varactors which can vary Ceq in LC-resonant oscillators.
The tuning range has to be very wide to meet the UWB system specification. Unfortunately the noise on the control voltage translates into phase noise and wider tuning range makes this problem more serious. Moreover, the size of the varactors has to be increased and the nonlinearity of larger varactors converts more amplitude noise into phase noise. Therefore, the SCA (Switched-Capacitor-Array) is added to avoid using large varactors[6][7]. Another advantage of SCA is that MIM (metal-insulator-metal) capacitors have a higher Q-value (about 1000) than varactors do. Due to this SCA design characteristic, the noise performance is improved. Fig. 2-3 shows the schematic of this multi-band VCO.
Fig. 2-2 Model of the ideal LC-resonant oscillator
Fig. 2-3 Voltage-controlled oscillator and the switched-capacitor-array
This VCO adopts a complementary cross-coupled negative-gm configuration which has several benefits: (1) only one inductor is needed and large chip area is saved (2) smaller voltage drop across the MOS transistors reduces the effect of velocity saturation in the short channel regime (3) the complementary structure offers higher trans-conductance for a given current, which results in fast switching of the cross-coupled pair (4) the output swing is more symmetry to alleviate the noise up-conversion effect and then phase noise performance is improved[8]. In addition, the current source is in parallel with a capacitor which provides a path to remove the noise disturbance from the current source. For symmetry the capacitor is actually placed at both sides of the current source.
The SCA (switched-capacitor-array) is formed with four pairs of binary-weighted MIM capacitors and four MOS transistors as digital-control switches. But actually the term 2C is replaced for the original term 8C because the bandwidth is already sufficient and using larger capacitors means increasing the load. The SCA provides coarse tuning while the varactors are in charge of fine tuning. In other words, the digital-control signal (B0, B1, B2, and B3) decides that which band the oscillation frequency is in and then analog-control voltage (Vctrl) controls the actual oscillation frequency. According to the rule mentioned above, the requirement for varactors is relaxed because the varactors are not responsible for the whole bandwidth. Fig. 2-4 shows the SCA modification. The MOS switches are not directly connected to the ground, and instead they are connected to both capacitors. This topology can avoid the substrate noise coupling into the tank and halve the number of the MOS switches.
Therefore the on-resistance can be reduced and phase noise is improved. The inverted digital-control signals assure that both gate-source and gate-drain junctions are reverse-biased in the OFF state and vice versa[9]. As a result, the effective capacitance of SCA is:
∑
=Fig. 2-4 (a) The conventional SCA and (B) the adopted SCA in this circuit
According to Fig. 2-2, the topology of LC-resonant oscillators is positive feedback. For the sake of stable oscillation, the trans-conductance has to be large enough to restore energy dissipated in the resistance of the LC-tank. In other words, the impedance of the active network should be equal to –Reff and the unity loop gain is achieved[10]. Consequently, the
oscillation frequency and required trans-conductance are:
Fig. 2-5 Model of the LC-resonant oscillator with parasitic resistance
In regard to low power consumption, the bias current is supposed to be small and then trans-conductance shrinks. As a result, the bias current should be chosen carefully. Also the overdrive voltage of the cross-coupled transistors needs prudent consideration to accomplish a good compromise between phase noise, tuning range, and power dissipation. Considering the parasitic resistance and non-ideal passive components in Fig. 2-5, the required trans-conductance can be expressed as
p
with fo the oscillation frequency, Rc the capacitor series resistance, Rl the inductor series resistance, and Rp the parasitic resistance. Moreover, to ensure reliable start-up, the active network has to provide 2~3 times required trans-conductance[10]. Now the bias current can be determined:
where Imn, gmn and VOD are the bias current, trans-conductance, and overdrive voltage of the NMOS transistors in Fig. 2-3. Finally, the phase noise can be found in the following
expression
where VA is the amplitude of the output swing, A is the noise contribution factor of the active network (usually equal to or larger than 1), and Δf is the offset frequency from the carrier at fo. Through Eq. ( 2-6 ), there is trade-off between power dissipation and phase noise performance.
Therefore a power-frequency-normalized (PFN) figure-of-merit (FOM) is often used to compare the performance of VCOs for both power consumption and phase noise[11].
}
A greater FOM corresponds to a better oscillator.
There are several new RF passive elements in TSMC RF 1P6M 0.18 μm CMOS technology. The improvement of the passive element leads to the better circuit performance.
In the fully integrated VCOs, the low Q-factor LC-tank is mainly caused by the spiral inductors. Symmetric inductors have higher Q-value thanks to their geometric characteristic.
The layout of the symmetric inductor in this circuit and its equivalent lumped circuit are shown in Fig. 2-6 with spacing=2 μm, width=15 μm, radius=47 μm, and 2 turns. The equivalent inductance Leq is about 0.555 nH and the parasitic resistance Rl is 1.8 Ω. In addition, the accumulation-mode MOS varactors is offered with a higher Q-value and larger capacitance variation range than diode varactor[12]. Here Fig. 2-7 shows the layout of the varactor and its equivalent lumped model. The MOS varactor has 17 branches in one group.
The equivalent capacitance Ceq is about 40.8~153 fF and the parasitic resistance Rc is 6.24 Ω.
After considering the SCA, VCO output stage and parasitic effect from the chip layout, the simulated VCO oscillation frequency is around 8.9 GHz. Due to the lumped models of spiral inductor and MOS varactors, the required trans-conductance and bias current can be decided
by Eq. ( 2-4 )and ( 2-5 ).
Besides, it is possible that the Gm and IBIAS are a little bit insufficient owing to omitting some parasitic resistance. But it still provides a good starting point for the design.
(a)
(b)
Fig. 2-6 (a) Layout and (b) its lumped model of the symmetric spiral inductor
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(b)
Fig. 2-7 (a) Layout and (b) its lumped model of the MOS varactor
2.1.2 High Frequency Divider
Frequency dividers operating at high frequency are one of the key blocks in the RF circuits because dividers must function properly over the required bandwidth and provide enough output swing for the next stage. Three kinds of dividers are often used: digital CMOS logic, current-mode logic (CML), and injection-locked frequency dividers (ILFD)[13]. Digital CMOS logic is seldom used since full-scale swing is needed and the operating frequency is relatively low. Compared with CML, ILFD has lower power consumption with larger area and
narrower locking range. Due to very wide bandwidth of VCO, the CML is chosen in this work[14].
Fig. 2-8 Block diagram of the CML frequency dividers
Fig. 2-9 Schematic of the CML frequency dividers
The block diagram of CML frequency dividers is shown in Fig. 2-8. The frequency of both Vm and Vo is half the frequency of Vi. Meanwhile the phase difference between Vm and Vo is just 90 degree and quadrature outputs are obtained. In other words, CML is also a kind of quadrature signal generators owing to the characteristic of the output nodes. According to Fig. 2-9, the master and slave D-FFs (D-type flip-flop) are clocked by complementary clocked signals and the differential outputs of LC-VCO in the previous section provide this kind of input signals. Consequently, the inverter in Fig. 2-8 is implemented without adding any circuit.
The D-FFs implemented in CML are composed of a clocked differential sensing amplifier pair and inversely clocked latching pair. In contrast with common CML circuits, the bias current source is eliminated to increase the maximum operating frequency about 10 %[15].
Only NMOS transistors are used in this circuit because the drain parasitic capacitance and power dissipation should be minimized. Due to omitting the current source, the bias point of this divider is determined by the DC level of the input signals, the size of the clock transistors and the load resistance. The trans-conductance of clock transistors has to be large and then the small input signals can drive them from the linear region to the saturation region.
Therefore the sensitivity to the DC level of input signals is increased. The load resistance is another key parameter since the dominant pole is decided by the load resistance and parasitic capacitance from transistors, interconnection, and next stage. As a result, the load resistance has to be kept small to make the dominant pole high enough and it is inevitable to raise the bias current to assure the next stage of proper DC input level.
(a) (b)
Fig. 2-10 Schematic of (a) the latching pair and (b) the sensing pair
Fig. 2-11 Comparison of amplification in (a) the latching and (b) the sensing
As shown in Fig. 2-10, the latching pair works in positive-feedback regeneration while sensing pair is in common-source configuration.
latching pair : 1 ) latching pair boosts the output exponentially while the sensing pair is an approximately linear amplifier. When the trans-conductance of latching pair is large, the latching is fast but changing state is difficult. Additionally, the clock is fed by sinusoidal signal rather than square wave. The grey area is wider between latching and sensing. In consequence the size of the sensing pair transistors has to be a bit greater than the size of the latching pair ones.
2.1.3 2-to-1 Multiplexer
Fig. 2-12 Schematic of the 2-to-1 multiplexer
In the beginning of this chapter, it is mentioned that a multi-band VCO provides carrier frequencies in Band Group #3 and #4 while a frequency divider is in charge of frequencies in Band Group #1 for the MB-OFDM UWB system. As a result, there is a 2-to1 multiplexer to decide that the output is generated from VCO or the divider. Fig. 2-12 shows the schematic of the multiplexer. Again the current source is removed to relax the voltage headroom problem[16]. When Vsel is high, MS2 is off and the output is only from the VCO. On the contrary, when Vsel is low, MS1 is off and the output is only from the divider. Because the output signals are spread in a very wide range of spectrum, the gain must be insensitive to the operating frequency. The load inductors and capacitors should be designed as large as possible to alleviate the impedance variation with the frequency. Therefore the bias-tee is chosen as the load impedance. The inductor and capacitor in the bias-tee can be treated as infinitely large at the multi-GHz frequency. For this reason, the load impedance is approximately only RL (50 ohm). The pure-resistive impedance fulfills a gain without dependency of the operating frequency.
In MB-OFDM UWB system, the channel switching time is about only 9.5 nsec. As a result, the multiplexer must change the output signals in a time less than the required period.
Because MS1 and MS2 work as complementary switches, the length of these two transistors is
kept the minimum value and the width is supposed to be a reasonable value to compromise between parasitic capacitance and trans-conductance.
2.2 Chip Layout and Simulation Results
A signal generator for UWB system is designed and optimized through Eldo RF simulator. The whole chip is 0.83×1.12 mm2 and fabricated in TSMC RF 1P6M 0.18 μm CMOS technology. Fig. 2-13 is the layout of this circuit. In order to extract the parasitic effect from the interconnection, Calibre xRC is adopted for the post-simulation. However it is insufficient to consider parasitic capacitance and resistance only. Parasitic inductance accompanies the interconnections in the circuits operating at multi-GHz band. Consequently, Sonnet software is also used to convert critical parts of the layout into s-parameter files and the interconnections are treated as transmission lines. Several parts of the whole chip are processed by Sonnet software and Fig. 2-14 shows one example. Besides, the layout should be kept symmetry to equalize the amplitude of the differential outputs. The power dissipation of each block is listed in Table 2-1.
As shown in Fig. 2-15, the tuning range is 5.97~9.22 GHz (about 42.8% of the center frequency) for the total 10 curves. A particular digital-control signal obtains its corresponding curve. Overlapping between curves is necessary to cover the entire band. In the lower bands, the slopes of these tuning curves and the distances between curves are smaller. The following equation can prove this.
Due to larger capacitance in the lower bands, Δf becomes smaller. In other words, the oscillation frequencies in the lower band don’t vary as much as those in the higher bands.
Fig. 2-13 Layout of the whole chip
(a)
(b)
Fig. 2-14 (a) Imported layout and (b) extracted S-parameter in Sonnet software Table 2-1 Power dissipation of each blocks in this circuit
Power Current
VCO 7.09 mW 3.94 mA
divider 9.43 mW 5.24 mA
multiplexer 21.39 mW 11.88 mA
total 37.91 mW 21.06 mA
Fig. 2-15 Tuning range curves of VCO with different banks
When the control voltage is 1.05 V with digital input (0,0,0,0), the oscillation frequency is 8.976 GHz. The output swing is 0.95 VPP (3.53 dBm) and the phase noise is -111 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 4.488 GHz is also generated.
These results are shown in Fig. 2-16 and Fig. 2-17.
Fig. 2-16 Output waveform of VCO and frequency divider
Fig. 2-17 Phase noise with oscillation frequency at 8.976 GHz
When the control voltage is 0.98 V with digital input (0,0,0,1), the oscillation frequency is 8.448 GHz. The output swing is 0.86 VPP (2.67 dBm) and the phase noise is -111 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 4.224 GHz is also generated.
These results are shown in Fig. 2-18 and Fig. 2-19.
Fig. 2-18 Output waveform of VCO and frequency divider
Fig. 2-19 Phase noise with oscillation frequency at 8.448 GHz
When the control voltage is 0.77 V with digital input (0,0,1,0), the oscillation frequency is 7.92 GHz. The output swing is 0.82 VPP (2.26 dBm) and the phase noise is -112 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 3.96 GHz is also generated.
These results are shown in Fig. 2-20 and Fig. 2-21.
Fig. 2-20 Output waveform of VCO and frequency divider
Fig. 2-21 Phase noise with oscillation frequency at 7.92 GHz
When the control voltage is 1.47 V with digital input (1,0,0,0), the oscillation frequency is 7.392 GHz. The output swing is 0.8 VPP (2.04 dBm) and the phase noise is -113 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 3.696 GHz is also generated.
These results are shown in Fig. 2-22 and Fig. 2-23.
Fig. 2-22 Output waveform of VCO and frequency divider
Fig. 2-23 Phase noise with oscillation frequency at 7.392 GHz
When the control voltage is 0.5 V with digital input (1,0,0,1), the oscillation frequency is 6.864 GHz. The output swing is 0.7 VPP (0.88 dBm) and the phase noise is -114 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 3.432 GHz is also generated.
These results are shown in Fig. 2-24 and Fig. 2-25.
Fig. 2-24 Output waveform of VCO and frequency divider
Fig. 2-25 Phase noise with oscillation frequency at 6.864 GHz
When the control voltage is 1.27 V with digital input (1,1,1,0), the oscillation frequency is 6.336 GHz. The output swing is 0.64 VPP (0.1 dBm) and the phase noise is -113 dBc/Hz at 1 MHz offset. Through the frequency divider, another signal at 3.168 GHz is also generated.
These results are shown in Fig. 2-26 and Fig. 2-27. Finally, the output power and the phase noise are listed for all carrier frequencies in Table 2-2.
Fig. 2-26 Output waveform of VCO and frequency divider
Fig. 2-27 Phase noise with oscillation frequency at 6.336 GHz
Table 2-2 Output power and phase noise performance of the carrier frequencies Carrier Frequency Output Power Phase noise @ 1MHz FOM
6.336 GHz 0.1 dBm -113 dBc/Hz 180.53
6.864 GHz 0.88 dBm -114 dBc/Hz 182.23
7.392 GHz 2.04 dBm -113 dBc/Hz 181.87
7.920 GHz 2.26 dBm -112 dBc/Hz 181.46
8.448 GHz 2.67 dBm -111 dBc/Hz 181.03
8.976 GHz 3.53 dBm -111 dBc/Hz 181.56
Because the 2-to-1 multiplexer is in charge of the output signals from VCO or the frequency divider, its bandwidth and switching time are important parameters. A very large bandwidth (10M~10GHz) is achieved in Fig. 2-28. According to Fig. 2-29, the switching period is 0.8 nsec when the multiplexer changes the output from VCO to the divider.
Furthermore, the band switching in the VCO also needs to be short enough. In Fig. 2-30, the band switching is completed in about 0.65 nsec. In consequence, both of the periods are much shorter than the required time (9.5 nsec).
Fig. 2-28 Gain of the multiplexer vs. the input frequency
Fig. 2-29 Output waveform switching from VCO to the divider
Fig. 2-30 Output waveform switching from bank (1,1,1,1) to bank (0,0,0,0)
The simulation also considers PVT (process-voltage-temperature) corner variations. The tuning range curves are simulated under different conditions. The results are shown in Fig.
2-31~Fig. 2-36 and summarized in Table 2-3. The curves are almost invariant regardless of any corner variation.
Fig. 2-31 Tuning range curves at FF corner
Fig. 2-32 Tuning range curves at SS corner
Fig. 2-33 Tuning range curves at VDD=1.62 V
Fig. 2-34 Tuning range curves at VDD=1.98 V
Fig. 2-35 Tuning range curves at T=-10°C
Fig. 2-36 Tuning range curves at T=60°C
Table 2-3 VCO tuning range under different conditions
Process corner SS TT FF
5.97~9.22 GHz 5.97~9.22 GHz 5.96~9.22 GHz Supply voltage 1.62 V 1.8 V 1.98 V
5.97~9.21 GHz 5.97~9.22 GHz 5.96~9.23 GHz
Temperature -10°C 25°C 60°C
5.97~9.23 GHz 5.97~9.22 GHz 5.96~9.22 GHz
2.3 Measurement Results
The results are obtained from on wafer circuit measurement in National Chip Implementation Center (CIC). The instruments contain Agilent E5052A signal source analyzer, E4407B spectrum analyzer, and E3615A DC power supply in Fig. 2-37. Also the whole chip photograph is shown in Fig. 2-38.
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(b)
(c)
(d)
Fig. 2-37 Measurement instruments (a) Agilent E5052A signal source analyzer (b) E4407B spectrum analyzer (c)E3615A DC power supply and (d) whole test set