Circuit Simulation

According to the simulation results from Eldo RF, the multi-modulus frequency divider works properly at 10 GHz maximally. The waveforms at four stages of the frequency dividers with a division ratio 34 are shown in Fig. 3-28 to prove its locking range. This ensures the output signal can be divided accurately to be compared with the reference clock at any time.

Then, Fig. 3-29 shows the correct comparison result when REF leads DIV 0.95 cycle. Under the condition of bank (0000), the characteristic of the PFD and the charge pump is shown in Fig. 3-30 which is similar to Fig. 3-15. According to the simulation, the valid comparison range is about ±1.89π. It helps the loop to settle rapidly. Also the frequency response of the wideband buffer is shown in Fig. 3-31. The amplitude error in the desired band is smaller than 1 dB.

Fig. 3-28 Individual waveforms of dividers at 10 GHz input signal

Fig. 3-29 Waveforms when REF leads DIV 0.95 period

Fig. 3-30 Characteristic of the PFD and the charge pump

Fig. 3-31 Frequency response of the wideband buffer

The transient waveforms and power spectrums at six carrier frequencies are shown in Fig.

3-32~Fig. 3-43. The locking time is less than 300 nsec with different carriers. It is a little longer than the values in both the hand calculation and the behavior simulation. But this interval is still met the specification. The spurious tone is smaller than -34.2 dBc at 264 MHz offset. In fact, the spur is not critical in this synthesizer because the reference frequency is just

half of the channel bandwidth, which is an advantage mentioned in section 3.2. Moreover, the worst phase noise is -109.8 dBc/Hz at 1 MHz offset and far lower than the value (-86.5 dBc/Hz) specified in Section 1.2. Finally, according to Fig. 3-44, the maximal I/Q channel phase mismatch is about 3.1° and still tolerable in the system requirement.

Fig. 3-32 Transient waveform when locking at 6.336 GHz

Fig. 3-33 Power Spectrum of the output at 6.336 GHz

Fig. 3-34 Transient waveform when locking at 6.864 GHz

Fig. 3-35 Power Spectrum of the output at 6.864 GHz

Fig. 3-36 Transient waveform when locking at 7.392 GHz

Fig. 3-37 Power Spectrum of the output at 7.392 GHz

Fig. 3-38 Transient waveform when locking at 7.920 GHz

Fig. 3-39 Power Spectrum of the output at 7.920 GHz

Fig. 3-40 Transient waveform when locking at 8.448 GHz

Fig. 3-41 Power Spectrum of the output at 8.448 GHz

Fig. 3-42 Transient waveform when locking at 8.976 GHz

Fig. 3-43 Power Spectrum of the output at 8.976 GHz

Fig. 3-44 Waveform of the quadrature output

3.4 Summary and Comparison

A fast-settling and low power frequency synthesizer is designed for MB-OFDM UWB system. The performance is summarized in Table 3-4. It meets all specifications which are found out in Section 1.2. The power dissipation in each block is also listed in Table 3-5. Due to the adjustable current in the charge pump, the total power consumption is varied from 46.35 to 48.24 mW. In the end, the comparison is made with the reference paper [24]. The major target of reducing power dissipation is achieved. This work consumes only 54.4% of the power in [24]. The noise performance is also better than the reference’s. The setting time is approximately twice in consequence of slower reference clock. However, the specification is still met.

Table 3-4 Output power and noise performance of the six carrier frequencies

Table 3-5 Power dissipation of each block Power (mW) Current (mA)

Table 3-6 Comparison with the reference paper

6.17～9.11 GHz 6.28~9.17 GHz

Average Phase Noise

Chapter 4 Conclusions and Future Work

4.1 Conclusions

In this thesis, a fast-locking and low power frequency synthesizer is designed for MB-OFDM UWB system. The locking time is less than 300 nsec to meet the specification when two frequency synthesizers are used by turns. This can avoid adopting many complicated single side-band mixers and multiplexers. The reference frequency is 264 MHz and the spurious tones have no undesired effect upon the channel. Moreover, the whole chip power dissipation is only 46.35 mW and greatly reduced because of the proposed topology of the programmable multi-modulus divider. The simulation results are listed and compared with the reference paper. It indeed shows a better performance.

In addition, a signal generator for MB-OFDM UWB system is also demonstrated. The VCO has a very wide tuning range (6.12~9.15 GHz) to cover Band Group #3 and #4. A divider-by-2 circuit follows the VCO and provides carriers in Band Group #1. Besides, a 2-to-1 wideband multiplexer has a flat frequency response over the 3~9 GHz and is included to select the output source: VCO or the divider. The measured tuning range and phase noise approximately agree with the simulation results. The best phase noise is -115 dBc/Hz at 1 MHz offset. The total power consumption is 36.63 mW while the VCO core dissipates 7.09 mW. By the power-frequency-normalized figure-of-merit (FOM), a VCO with both wide tuning range and low phase noise is presented in this circuit.

Table 4-1 Performance of two works in this thesis

6.12～9.15 GHz 6.28~9.17 GHz

Average Phase Noise

There are several ways to improve the design of the frequency synthesizer for MB-OFDM UWB system. First, the wideband multiplexers have to replace the output buffers.

As a result, both the QVCO and divider-by-2 circuit can provide carriers for Band Group #1,

#3, and #4. This leads a larger load for the divider-by-2 circuit. Therefore the divider should be re-designed and a complicated layout needs to be planned well. Second, the adopted passive loop filter produces less noise but causes the narrower valid range at the control voltage. In consequence, the carrier frequencies should be located at the centers of tuning range curves for predicted transient behavior and low spur. If an op-amp can be implemented with low noise, the performance is supposed to be improved further. Third, the EM parasitic effect has to be extracted more extensively. This takes much longer time in simulation but brings more reliable results. Finally, the supply voltage is chosen as 1.5 V for battery use. In the measurement, the battery means less noise and cleaner DC source. For the practical application, band-gap reference circuits can be used for every bias voltage. It not only improves the noise performance but also reduces the number of the required pads. All the mentioned future works above are believed to lead a mature frequency synthesizer design for the MB-OFDM UWB application.

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Publishing Remarks

International Conference Paper:

1. Shih-Hao Tarng and Christina F. Jou, “A 10 GHz Low Power CMOS Quadrature Voltage-Controlled Oscillator,” IEEE Asia-Pacific Microwave Conference (APMC), Vol. 2, Dec. 2004

Submitting Papers:

1. Shih-Hao Tarng and Christina F. Jou, “A Fully-Integrated, Low Power, Fast-Locking, Integer-N Frequency Synthesizer for MB-OFDM UWB System, ＂ Progress In Electromagnetics Research Symposium (PIERS), Mar. 2007

2. Shih-Hao Tarng and Christina F. Jou, “A Signal Generator for MB-OFDM UWB System in 0.18 um CMOS Process,＂ Progress In Electromagnetics Research Symposium (PIERS), Mar. 2007