Summary and Comparison - Wideband Voltage-Controlled Oscillator and Its Frequency

Chapter 2 Wideband Voltage-Controlled Oscillator and Its Frequency

2.4 Summary and Comparison

The performance in the measurement is close to the results in the simulation except that 4.224 GHz signal is not generated successfully. To improve this, the layout parasitic extraction by EM software has to be more detailed although this will take a far longer time.

The summary of this work is listed in Table 2-6. In addition, the comparison with other wideband VCOs is made in Table 2-7. Through the figure-of-merit (FOM), this work really achieves better performance.

Table 2-6 Summary of the performance in the simulation and measurement

Performance Post-Simulation Measurement

Supply Voltage 1.8V

Power Consumption 37.91 mW 36.63 mW

Tuning Range 5.97~9.22 GHz 6.12~9.15 GHz Phase Noise @ 1MHz -111~-114 dBc/Hz -105.5~-115 dBc/Hz

Output Power 0.1~3.53 dBm -5.85~-0.99 dBm Table 2-7 Comparison with the recent published papers about wideband VCOs

MAPE 2005

FOM 166.97 182.17 180.09 183.31

Chapter 3 Low Power and Fast-Locking Integer-N Frequency Synthesizer for MB-OFDM UWB System

In this chapter, a low power and fast-locking integer-N frequency synthesizer is presented for the MB-OFDM UWB application. Because of the frequency divider in this proposed synthesizer, a remarkable reduction in the power dissipation is achieved.

Additionally, the choice of the reference clock leads immunity against the spurious tone. This circuit is designed by using TSMC RF 1P6M 0.18 μm CMOS technology and applied to be fabricated in June 2006. In the following sections, the architecture and circuit design consideration is demonstrated first. Then each block in this frequency synthesizer will be explained individually. Finally, the simulation results and comparison will also be discussed.

3.1 Architecture

There are three ways to perform frequency generation for MB-OFDM UWB system. One approach is to have multiple PLLs in parallel which are responsible for different frequencies.

In [20], three fixed-modulus PLLs are used for the frequencies in Band Group #1. This method is most direct and easy to meet the specifications. However, it will need too many PLLs while all 14 carrier frequencies are used. It will demand too much power dissipation and large chip area to be practical. The second method is to integrate PLLs with external multiplexers and single side-band (SSB) mixers[21]-[23]. Two specified frequencies are

generated by PLLs and SSB mixers can up/down-convert these two signals into the desired carrier frequency. But the SSB mixers need accurate quadrature inputs and should be highly linear for low spurious tones. These requirements add more complexity and difficulty to the circuits. The third method is using two fast-settling frequency synthesizers to generate the desired signal by turns[24]. As proposed in [3], the symbol interval is 312.5 nsec and the guard time is 9.47 nsec. Therefore a single PLL has to be locked with about 322 nsec. It becomes more practical for a conventional frequency synthesizer which is easy to be implemented. Here the third method is adopted in this thesis.

Fig. 3-1 Block diagram of the synthesizer in [24]

Fig. 3-2 Block diagram of the proposed synthesizer

As shown in Fig. 3-2, QVCO in the proposed synthesizer does not have to generate all signals for whole 3.1~10.6 GHz band. In fact, QVCO is merely responsible for Band Group

#3 and #4 while Band Group #1 is left for the divider-by-2 circuit. Band Group #2 is ignored

for the better coexistence with other wireless standards and Band Group #5 is reserved for the future research. Comparing with [24], there are several modifications in this proposed synthesizer. First, the divider-by-2 circuit is included in the loop. In [24], the dual-modulus /4/5 divider contains six CML DFFs which are power-hungry when operating at high frequencies from QVCO. Therefore it is replaced by a divider-by-2 circuit which consumes less than half original power (including the external divider-by-2) and the load of the oscillator becomes smaller because only two DFFs are needed. Second, two dual-modulus /2/3 dividers are substituted for the /4/5 divider. This reduces the power in the multi-modulus divider again. Section 3.2.2 will give explanation for why the power reduction is made. Third, the frequency of the reference clock is halved. Although this causes the settling time longer, the specification is still met. Moreover the reference frequency is half of the channel bandwidth and then the spur effect on the channel is eliminated. It is resulted from that spurs occur at the center of two neighboring channels and do not pollute the channel anymore (shown in Fig. 3-3). The requirement of the spurious tones is greatly relaxed.

Fig. 3-3 Comparison of spur at different frequencies

3.2 Circuit Design Consideration

According to Fig. 3-2, the proposed frequency synthesizer is based on an integer-N type

phase-locked loop. In contrast with fractional-N type, integer-N type has a fixed division number in every reference clock and then spurious tone is lowered. In addition, it is a simpler structure and dissipates less power. Due to the relatively large frequency resolution (528 MHz) and sufficient locking time, integer-N type is more suitable in this design.

This frequency synthesizer is composed of a quadrature voltage-controlled oscillator (QVCO), a multi-modulus frequency divider, a fast phase-frequency detector, a charge pump with variable current, and an on-chip third-order passive loop filter. There are seven digital input signals: four are to select the tuning range curves of the QVCO and the remainders are to control the division ratio in the multi-modulus divider.

As mentioned in the preceding section, the frequency synthesizer has to settle with 322 nsec over PVT (process-voltage-temperature) corner variations. Therefore the settling time is designed to be approximately 200 nsec. The essential open-loop bandwidth to achieve a settling time of 200 nsec can be roughly calculated by the following equation

)

where Tlock is the locking time, ζe(PM) is the effective damping coefficient as a function of the loop phase margin PM, fstep is the magnitude of the frequency jump, and ferror is the allowable frequency error after locking[25]. This equation is derived from continuous-time approximation. As far as the fastest locking time is concerned, the phase margin should be set to 50°, and ζe(50°) will be about 5[26]. In the case of 528 MHz frequency jump and 1 KHz frequency error tolerance, BW is about 13.2 MHz from Eq. ( 3-1 ). In a PLL design, the reference frequency has to be greater than 10 times of the loop bandwidth in order to guarantee the loop stability[27]. In other words, the assumption of the 264 MHz reference frequency above is quite acceptable. Although the frequency of a conventional crystal oscillator is merely up to tens MHz, a simple PLL can be employed for the synthesis of the reference clock for the consideration of SOC. A narrow band PLL is preferred because phase

noise at an offset above a few hundred kHz has to as low as possible.

In the principle of designing PLLs, wider loop bandwidth leads to more suppression of the in-band VCO phase noise. As a result, noise from other blocks, such as reference, charge pump, and loop filter becomes more important within the loop bandwidth. By the UWB system proposal, the noise requirement is defined as the overall integrated rms phase noise from 0 Hz to infinity and the obtained value should be lower than 3.5°. This integrated phase noise can be calculated by this formula:

where k is the in-band phase noise density (dBc/Hz) and p is the peaking of k[24]. In order to achieve the integrated phase noise below 3.5°, k should be less than -95.5 dBc/Hz while p is assumed to be 0.

Spurious tones from the ripple on the QVCO control voltage do not get much attenuation by the loop filter because of the wide bandwidth. To reduce these spurious tones can be accomplished by matching the current sources in the charge pump. At the output nodes of QVCO, the relative magnitude of the primary sidebands is given by:

REF

where Aripple is the peak amplitude of the first harmonic of the ripple, KV is the gain of the QVCO, and fREF is the reference frequency[29]. For smaller spurious tones, Aripple and KV

should be minimized. Current matching in the charge pump is a method to lower Aripple. KV

should be as small as possible while the tuning range still meets the specification. In this circuit, KV is large and up to 500 MHz/V because a 6~9 GHz band needs to be covered.

Under the condition of the maximal KV and the given 264 MHz reference frequency, the peak fundamental ripple amplitude must be less 10.6 mV to guarantee than sidebands are 50 dB below the carrier.

The output frequency is determined by the multi-modulus frequency divider. The

division factor is controllable even number from 24 to 34. The frequency synthesizer can provide six carrier frequencies which are spread from 6.336 to 8.976 GHz in steps of 528 MHz.

3.2.1 Quadrature Voltage-Controlled Oscillator

There are several ways to obtain quadrature signals: divider-by-2 circuit, RC poly-phase filters, and two interleaved voltage-controlled oscillators. The divider-by-2 circuit needs an oscillator operating at 2 times higher than the desired frequency and a high-speed frequency divider. Both circuits dissipate a lot of power in spite of a smaller chip size. RC poly-phase filters attenuate the signal and increase the effective capacitance of the tank. Also a lot of chip area is needed for a good matching of the filters. For the low power consumption and quadrature phase accuracy, two interleaved voltage-controlled oscillators are adopted in this circuit[28]. According to the Barkhausen criterion, oscillation occurs only when the loop gain [A(jω)]⁴ is unity in Fig. 3-4. Therefore A(jω) has amplitude of one with a 90 degree phase shift and quadrature signals are obtained at the four outputs of these two VCOs.

Fig. 3-4 Two interleaved VCO configuration

As shown in Fig. 3-5(a), the VCO is in a complementary cross-coupled negative-gm configuration. The advantages of this configuration are mentioned in Chapter 2. However, there is a difference from the VCO in Chapter 2. The tail current source is removed to

maximize the output swing. Two benefits are also achieved thanks to the removal of the current source. First the current source is the main contributor to the phase noise[30]. Second, when all transistors in the VCO core are put in GHz-switching bias condition, flicker noise will apparently be reduced by about 10 dB[31]. The dimension of four cross-coupling PMOS transistors is an important parameter. If cross-coupling is made weak, two-tones oscillation exists probably; if it is made strong, DC power is wasted and more capacitance is added into the LC-tank. By means of transient simulations, the optimal width of the cross-coupling transistors should be set to one-third of the width of the core transistors while the length of all transistors is chosen as the minimal length (0.18 μm in this circuit)[32].

(a) (b)

Fig. 3-5 (a) Quadrature voltage-controlled oscillator and (b) switch-capacitor array For a wide tuning range of 6~9 GHz, the SCA (switched-capacitor-array) is used as well as in Chapter 2. SCA is composed of four pairs of binary-weighted MIM capacitors and eight NMOS transistors as digital-control switches. The SCA decides the tuning range curve and then the varactors are for actual frequency. Therefore no bulky varactors are required because the whole bandwidth is not covered only by the varacters. Fig. 3-5 shows the SCA configuration. The NMOS switches are connected to ground directly rather than connected

with bottoms of two MIM capacitors. Despite of several advantages remarked in Chapter 2, NMOS switches connected with the MIM capacitors leads to a more complicated layout and serious parasitic effect.

The passive components in LC tank are symmetric spiral inductors and accumulation-mode varactors again. They improve the phase noise performance due to their higher Q-value and the reason is mentioned in Chapter 2. The layout of the symmetric inductor in this circuit and its equivalent lumped circuit are shown in Fig. 3-6 with spacing=2 μm, width=15 μm, and radius=87 μm. The equivalent inductance Leq is about 0.43 nH and the parasitic resistance Rl is 1.49 Ω. Fig. 3-7 shows the layout of the varactor and its equivalent lumped model. The MOS varactor has 14 branches and two groups. The equivalent capacitance Ceq is about 140.29~339.33 fF and the parasitic resistance Rc is 2.53 Ω. After considering the SCA, VCO output stage and parasitic effect from the chip layout, the simulated VCO oscillation frequency is around 8.9 GHz under the condition of Vctrl=0.9 V and bank(0000). The simulated KV is distributed from 240~500 MHz/V.

(a) (b)

Fig. 3-6 (a) Layout and (b) its lumped model of the symmetric spiral inductor

(a) (b) Fig. 3-7 (a) Layout and (b) its lumped model of the MOS varactor

3.2.2 Multi-Modulus Divider

Fig. 3-8 Programmable frequency Divider Block Diagram

As shown in Fig. 3-8, a programmable frequency divider is implemented by cascaded a divider-by-2 circuit and three dual-modulus asynchronous frequency dividers. This design assures only the first divider works at the highest frequency and no pulse swallow counter or phase select state machine is needed. Moreover, the modulus-control signals of the last stage are produced first and given to the followed stage. Thus the delay in the critical path (the feedback of the first divider) is minimized[33]. In order to integrate the divider-by-2 into the loop, the division ratios are all even. In other words, a step increment is 2. The output frequency can be expressed by the following equation[34].

The required division numbers are distributed over 24~34 while 36 and 38 are reserved for future integration with Band Group #5.

For the wideband locking-range and high reference frequency consideration, current-mode logic (CML) is adopted in the whole programmable frequency divider. The principle of divider-by-2 circuit is already described in Chapter 2. The dual-modulus /2/3 divider and its timing diagram are shown in Fig. 3-9. Every DFF is made up of master-slave latches. When MC bit is low, the output of the first DFF is always high and has no effect on the second DFF. It behaves as a divider-by-2 circuit. By contrast, when MC bit is high, the Vm

can be low and delay the negative half-cycle for one input clock. Therefore the division ratio is turned into 3. The NAND logic gates in Fig. 3-9 can be combined with the DFF as shown in Fig. 3-10[14]. The advantages of this structure over the conventional dual-modulus divider are its simpler and more symmetric layout, improved speed, fully differential schematic, and no extra current for the logic gates[35]. The dual-modulus /3/4 divider functions in a similar way. In Fig. 3-11, a DFF is inserted at the output to lengthen one more reference cycle. As a result, a variable division ratio of 3 or 4 is achieved. The complete multi-modulus frequency divider is shown in Fig. 3-12. Several feedback AND gates are inserted into the feedback path of the individual divider.

Fig. 3-9 Schematic of the /2/3 divider

Fig. 3-10 Circuit implementation of the NAND/flip-flop combination

Fig. 3-11 Schematic of the /3/4 divider

Fig. 3-12 Schematic of the programmable frequency divider

From the schematic, the first DFF in a dual-modulus divider is only loaded with one flip-flop while the second is with more than two including the next stage. Consequently, the

second DFF dissipates approximately twice power as much as the first one. Additionally the consumed power in a divider is also about 50% of the one in the previous divider because the maximum operating frequency halves. According to this power scaling rule, less power of the divider in this work than [24] can be explained. Both /4/5 and /3/4 frequency dividers are required and one divider-by-2 circuit is also essential for Band Group #1 carriers in [24]. It is assumed that the weight is one for a DFF loaded with a flip-flop in the first stage. If the load doubles or the maximum operating frequency halves, the weight will alter proportionally.

According to Table 3-1, power dissipation is theoretically only 45.6% of the power in [24].

The DC power reduction is accomplished indeed.

Table 3-1 Theoretical comparison of power dissipation in dividers 1^st stage 2^nd stage 3^rd stage 4^th stage total

3.2.3 Fast Phase-Frequency Detector

The phase-frequency detector (PFD) compares two inputs from the reference clock and the output at the last stage of the frequency divider. The result decides that the control voltage of VCO is increasing or decreasing and then the output frequency is approaching to the desired value. A conventional tri-state PFD is widely used for the simplicity and wide comparable range of almost ±2π radians. Moreover it can detect both phase and frequency.

The schematic of tri-state PFD is shown in Fig. 3-13. If REF arrives earlier, UP is triggered to high level and then reset to low level until DIV arrives; contrarily if DIV arrives earlier, DN is triggered to high level and reset to low level until REF arrives. Therefore greater phase error

causes longer duration which UP or DN is at high level. The characteristic curve is plotted in Fig. 3-13. Although the comparable range is supposed to be ±2π the comparison produces wrong signals when the phase error is near ±2π practically. This non-ideal phenomenon is from the delay buffer in the reset path of the PFD which is to avoid a dead zone problem. The actually valid phase comparison range shrinks to ±|2π-Δ|. Δ can be found out by

REF delay f t ⋅

⋅

Δ 2π ( 3-5 )

tdelay is the delay time in the rest path and fREF is the reference frequency[36]. In a conventional design, the reference frequency is only a few MHz and Δ is small to ignore. Now the reference clock is 264 MHz and Δ becomes considerable. Therefore the control signal will not monotonically approach to lock-in range and the settling slows. While Δ is even larger than π, the possibility of incorrect comparisons is over 50% and the locking behavior may not be guaranteed anymore. In this case tdelay is about 312 psec and Δ is 0.16π. This value can increase the setting time to some extent.

Fig. 3-13 Schematic and characteristic of a conventional PFD

Fig. 3-14 Topology of TSPC-based DFF

In order to solve such a problem, the precharged PFD is used[36]. The DFF implemented in true single phase clock (TSPC) type is shown in Fig. 3-14. The precharged PFD is to insert one delay stage between CK and the input PMOS of TSPC-type DFFs and the schematic is shown in Fig. 3-15[24]. According to Fig. 3-15, this precharged PFD can still generate effective control signals when the phase error is close to ±2π. Despite of the similar characteristic, this PFD has some advantages over the proposed latch-based PFD in [36].

Lower power consumption and higher accuracy are obtained because the dynamic logic circuits have lower propagation delay and better matching. Fig. 3-16 shows the operation of the precharged PFD. td1 is the delay between REF and D_REF (DIV and D_DIV) and td2 is the duration from a rising edge of a lagging input between REF and DIV to the falling edge of the reset signal. At the second rising edge of REF, the phase error Φ is between 2π-Δ and 2π-δ.

At the falling edge of the following reset signal, D_REF is low and node A is charged to high level. Because REF is high at the same time, node B is discharged to low level and UP becomes high earlier than DN. Therefore the PFD does not miss the signal arriving during reset and provides correct control signal. At the third rising edge of REF, the phase error is greater than 2π-δ. The falling edge of the reset signal occurs while D_REF is already high. As a result, A cannot be charged to high level and B is still high. In other word, UP remains low

在文檔中應用於多頻帶正交分頻多工超寬頻系統之全積體化低功率快速鎖定整數型頻率合成器 (頁 53-0)