Chapter 1 Introduction
1.2 Thesis organization
This thesis discusses about the circuit design and implementation for Ultra-wideband applications. The contents consist of two major topics: “3.1~10.6GHz low-voltage, low-power, low-noise amplifier” and “a 3-to-10-GHz direct frequency synthesizer for MB-OFDM UWB Communications”, respectively in Chapter 2 and Chapter 3. We will present the design flow and experimental results in TSMC 0.18-μm CMOS process. Moreover, we will discuss the reasons of differences between simulation and measurement results.
In Chapter 2, we will present the design and implementation of a low-voltage, low-power LNA for UWB applications. We will discuss the configuration, wideband input/output matching, noise and linearity of LNA. Besides, electromagnetic simulated
software Sonnet is used to approach simulated results to practical circuited property.
In Chapter 3, we will present the design and implementation of multiband frequency synthesizer for UWB applications. This chapter includes two circuits. The first section is an initial frequency synthesizer structure for the low phase noise design, and the circuit can produce three LO bands (8448MHz, 4224MHz and 2112MHz). The second section presents the design and simulated results of a fast-hopping frequency synthesizer that generates clocks for twelve bands from 3 to 10 GHz. The proposed topology provides a simple efficient method of frequency synthesizer to create multiband LO signals.
Finally, we discuss our simulated and measurement results, self-criticisms of the shortcomings in specification, and future prospects in Chapter 4. The UWB receiver and the advanced transceiver structure for cognitive communications are described for future communications.
Chapter 2
Low-voltage, Low-power, Low Noise Amplifier for UWB Receivers
2.1 Introduction
A UWB receiver, diagrammed in Fig. 2.1.1, will feature a low-noise amplifier (LNA) followed by a correlator that removes the carrier from the received radio frequency (RF) signal. Analog-to-digital conversion will then allow for digital signal processing aimed at recovering the information data. In this chapter, it is clear that, regardless of what the future standard will be, a wideband LNA operating over the entire 7.5-GHz band of operation is required. Such an amplifier must feature wideband input matching to a 50-Ω antenna for noise optimization and filtering of out-of-band interferers. Moreover, it must show flat gain over the entire bandwidth, good linearity, minimum noise figure (NF) and low power consumption.
Fig. 2.1.1 Block diagram of a UWB receiver
Several CMOS LNA design techniques had been reported for broadband communication applications. The well-developed distributed amplifier is known as its excellent performance of gain-bandwidth product. However, as shown in Fig. 2.1.2, it requires several area consuming inductors to perform signal delay and many stages to provide a given gain that
consumes much power [4-5]. In other work, a cascode configuration [6] is used to achieve good performance with less number of active elements and power. Therefore, we will introduce the cascode structure and focus on the design and implementation of LNA for low-power, low-voltage UWB system. Besides, the electromagnetic effect of transmission lines is considered to minimize the difference between measured and simulated results in the improved LNA circuit.
Fig. 2.1.2 Conventional distributed amplifier
2.1 Architectures
The fundamental architecture of the UWB LNA is shown in Fig. 2.2.1. A cascode configuration with source inductive degeneration is used for the requirement of low power consumption. The cascode structure also has good properties of better reverse isolation, frequency response, lower noise figure and less Miller effect. [8-9]. To get flat gain performance over wide bandwidth, serial resistor Rd is used to improve the gain at low frequency.
In order to achieve wideband input matching from 3.1 to 10.6 GHz, the three-section Chebyshev filter is usually used in the input matching network by combining the gate-drain parasitic capacitance of M1 and the inductance Ls. In the conventional design, a capacitor is
usually added in parallel with the gate-drain parasitic capacitance to help design flexibility. In our design, we will try to simplify input matching network, and still maintain the wideband matching.
Fig. 2.2.1 The fundamental architecture of the UWB LNA
The noise performance of the proposed topology is determined by two main contributors:
the losses of the input network and the noise of the amplifying device M1. The noise contribution of the input network is due to the limited quality factor Q of the integrated inductors. Its optimization relies on achieving the highest Q for a given inductance value, but it is limited by the wideband requirement of inductances that must be low-Q characteristic.
Therefore, the optimization of the noise contribution from M1 is important and needs to extend the analysis to the wideband case. Finally, the size of M1 is determined.
An output-matching buffer is designed to achieve flat gain over the whole bandwidth and generate more output current. Unlike common source amplifier, the common drain structure is designed to supply current gain in high frequency. The size of M3 and the type of current source will determine the high-frequency characteristic of UWB LNA.
For the UWB technology to be widely employed in the hand-held wireless applications, it
bandwidth, low noise and enough power gain while keeping low power dissipation will be discussed in the next section where a low power UWB LNA topology is presented.
2.3 Design considerations
2.3.1 Input matching analysis
The technique of filter design is employed for wideband input impedance matching. The two kinds of the most common used filter design technique are image parameter method and insertion loss method. The first one, image parameter method, consists of a cascade of simpler two-port filter sections to provide the desired cutoff frequencies and attenuation characteristics. Thus, although the procedure is relatively simple, the design of filters by image parameter method must often be iterated many times to achieve the desired results and that will result in large chip area. The other one, insertion loss method, uses network synthesis techniques to design filters with a completely specified frequency response. The design is simplified by beginning with low-pass filter prototypes that are normalized in terms of impedance and frequency. Transformations are applied to convert the prototype designs to the desired frequency range and impedance level [9]. The insertion loss method is used to design the broadband input matching for diminishing the implement costs. The Butterworth (Maximally flat) and Chebyshev (Equal ripple) filter design are two familiarly practical filter responses by used insertion loss method. The Butterworth design offers a smooth response curve with maximal flatness at zero frequency. The Chebyshev design offers a steeper response curve at the 3 dB cutoff frequency and requires fewer components. In this work, to have precipitous response curve at 3 dB cutoff frequency, the Chebyshev filter design is chosen. The filter designs can be scaled in terms of impedance and frequency, and converted to bandpass characteristics. This design process is illustrated in Fig. 2.3.1.
Fig. 2.3.1 The process of filter design by the insertion loss method The filter response is defined by its insertion loss, or power loss ratio, PLR:
)2 even function of ω; therefore it can be expressed as a polynomial in ω2. Thus
)
where M and N are real polynomials in ω2. Substituting this form to (2-1) gives the following:
)
Thus, for a filter to be physically realizable its power loss realizable its power loss ratio must be of the form in (2-3). Notice that specifying the power loss ratio simultaneously constrains the reflection coefficient, Γ(ω).
In this design, the Chebyshev polynomial is used to specify the insertion loss of an N-order low-pass filter as
The passband response will have ripples of amplitude 1+k2, as shown in Fig. 2.3.2, since TN(x) oscillates between ±1 for |x|≦1. Thus, k2 determines the passband ripple level.
Fig. 2.3.2 Chebyshev (equal-ripple) low-pass filter response (N=3)
From the power loss ratio equation of Chebyshev filter, the normalized element values of L and C of low-pass filter prototypes is shown in Fig. 2.3.3, and the normalize values are listed in Table 2.3.1.
(a)
(b)
Fig. 2.3.3 Ladder circuits for low-pass filter prototypes and their element definitions. (a) Prototype beginning with a shunt element. (b) Prototype beginning with a series element.
Table 2.3.1 Element values for equal-ripple low-pass filter prototypes (g0=1, ωc=1, N=1 to 3, 0.5dB ripple) [10]
N g1 g2 g3 g4
1 0.6986 1.0000
2 1.4029 0.7071 1.9841
3 1.5963 1.0967 1.5963 1.0000
Low-pass prototype filter designs can be transformed to have the bandpass response. If ω1
and ω2 denote the edges of passband, then a bandpass response can be obtained using the following frequency substitution:
Δ is the fractional bandwidth of passband. The center frequency, ω0, could
be chosen as geometric mean of ω1 and ω2, i.e.ω0 = ω1ω2 . The low-pass prototype transfers to the band-pass filter type. The elements based on Table 2.1 are converted to series or parallel resonant circuits. The series inductor, Lk, is transformed to a series LC circuit with element value:
The shunt capacitor, Ck, is transformed to a shunt LC circuit with element value:
k
Fig. 2.3.4 shows the complete transformation circuit of low-pass filter converted to band-pass filter.
Fig. 2.3.4 Components convert from low pass filter to band-pass filter
Fig. 2.3.5 Small signal equivalent circuit of the inductive source degeneration structure In Fig. 2.3.5, since the input impedance of the MOS transistor with inductive source degeneration can be seen as a series RLC circuit
s of our third-order Chebyshev L-C filter structure can then absorb this MOS input impedance into its network. The size of M1 determines not only third-order L-C tank of band-pass filter but also the noise performance. According to these basic formulas, the models of authentic inductor and capacitor, and trading off noise performance, we can then omit the capacitor C2’ that shunts with the inductor L2’, and the capacitor C3’ is wholly replaced by the capacitance Cgs of M1 without connecting additional capacitor, as shown in Fig. 2.3.6 [11]. The inductor L3 is replaced by the inductors Lg and Ls. Besides, because the frequency of input signal is up to 10GHz, the electromagnetic effect of transmission lines changes the characteristic of the input matching network. The effect of transmission lines between components is considered and simulated by the software, Sonnet. The whole input matching network is shown in Fig.
2.3.7. The block of S2P vin means the equivalent S-parameter model of the transmission line
between input node and the inductor L1. The block of S2P net01 means the equivalent S-parameter between the inductor L1 and the capacitor C1, and so on. The capacitor Cpad is the parasitic capacitance from the RF signal pad to ground. Therefore, the input network has lower complexity and good reflected coefficient from 3.1GHz to 10.6GHz. The Smith chart of the simulated return loss (S11) from 3.1 to 10.6 GHz is shown in Fig. 2.3.8.
Fig. 2.3.6 Basic schematic of the LNA input network
Fig. 2.3.7 The whole schematic of the LNA input network
Fig. 2.3.8 The Smith chart of the simulated return loss (S11) from 3.1 to 10.6 GHz
2.3.2 Noise analysis
The noise performance of the proposed topology is determined by two main contributors:
the losses of the input network and the noise amplifying device M1. The noise contribution of the input network is due to the limited quality factor Q of the integrated inductors. Its optimization relies on achieving the highest Q for a given inductance value. The optimization of the noise contribution from M1 relies instead on the choice of its width for a given bias current. Optimum device width has been fully discussed in the literature in the case of narrow-band LNA design [12]. The noise analysis of the wideband case is the optimization of the performance on the in-band average NF, as opposed to the NF at a single frequency. The analysis follows the guidelines of [14] in a dual fashion and with the difference that the loading effect of the local feedback inductor is taken into account. MOS transistor noise sources, shown in Fig. 2.3.9(a), are input-referred in a conventional way and replaced with two correlated noise generators, as shown in Fig. 2.3.9(b):
(a) (b)
Fig. 2.3.9 Noise model for the amplifying transistor M1 (a) M1 noise sources (b) input-referred equivalent noise generators.
nd
where ind is the drain noise current, due to the carrier thermal agitation in the channel, while ing is the induced gate noise, due to the coupling of the fluctuating channel charge into the gate thermal. The induced gate noise and drain current noise power spectral densities are, respectively
The noise voltage en can be expressed as the sum of two components, one fully correlated, enc, and the other, enu, uncorrelated to the noise current as follows:
nu nc
n e e
e = + (2-15)
Carrying out the calculations, the correlation impedance Zc is written as
( ) ( )
c= / is the correlation coefficient between the gain noise and the drain noise. For MOS devices, the value of c is ≈ j0.4. The parameter
/ d0
m g
=g
α accounts for short-channel effects. It describes the transconductance reduction due to velocity saturation and mobility decrease due to the vertical fields.
The two uncorrelated noise sources, enu and in, are described by means of the following
By using the introduced parameters, the NF can be expressed by
s
Class noise optimization theory [13], shows that the minimum NF is achieved if the source impedance Zs =Zopt =Ropt+ jXopt is chosen such that
Equations (2-16) and (2-21) show that the optimum source impedance is roughly the one that
resonates the series combination of Cgs and Ls. As a consequence, nearly minimum NF is achieved over the entire amplifier bandwidth by using the proposed input network, which produces Xopt over a wide bandwidth. As a result of the foregoing discussion, the NF of the LNA is
Equations (2-22) and (2-23) show that, as α≦ 1 and χ < 1, using a smaller transistor for a given gm, i.e., drawing more current, is preferable. Moreover, increasing the transconductance improves the noise performance, with all of the other parameters being the same.
The LNA NF described by (2-22) depends on three of the following four quantities: the drain bias current ID, the over-drive voltage Vod, the transistor width W, and the frequency. In order to perform an optimization over the entire band of interest, the average NF must be considered. According to [6], Fig. 2.3.10 shows the contour plots of the average NF as a function of ID and W. For each value of the bias current, the device width can be chosen to minimize the NF.
Fig. 2.3.10 Contour plots of the average NF [6]
In order to minimize the average NF, the more drain bias current ID has the better NF performance, but it consumes more power. Therefore, in the condition of fixing the power consumption, decreasing the supply voltage and increasing the current can improve NF performance. Therefore, the supply voltage in this design is set a low voltage of 1V. The best average noise performance is achieved if 200 μm < W < 400 μm. Note that quantitative results of Fig. 2.3.10 only refer to the noise contribution of M1. Moreover, note that the NF decreases with the scaling of MOS technology. The NF in an actual LNA implementation is thus expected to be worse because of:
1. the losses of the input network, i.e., the limited quality factor of the integrated inductors;
2. the cascode device (M2) noise contribution, particularly significant at higher frequencies;
3. the load resistance (Rd) noise contribution;
4. the output buffer (M3) noise contribution.
2.3.3 Gain analysis
A single-cascode configuration with source inductive degeneration is used for improving the reverse isolation, frequency response, better noise figure and lower Miller effect. It also provides low-power characteristic at low supply voltage. The whole circuit of UWB LNA is shown Fig.2.3.11.
Fig. 2.3.11 The schematic of UWB LNA
At upper frequency, the transistor’s behavior is like a current amplifier. The current gain isβ
( )
s =gm/sCgs, and the current into M1 is Vin⋅W( )
s /Rs, where W(s) is Chebyshev transfer function. Therefore, the voltage gain is[
d d c]
capacitance of M2, and Cgd3 is the gate-drain capacitance of M3. Equation (2-23) shows that the current gain roll-off is compensated by Ld. Moreover it shows that Cc introduces a spurious resonance with Ld, which must keep out-of-band.The total parasitic capacitance at the drain of M1 (sum of Cdb1 and Cgs2) introduces a pole that limits the bandwidth of the amplifier at high frequency. By connecting the bulk of M1 to
its source, the performance of the amplifier is improved, as shown in Fig. 2.3.12.
Fig. 2.3.12 Impact of parasitic capacitances
In this way, the capacitance between the source and the bulk of M1 is shorted, and Cdb1 is connected between the drain and the source of M1. This decreases the contribution of Miller effect from Cdb1 and the total capacitance at the drain node at high frequency. This results in an enhancement of the bandwidth of amplifier.
The source–follower buffer (M3 in Fig. 2.3.9) is needed to drive an external low-impedance load. The external output voltage V ′ is related to the output voltage of the out amplifier by
The buffer is designed to improve the power gain of the amplifier at high frequency. The inductance Ls2, as a current source, biases the buffer and is simulated as a matching element to maintain high gain at upper frequency. As a consequence, we can achieve the flat gain between 3.1-10.6GHz.
2.4 Chip implementation and measured results
2.4.1 Layout considerations
The chip photo of the UWB LNA is shown in Fig. 2.4.1. The layout skill is very important for radio frequency circuit design because it may affect circuit performance very much. In
order to reduce noise that is considered in Section 2.3.2, the MOSFET is used as multi-finger, which total width is 320 μm, and the power supply (Vdd) is 1V. The 0.18μm (minimum) gate length was chosen to get the highest speed. The MIM (Metal-Insulator-Metal) capacitors without shield (the capacitance of per unit area) and hexagonal spiral inductors (the Q-value is below 18) are used in this work. Because the inductance of Ls1 is small, it is wholly replaced by a transmission line, and the inductance is 0.43nH, as shown in Fig. 2.4.2. The poly without silicide resistance is used for gate bias. Guard-rings are added with all elements to prevent substrate noise and interference. A shielded signal GSG pad structure is used in RF input and RF output to reduce the coupling noise from the noisy substrate. As for the connection lines, the power lines are considered for the current density while the signal lines are designed as short as possible. All interconnections between elements are taken as a 45° corner. The RF input and the RF output are placed on opposite sides of the layout to avoid the signals coupling. The chip size is 0.86 mm x 0.9 mm.
Fig. 2.4.2 The electromagnetic simulation and the inductance of Ls1
2.4.2 Measurement considerations
The UWB LNA is designed for on-wafer measurement so the layout must follow the rules of CIC’s (Chip Implementation Center’s) probe station testing rules. This circuit needs one 3-pin DC PGP probe, one 6-pin DC PGP probe and two RF GSG probes for on-wafer measurement. Fig. 2.4.3 shows the on-wafer measurement setup with four probes. The top and bottom probes are DC PGP probes which provide the power supply voltage and bias voltage for the circuit. The left and right probes are RF GSG probes.
A large coupling capacitor is needed in the input of the UWB LNA to isolate the dc between circuit and equipment. Fig. 2.4.4 is the picture of the on-wafer measurement setup with four probes. Fig. 2.4.5 ~ Fig. 2.4.7 show the measurement setup for S-parameters, noise figure, 1dB compression point and third-order intercept point. We use the RF IC measurement system powered by LabView to measure the linearity of the UWB LNA. We will discuss the experimental and testing resultsof this circuit in following sections.
Fig. 2.4.3 On-wafer measurement test diagram
Fig. 2.4.4 Picture of on wafer measurement setup with four probes