Binary 8448MHz Voltage-Controlled Oscillator (VCO)

Voltage-Controlled Oscillator (VCO) plays an important role in communication systems because the phase noise of the VCO determines the out-of-band noise of the frequency synthesizer. An oscillator can generate various frequencies for up/down conversion in communication transceivers. In order not to distort the received signals, the excellent noise performance of VCO is required. The design of VCO becomes even more challenging in RF applications, where stringent requirements of phase noise and power consumption remain as the toughest tasks that RFIC engineers have to deal with.

There are two kinds of CMOS RFIC oscillators in common use: One is LC-tank oscillator and the other is resonatorless oscillator. The later has not been popular in RF design. This is

passive devices in the signal path. For example, in a three-stage differential ring oscillator, the open-loop Q is approximately equal to 1.3 [8], and nine transistors (including the tail current sources) and six load resistors add noise to the carrier. Hence, we adopt the LC-tank architecture.

An LC-tank oscillator is a feedback network with an LC-tank as the feedback circuit [24], as shown in Fig. 3.2.1. In this oscillator model, a noiseless load resistor Rp is present, so we want to provide energy replenished by a transconductor gm. The idea is that an active network generates impedance equal to -Rp so that this feedback system allow steady oscillation [25].

The oscillator frequency and gm value are:

p

Fig. 3.2.1 Behavioral model of an ideal LC oscillator

Fig. 3.2.2 shows the CMOS LC-tank VCO architecture. It contains an LC-Resonator with negative-gm cross-coupled pairs of MOS transistors as active part. The architecture of cross-coupled pairs adopts both NMOS and PMOS transistors (M1, M2, M3, M4) to enhance negative conductance, besides, only one inductor is paralleled with varactors to build the LC-resonator, instead of two inductors paralleled to signal ground. Such architecture can save large chip area. The complementary architecture mentioned above also provides several excellences over conventional structure only adopt NMOS or PMOS to be -gm cell.

Fig. 3.2.2 Voltage controlled oscillator structure

For low power consideration, the bias voltage of current source should be chosen carefully.

The Vgs-Vt and the gm of MOS in cross-coupled pair must be chosen correctly in order to achieve a good compromise between power consumption, phase noise and tuning range. A low value of Vgs-Vt gives a good transconductance-to-current ratio and hence low power consumption, but results in large transistor and small tuning range. From [25], the required negative transconductance GM of MOS in negative transconductance cell must then be at least equal to

(

)

G_M R^eff

= ω (3-3)

where Reff means the effective resistance of the LC tank in the equation above. The safety factor in the transconductance value must be large enough to ensure proper start-up of the oscillator, and is chosen to be 2.5. In order words, gm value equals to 2.5 times of GM. The total current consumption is

( )

The PMOS transistors are approximately three times larger than the NMOS transistors.

Assume the oscillation amplitude is VA. The expected phase noise at ∆f kHz offset then equals to

{ } ^{( )}

The parameter “A” is defined to be the negative transconductance cell noise contribution factor and usually no less than 1. Through the equations above, the bias voltage can be considered and tradeoff between low-power and low phase-noise is also taken.

A widely used figure of merit (FOM) [26] to compare VCO for both phase noise and power consumption is defined as:

( )

In Fig. 3.2.2, the capacitor bank architecture adopts a MOS as a varactor. When a control bit of capacitor bank is at low level, the MOS varactor has small capacitance. Otherwise, when a control bit is at high level, the MOS varactor has large capacitance. It can prevent not start-up oscillation while some damage of switch happened.

Fortunately, there are new RF models released from TSMC standard model library. The symmetric inductor is able to enhance the quality factor of LC-tank. The spiral inductor being used is shown with its layout (Fig. 3.2.3(a)) and equivalent lump circuit model (Fig. 3.2.3(b)) with radius=49μm, width=15μm, number of turns=3, and spacing=2μm. The total inductance is about 1.89nH. Using the MOS varactor (Blanch=17 and Group=1, as showing in Fig. 3.2.4), the oscillation frequency of this VCO is 8448 MHz.

(a) (b) Fig. 3.2.3 Spiral inductor in this synthesizer (a) layout (b) equivalent circuit model

(a) (b) Fig. 3.2.4 MOS varactor in this synthesizer (a) layout (b) equivalent circuit model

In addition, the tail transistor Mt must increase the width and the length of the PMOS tail transistor to further reduce the flicker noise which lowers significantly the close-in phase noise of the VCO in Fig. 3.2.2. The voltage swing across the resonator is proportional to tail-current Itail and the tank equivalent resistance Therefore, through the equations (3-3, 3-4) the tail-current value is optimized by the choice of Vbias1 to obtain a sufficient drain current for a large transconductance to ensure VCO’s startup while maintaining the thermal noise and power consumption diminished. A tail capacitor Ctail is used to attenuate both the high-frequency noise components of the tail current and the voltage variations on the tail node T. The effect results in more symmetric waveforms and smaller harmonic distortion in VCO outputs. This behavior is consistent with an improvement of the phase noise performances of