Chapter 1 Introduction
1.2 Thesis organization
We will discuss three circuits about LNA and mixer in this thesis. The chapter 2, chapter 3, and chapter 4 will introduce the proposed circuits. At first, we will make an introduction, present some previous researches, and indicate the advantages and drawbacks. Then we will propose the architecture and explain the circuit. The principles of the circuit and design considerations will be analyzed. The layout and measurement considerations will also be discussed. We will show the simulated and measured data and discuss the results. Finally, the performances will be listed in a table and compare with other literatures. The chapter 5 will make a conclusion and discuss the future work.
In chapter 2, a LNA with image-rejection (IR) function application for WLAN communication system will be expressed. The new design based on current-reused configuration will be presented. The principles of IR filter will be analyzed.
In chapter 3, a LNA for UWB system will be presented. By improving the resistive shunt feedback amplifier to current-reused amplifier, which stacking PMOS and NMOS, the input impedance can match to 50Ω over wide bandwidth and the gain will not reduce owing to the enhancement of transconductance. The details will be explained in chapter 3.
Chapter 4 will introduce a mixer for UWB system. The mixer adopts some techniques to improve the linearity, and it can achieve wideband input matching without the use of inductor. For UWB application, the mixer is also designed for low power operation.
Chapter 2
Design of LNA with Image-Rejection Function for WLAN system
2.1 Introduction
The growing WLAN has generated increasing interest in technologies that will enable higher data rates and capacity than initially deployed systems. The 802.11a standard (5-6 GHz), released by IEEE in 1999, is based on OFDM modulation technology with data rates up to 54 Mbps in the 5 GHz band.
For RF integrated circuits wireless receivers, the need for low-power and low-cost systems demands the use of CMOS technology to arrive in a single chip solution.
Heterodyne and homodyne are two major widely used receiver architectures in modern handsets. Each of the architectures has its own advantages and drawbacks. Homodyne architecture receiver, for instance, has higher level of integration due to its image-free architecture, but the DC offsets issues are the problems. By contrast, heterodyne architecture translate RF signal to IF through the mixer will deal with problem of image.
The RF and image bands symmetrically located above and below the local-frequency (LO) are down-converted to the same center frequency. The most common method to suppress the image is to use IR filter. However, the IR filter usually is an external component, such as surface-acoustic wave filters. These kinds of filters are often expensive and large that increase power consumption and costs, thus not suitable for integration. For this purpose, the researches of LNA with IR technique have developed and improved RF level of integration. The most widely adopted approach in the IR LNA is to exploits the notch filter implemented in the signal path of cascode LNA
circuit, which provides the lowest peak of input impedance at image frequency, thus the image signal will be connected to ground. Some reported analysis will be discussed.
2.2 Numerous topology of IR LNA
The on-chip IR LNA with second-order active filter is first introduced in [1]. The second-order active filter is illustrated in Fig. 2.1. The input impedance of IR filter, Zin is given by where Cgs1 is the gate-to-source parasitic capacitance, gm1 is transconductance, rg1 is the gate parasitic resistance, and r1 is the parasitic resistance of the inductor. The image frequency is designed at the resonant frequency fimage of the L1 and (1/Cgs+1/C1).
Note that in (1), the third term on the right-hand side is negative, thus the real part can be decreased to enhance the quality factor Q. The drawback is that Zin might be lower at wanted frequency, which leads to the degradation of the gain.
C1
L1
M1
Zin
Fig. 2.1. The IR LNA with the second-order active notch filter.
The third-order passive notch filter noted in Fig. 2.2 is introduced in [2]. The input impedance of IR filter Zin is derived as
( )
The RF and image frequency are located at
( )
1 1 The IR filter can provides low impedance and high impedance at image frequency and RF frequency, respectively. Thus the gain will not degrade due to the parasitic capacitance. However the quality factor Q of the on-chip inductor is comparatively low, so that the peak is not sufficient deep.Fig. 2.2. The IR LNA with the third-order passive notch filter.
In Fig. 2.3, the improved approach of previous researches is described as followed [3]. It exploits the third-order active notch filter implemented in the signal path of cascode LNA circuit. The input impedance of the IR filter, RF frequency, and image frequency can be expressed as
1 1
where Cgs1 is the gate-to-source parasitic capacitance, gm1 is transconductance, rg1 is the gate parasitic resistance, and rf is the parasitic resistance of the inductor.
Because Zin has negative resistance, the quality factor is unaffected by relatively low quality factor of the on-chip inductor. At image frequency fimage, Zin is reduced to zero, whereas at RF frequency, Zin is maximized. The loss of RF signal can be avoid.
However, the active filter will contribute extra power and noise. In addition, stack of three stages transistors in this design needs higher supply voltage (3V).
Fig. 2.3. The IR LNA with the third-order active notch filter.
Another research like Fig. 2.4 presents the LNA with the 4th-order T structure filter in [4] and Fig. 2.5 shows the LNA with the active filter in [5]. In Fig. 2.4, the current transfer function of the T structure filter and the image frequency can be express as The current transfer function has the zero frequency at fimage, which filters out image signal because iRF can’t pass the filter to M2 stage. But it still have no technique to increase quality factor and the RF signal will be degraded by the T-structure filter.
All approaches of above discussed researches implement IR filter into the inter-stage of a cascode LNA.
Fig. 2.4. The IR LNA with the forth-order T structure filter.
Fig. 2.5. The IR LNA with active filter.
This work presents a new design which improves current-reused technique by adding a LC tank in inter-stage to achieve simultaneously IR function and lower power dissipation than [3-5].
2.3 Conventional current-reused amplifier
Fig. 2.6 illustrates an amplifier topology called current-reused. The bias circuits of two NMOS transistors are not shown in the diagram. In this circuit, the source of upper transistor is bypassed to ground, thus both transistors operate as common-source stage, while they share the same bias current. The signal amplified by lower transistor is coupled to the gate of upper transistor by inter-stage capacitor. Two inductors as two loads of transistors have high impedance at RF frequency, so that the signal can be amplified twice. The usage of inductor instead of resistor is because the DC current leads to no voltage drop, the supply voltage can be reduced. This circuit can save power through the reuse of the bias current and obtain high gain performance.
Fig. 2.6. Conventional current-reused amplifier.
2.4 Architecture
The schematic diagram of the proposed LNA is shown in Fig. 2.7. Cbs is bypass capacitor like short in AC. The circuit uses supply voltage (VDD) of 1V and bias voltage (Vbias) of 0.7V. Gate bias resistor, Rbias, is large value (21 kΩ) to isolate voltage sources from RF signal path and block noise from voltage source. Ls and Lg
are for input matching. Cin is DC blocking capacitor. The inter-stage is composed of L1, L2, C1, and C2. Ld and Cout are for output matching. Supply voltage VDD connects a bypass capacitor (10pF) to ground, which ensure VDD working like ground in AC. The circuit topology uses current-reused technique, that M1 and M2 transistors are stack like common source and use the same bias current, therefore, the total power consumption is minimized.
Fig. 2.7. Circuit schematic of the proposed IR LNA.
2.5 Design considerations
2.5.1 Input matching analysis
The proposed LNA is used to match to 50Ω, its small signal equivalent circuit of input stage is shown in Fig. 2.8, where Ls is effective inductance of M1 source to ground; Cgs is the gate-to-source parasitic capacitance and the gate-to-drain parasitic capacitance is ignored to simplify the process; ro is the channel length modulation resistor of M1. Zout1 is output impedance of M1. To achieve input impedance matching, only small Ls value is required. This Ls value is done by layout a small transmission line at M1 source connected to ground, instead of using spiral inductor component, so
that area and cost can be saved. Note that Ls value is designed and optimized by an electromagnetic simulation tool. The input impedance can be derive as
1 1 real part of Zin and shift the resonant frequency. Therefore, the choices of device values will be careful to optimize the circuit design.
ν
gsm gs
g ⋅ ν
Fig. 2.8. The small signal equivalent circuit of input stage of the proposed LNA.
2.5.2 Image-rejection filter analysis
The IR filter is shown in Fig. 2.9, where Cin2 is gate parasitic capacitance of M2. The LC tank, including L1 and C1, provides the highest dip of impedance at resonating frequency to reject image at signal path.
Fig. 2.9. Schematic of the IR filter.
The voltage ratio of node X to node Y can be derived as
2
Equation (2-4) can be re-written as
2
From equation (2-5), the image and RF signals can be located at
1 1 close to fRF. For fimage > fRF, the image frequency must be designed slightly higher than RF frequency.
Here, we consider the quality factor Q of the proposed IR filter. Fig. 2.10 shows
the small signal equivalent circuit looking into the gate of M2. Transistor M2 not only plays an amplified role, but also be exploited to achieve sufficient quality factor. The analysis ignored L2 due to its high impedance at high frequency.
ν
gs2m2 gs2
g ⋅
ν
Fig. 2.10. The small signal equivalent circuit looking into the gate of M2. Where Cgs2 is the gate-to-source parasitic capacitance, and rg2 is the series gate parasitic resistance. The input impedance can be derived as
2 2 2 Because the quality factor usually is dominated by resistance of the filter, we only discuss the real part. In (10) the second term on the right-hand side is negative resistance proportional to gm2, by adjusting M2 size, sufficient negative resistance can be generated to cancel out rg2 and parasitic resistance of on-chip inductor L1. Therefore, the quality factor of the IR filter will be increased to high value. Note that the analysis of input impedance has to include L2 at low frequency.
To verify IR ability of the filter, the simulation result of Av is shown in Fig. 2.11.
The RF signal at 5.8 GHz passes through the filter and image signal at 6.9 GHz is filtered out. The passive IR filter, which only requires simple circuit and exploits parasitic capacitance of M2, is implemented at inter-stage and consumes no additional power and noise compared with active filter. From (2-5), Av should be 0 dB at high
frequency and low frequency, but the simulated result is not coincident. It is because the parasitic resistances within the transmission line, the signal will be lost from node Y to node X.
In addition, the filter is also used as the inter-stage matching. Fig. 2.12 shows that at node Y, the simulated reflection coefficients Γ1 and Γ2 are approximately complex conjugate matching from simulation result to achieve maximum power transformation.
1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
-30 -25 -20 -15 -10 -5 0 5
Av (dB)
Fig. 2.11. Simulation result of Av =X Y/ in Fig. 2.7.
Fig. 2.12. Simulation result of the inter-stage matching.
2.6 Chip implementation and measured results
2.6.1 Measurement considerations
The proposed LNA for WLAN has been designed based on TSMC 0.18µm mixed-signal/RF CMOS 1P6M technology and for on-wafer measurement by Chip Implementation Center (CIC). The layout follows CIC’s probe station testing rules.
This circuit requires two 3-pin DC probes on upper and lower side and two RF GSG probes for RF signal on left and right side as shown in Fig. 2.13.
RFin RFout
DC DC
Fig. 2.13. On-wafer measurement of proposed IR LNA
The layout and chip photo of proposed LNA are shown in Fig. 2.14 and Fig. 2.15, respectively. The chip size is 0.75 mm × 0.93 mm including the probing pads.
Fig. 2.14. Layout of the proposed LNA.
Fig. 2.15. Micrograph of the proposed LNA.
The measurement setups for each parameter are shown in Fig. 2.16(a-d). We needs measured instruments including network analyzer, noise analyzer, spectrum analyzer, two signal generators, and two dc power supplies in CIC radio-frequency measurement environment.
(a)
(b)
(c)
(d)
Fig. 2.16. Measurement setups for (a) S-parameter. (b) noise figure. (c) P1dB. (d) IIP3.
2.6.2 Measured Results and discussion
The circuit operates at supply voltage of 1 V, and consumes 6.1mW power. The S-parameter is shown in Fig. 2.17-2.20. The measured results shows that the proposed LNA at 5.9 GHz exhibits 15.2 dB power gain (S21), better than -15 dB input and output return loss, better than -30 isolation, and -27 IR at 7.3 GHz. The simulated and measured operation frequency are at 5.8 GHz and 5.9 GHz, respectively, thus the operation frequency shifts 0.1 GHz. In addition, image frequency shifts 0.5 GHz from simulated 6.8 GHz to measured 7.3 GHz. This phenomenon is probably because the process variation and the simulated models of inductors are inaccurate. From (2-14) and (2-15), L1 determining the location of fRF and fimage, is comparatively large size so as to easily be influenced by variation, thus L1 is the most important component and must be carefully designed. In Fig. 2.17, we can observe that the lowest dip frequency
of measured output return loss is the same as simulated. The output impedance matching is determined by Ld, which is comparatively small to defy variation. Fig.
2.21 shows the simulated and measured noise figure (NF), which both are similar before 5.9 GHz. After 5.9 GHz, simulated and measured NF are different and have the highest peaks located at each image frequency. The measured NF is 3.2 dB at 5.9 GHz. The linearity including input-referred third-order intercept point (IIP3) and input 1 dB compression point (P1dB) are shown in Fig. 2.22-2.24. It shows the measured P1dB of -19.5 dBm and the measured IIP3 of -9.5 dBm similar to the simulated results. The performance summary of the proposed IR LNA is listed in table 2.1.
1 2 3 4 5 6 7 8 9 10
Fig. 2.17. Measured and simulated gain (S21).
1 2 3 4 5 6 7 8 9 10
Fig. 2.18. Measured and simulated input return loss (S11).
Fig. 2.19. Measured and simulated output return loss (S22).
1 2 3 4 5 6 7 8 9 10
Frequency (GHz)
-70 -65 -60 -55 -50 -45 -40 -35 -30 -25
(dB)
Simulation S12 Measurement S12
Fig. 2.20. Measured and simulated isolation (S12).
3 4 5 6 7 8 9 10 11
Fig. 2.21. Measured and simulated noise figure (NF).
-50 -45 -40 -35 -30 -25 -20 -15 -10
RF Input Power (dBm)
9
Fig. 2.22. Measured and simulated P1dB.
-40 -35 -30 -25 -20 -15 -10 -5 0
Fig. 2.23. Simulated IIP3.
-40 -35 -30 -25 -20 -15 -10 -5 0
Fig. 2.24. Measured IIP3.
Table 2.1
Performance summary of the proposed IR LNA
Specification Measurement Post Simulation
Operation Frequency
(GHz) 5.9 5.8
Image Frequency 7.3 6.8
Input Return Loss (dB) -16.4 -16.5
Output Return Loss (dB) -15 -27
Gain (dB) 15.2 15.1
Image Rejection (dB) -27 -15
Isolation (dB) -30.3 -35.7
P1dB (dBm) -19.5 -18.9
IIP3 (dBm) -9.5 -9.4
Noise Figure (dB) 3.2 3.1
Vdd (V) 1 V 1 V
Total LNA Power (mW) 6.1 5.9
2.6.3 Comparison with other literatures
The performances of the proposed IR LNA are listed and compared with other works shown in Table 2.2. It reveals that this work has the lowest power comsumption and supply voltage due to the current-reused configuration. The proposed LNA also has good IR capability compared with [3]. Although [4] and [5]
shows the better performance of IR, it is only simulated results. It is difficult to filter
out the unwanted signal with a deep peak due to the low quality factor Q of the on-chip component. The performances of the proposed LNA satisfy the system specification and chip size is comparatively small.
Table 2.2
Comparison of the IR LNA performances S11
Chapter 3
Design of Current-Reused LNA for UWB
3.1 Introduction
The requirement for high-speed wireless communication systems has increased significantly during the last few years. The FCC has allocated 7500-MHz bandwidth in the 3.1–10.6 GHz frequency range (low-frequency band: 3.1–5 GHz;
4high-frequency band: 6–10.6 GHz) for UWB application. The UWB technology, including the IEEE 802.15 standard, is considered as an attracted wireless interface because of its potential to provide high data rate, low power consumption, and low cost. The UWB communication is allowed very low average transmit power compared with more conventional systems for short range and high rate connectivity, that can be applied to Wireless Personal Area Network (WPAN).
The design of the front-end LNA is one of the challenges in the RF receivers.
LNA’s purpose is to amplify the received signal from the antenna with as weak signal and additional noise as possible. Because it is a first building block in the RF receiver, its performance dominates the sensitivity of the overall system. Hence, for the achievement of high receiver sensitivity, the LNA is required to have a low noise figure with good matching network between the antenna and the LNA as well as sufficient gain with flatness in the wide frequency range of operation.
3.2 Numerous topology of wideband LNA
The amplifiers that can provide 50 Ω input impedance over a wide bandwidth are the challenge. Some researches about wideband amplifier will be discussed as follow.
Fig. 3.1 shows resistor-terminated common-source amplifier, common-gate amplifier, and resistive shunt-feedback amplifier .
Fig. 3.1. Conventional wideband configurations. (a) Resistor-terminated common-source amplifier. (b) Common-gate amplifier. (c) Resistive shunt-feedback amplifier.
The three configurations of amplifiers all can achieve 50 Ω wideband input matching, however, they have some drawbacks. In Fig. 3.1(a), The Resistor-terminated common-source amplifier achieves wideband matching by setting RT equal to 50 Ω, but it loses a lot of voltage due to the loading effect, the voltage gain will decrease. In Fig. 3.1(b), the CG amplifier has small input resistance of 1/gm
to achieve wideband input matching, however it is noisier than common-source amplifier. The noise figure can be improved by increasing gm, but the input matching will be difficult to obtain over wide bandwidth. In Fig. 3.1(c), an alternate approach for wideband amplifier is the resistive shunt-feedback amplifier. It exploits negative feedback method to get lower input impedance, more stability, but lower voltage gain, so that noise of next stages won’t be suppressed due to gain degradation.
Fig. 3.2 shows the distributed amplifier that can provide wide band matching by several stages, and relatively flat gain over 3.1-10.6 GHz UWB band can be achieve in recent research [6]. However, the drawback is large power consumption due to multiple transistors stages, and the usage of much inductors occupies large die area, which make them unsuitable for integration. In addition, the research shows the distributed amplifier cannot achieve sufficient gain compared with other configurations.
Fig. 3.2. Conventional distributed amplifier.
In recent research, a wideband input matching approach has been presented.
Fig. 3.3 is the simple small signal equivalent circuit of common-source amplifier with inductive source degeneration, and load resistance and capacitance at the drain of transistor are shown in the diagram. The input impedance depends on resistive load and capacitive load at high frequency and low frequency, respectively. The wideband impedance matching and noise matching can be achieved without extra matching network [7].
Fig. 3.3. The small signal equivalent circuit of CS amplifier with inductive source degeneration.
Here, this work is designed based on resistive shunt-feedback amplifier. To improve gain performance, the current-reused technique will be adopted to enhance gm. The traditional current-reused amplifier [8] is expressed in Fig. 3.4.
V
inV
outFig. 3.4. Current-reused amplifier.
3.3 Architecture
The proposed UWB LNA employs three stages as shown in Fig. 3.5. This circuit is designed to require two bias voltage sources of 1.5 V (Vdd) and 0.7 V (Vbias).The first input stage including M1n and M1p is current-reused configuration. It can achieve wideband matching and no degradation of the gain. The second stage M is