Chapter 3 Design of Current-Reused LNA for UWB
3.2 Numerous topology of wideband LNA
3.5.3 Measured and simulated results
The proposed LNA for UWB system has been fabricated on TSMC 0.18 µm mixed-signal/RF CMOS 1P6M technology with chip size of 0.949 x 0.912 mm2. The total power consumption is 14.4 mW with bias voltage source 1.5 V and 0.7 V. The S-parameter are shown in Fig. 3.13-3.16. The input return loss (S11) in Fig. 3.13 shows the measured S11 lower than -10 dB, which degrades about maximum 2 dB compared with simulated result at 7 GHz. Fig. 3.14 indicates the measured and simulated output return loss (S22). The measured S22 is lower than -17 dB and the experimental result reveals measured S22 is better than simulated S22. The gain (S21) is an important parameter of a LNA. The measured S21 degrades about 2 dB and 1 dB at low frequency and high frequency than simulated S21, respectively. The measured S21 in 3.1-10.6 frequency band is 11.9 dB to 16.4 dB, which is not flat in UWB band.
The noise figure (NF) performance is shown in Fig. 3.17. The measured NF has maximum 5.28 dB and minimum 3.33 dB, which is higher than simulated NF perhaps due to the inaccurate noise model and post-simulation. The input-referred 1dB compression point (P1dB) are shown in Fig. 3.18(a-e). The measured P1dB are -18.3 dBm at 3.1 GHz, -18.5 dBm at 4.9 GHz, -18.5 dBm at 6.8 GHz, -15.6 dBm at 8.7 GHz, and -11.7 dBm at 10.6 GHz. The input-referred third-order intercept point (IIP3) at five frequency points are shown in Fig. 3.19(a-e). The measured IIP3 shows -8.2 dBm at 3.1GHz, -9.5 dBm at 4.9 GHz, -9 Bm at 6.8 GHz, -2.6 dBm at 8.7 GHz, and 0 dBm at 10.6 GHz. The performance summary is listed in table 3.1.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.13. Measured and simulated results of S11.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.14. Measured and simulated results of S22.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.15. Measured and simulated results of S21.
2 4 6 8 10 12
Fig. 3.16. Measured and simulated results of S12.
2 3 4 5 6 7 8 9 10 11 12
Frequency (GHz)
2 3 4 5 6 7
NF (dB)
Measurement Simulation
Fig. 3.17. Measured and simulated results of noise figure.
-30 -25 -20 -15 -10
-30 -25 -20 -15 -10
Fig. 3.18. Measured and simulated results of P1dB at (a) 3.1 GHz. (b) 4.9 GHz. (c) 6.8GHz. (d) 8.7 GHz. (e) 10.6 GHz.
-40 -35 -30 -25 -20 -15 -10 -5
Measured IIP3 @ 3.1GHz
(a)
Measured IIP3 @ 4.9GHz
(b)
Measured IIP3 @ 6.8GHz
(c)
-40 -35 -30 -25 -20 -15 -10 -5 0
Measured IIP3 @ 8.7GHz
(d)
Measured IIP3 @ 10.6GHz
(e)
Fig. 3.19. Measured result of IIP3 at (a) 3.1 GHz. (b) 4.9 GHz. (c) 6.8GHz. (d) 8.7 GHz.
(e) 10.6 GHz.
Table 3.1
Performance summary of the proposed LNA
Specification Measurement Post Simulation
Input Return Loss (dB) -16.8~-10.6 -19.8~-14.1
Output Return Loss (dB) -58~-16.7 -21.4~-13.6
Gain (dB) 14.1± 2.3 14.75 ± 1.85
Isolation (dB) -64.6~-40 -73.8~-36.8
P1dB (dBm) -18.7~-11.7 -20.2~-13.7
IIP3 (dBm) -9.5~0 -12.5~-3.5
Noise Figure (dB) 3.3~5.3 2.7~3.8
Vdd (V) 1.5 V 1.5 V
Total LNA Power (mW) 14.4 11.6
3.5.4 Comparison with other literatures
The performances of the proposed UWB LNA are compared with other works for UWB band listed in Table 3.2. This work has the smallest ratio of average gain to power approximately equal to 1. It reveals that the current-reused configuration can efficiently enhance the gain performance. In 3.1-10.6 GHz, the proposed LNA exhibits average gain of 14.1 dB while consumes 14.4 mW power. The NF of the proposed LNA also has better performance at lower frequency than other works based on CMOS 0.18 um process. In addition, no buffer is required in this design, however, table 3.2 shows that this work has the best output return loss, which is lower than -16.7 dB over UWB band.
Table 3.2
Comparison of Ultra Wide-band LNA
Ref. Process
Chapter 4
Design of Low-Power High-Linearity Inductorless Mixer for UWB
4.1 Introduction
RF CMOS technology is developed to achieve higher frequency and wider bandwidth application. Large-scale availability of CMOS allows devices to be manufactured at a much lower cost as compared with devices that depend on non-silicon technologies. The UWB communication system over 3.1 GHz to 10.6 GHz frequency band will be widely used in the short distance WPAN, providing high data rates to a large number of users over large area.
In the chain of down-conversion UWB receiver, the mixer plays a key role to shift RF signal to IF. The researches of wideband matching for the mixer have developed. For example, the matching network for the mixer can employ distributed network [14] and LC ladder network [15] as shown in Fig. 4.1 and Fig. 4.2, respectively. However, both methods require inductors that occupy large die area that is unsuitable for integration.
Fig. 4.1 The mixer using the distributed matching network.
Fig. 4.2. The mixer using the LC ladder matching network.
High linearity receiver is essential for high data rate communication system. The second stage should consider the linearity performance because the last stage is a prominent contributor to degrade the linearity. For a cascaded amplifier, the total input-referred third-order intercept point (IIP3total) can be expressed as
2 2 2
1 2 3
1 1
3total 3 3 3 .
IIP IIP IIP IIP
α α β
≅ + + +" (4-1) where α and β are the linear gain for the first and second stages, respectively. From
(4-1), we can observe that the IIP3 of the last stage significantly affects the total IIP3.
In addition, because LNA usually designed for high gain to suppress the noise of next stage, it is difficult to maintain comparatively better linearity. In general, the linearity of the receiver is dominated by a mixer. The linearity performance requirement becomes more significant in modern RF mixer for improvement of the receiver dynamic range and immunity to the various interferer signals from other communication standards.
In this work, a low-power, high-linearity wideband down-conversion mixer without the use of inductors is designed and implemented using TSMC 0.18 µm CMOS process. The circuit will be analyzed and discussed.
4.2 Architecture
In Fig. 4.3, the proposed mixer is based on Gilbert-cell topology, which is double balance mixer to suppress LO-to-IF feed though compared to single balance mixer.
Three voltage sources (VDD=1.8 V, VB=0.77 V, VS=0.63 V) are used in the circuit. The bias voltage, VB, at switching stage is not shown in the diagram. The transistors of switching stage with small W/L are sufficiently fast to steer the RF current from transconductance stage to switching stage. The gate-to-source voltage (Vgs) is set near threshold voltage (Vt) for completely current commutation. The differential output employs the buffer to provide 50 Ω output impedance for on-wafer measured requirement. In this work, some techniques will be exploited to improve linearity of the mixer.
Fig. 4.3. Schematic of the proposed mixer.
4.3 Design considerations
4.3.1 Common-gate transconductance stage with source resistor
The proposed mixer employs common-gate (CG) amplifier as transconductance stage. The CG configuration adding a source resistor can improve linearity. To observe this phenomenon, we derived the voltage gain (AV) of CG amplifier as
= +In2 1.
V
S In
A R
R R (4-2)
where In1≅ 1 .
m
R g (4-3)
and RIn2 is second stage input resistance. From (4-2), additional source resistor RS will
stabilize the voltage gain throughout operation. If the transconductance value gm
varies, the operation point will not vary as much. Therefore, CG amplifier with source resistor can maintain stability of operation point against variation in transistor parameters. However, the trade-off is that the voltage gain will degrade because of source resistor.
The CG configuration also has wide bandwidth to achieve better linearity compared to common-source (CS) configuration. The high-frequency response of CG amplifier is shown in Fig. 4.4, where CIn2 is second stage input capacitance. For simplicity, channel length modulation is negligible because RIn2 is relatively small. In such case, there are two poles given by
( )
The frequency response can be derived as
( )
= + 2(
+ ω 1)(
+ ω 2)
Fig. 4.4. CG amplifier.
Besides, in Fig. 4.5, CS amplifier also has two poles obtained as If CS voltage gain is enough large, ωP1 will dominate the high-frequency response due to Miller effect. Therefore, the voltage gain of CS configuration begins to decay at lower frequency. Here, although RIn2 is relatively small, which reduces the gain, the CG bandwidth is still better than CS bandwidth.
In general, 50 Ω input matching is difficult for CS stage due to its large input resistance. For this purpose, matching network including inductors is required.
However, inductors are usually large so that impedes the level of integration. In this work, CG configuration provides excellent input-matching over wide bandwidth by setting RS+1/gm ≅50 Ω, which is suitable for UWB application.
Fig. 4.5. CS amplifier.
4.3.2 Current-Injection Technique
For Gilbert-cell mixer, the conversion gain and IP3 are expressed as
2 . Both the conversion gain and the input third-order intercept point (IIP3) are proportional to the square root of the bias current. However, the consequence of increasing bias current will increase the voltage dropped across load resistor. Thus the mixer remains less voltage headroom to degrade the linearity. One method to deal with this problem is current-injection technique [16]. It can be achieved by injecting the required additional bias current into the drain of the transconductance stage MOSFETs to reduce the bias current in the switching stage. The small bias current in the switching stage also allows the usage of large load resistor without consuming large voltage drop from the limited headroom. However, current source will contribute to the mixer noise.
Because flicker noise of the switching stage is only present at the switching instant of the LO differential pairs, we can inject a dynamic current equal to bias current at only the switching event. The dynamic current-injection technique [17] is shown in Fig. 4.6, where MP1 and MP2 are switching pairs to control when current source (MP3) injects to the transconductance stage. Using this technique can improve the flicker noise and minimize the bias current in the switching stage. In this design, only 350 µA current flows through each load resistor. In addition, because the bias currents of the load stage are much small, the usage of resistors as load is more suitable than active load. The reason is that the voltage drop can be small, while the source-to-drain voltage drop of PMOS active load may be lager.
Fig. 4.6. Dynamic current-injection technique.
4.4 Chip implementation and measured results
4.4.1 Measured considerations
The proposed fully integrated mixer is fabricated in TSMC 0.18 µm CMOS technology and for on-wafer measurement. Fig. 4.7 and Fig. 4.8 show the chip layout and micrograph with a chip size of 0.84 x 0.72 mm2 including pads. According to the testing rules of the measured environment, pad-to-pad must have limited minimum distance to prevent a knock of the probes. Therefore, the layout area of the designed mixer with pads can’t be reduced. For actual application, the UWB mixer can achieve smaller size. The layout uses bottom ground metal under important signal path to shield off noise from substrate. The circuit operates at supply voltage of 1.8 V, and the core mixer consumes 4.68 mW power. The on-chip bypass capacitors is included between each voltage source and ground in the circuit.
Fig. 4.7. Layout of the proposed mixer.
Fig. 4.8. Micrograph of the proposed mixer.
The proposed mixer for ultra-wideband application is designed for on-wafer measurement. The layout follows the CIC probe station testing rules. Fig. 4.9 expresses the arrangements of the probes. The proposed mixer is designed to require three RF GSGSG probes for differential signals and a 6-pin DC probe. All probes are pitch 100 µm for saving area. The RF port, LO port, and IF port all need external balun and DC block capacitors for measured purpose.
Fig. 4.9. On-wafer measurement of UWB LNA test diagram.
The measurement setup for RF port and IF port return loss, conversion gain, P1dB, IIP3, and noise figure is shown in Fig. 4.10(a-d). The required equipments include a network analyzer, a spectrum analyzer, a noise analyzer, three signal generators, and a DC power supply.
(a)
Balun Balun
Balun
Spectrum Analyzer Signal
Generator
Signal Generator
(b)
(c)
Balun Balun
(d)
Fig. 4.10. Measurement setup of the proposed mixer for (a) RF port and IF port return loss. (b) conversion gain and P1dB. (c) IIP3. (d) noise figure.
4.4.2 Measured Results and discussion
Fig. 4.11(a-c) shows the conversion gain versus the LO power to find what LO power could lead to maximum conversion gain. The measured result shows the LO power of -2.5 dBm can achieve maximum conversion gain in UWB band. The measured and simulated conversion gain of the proposed mixer versus RF frequency is shown in Fig. 4.12 with a fixed IF frequency of 100 MHz, RF power of -30 dBm, and LO power of -2.5 dBm. Fig. 4.13 shows the input RF port return loss, which the measured result achieves better than -11 dB over 3.1 to 10.6 GHz. It reveals that the proposed transconductance stage is suitable for matching of broad bandwidth. The measured output IF port return loss is -26 dB at 100 MHz due to the usage of the buffers for measured requirement. Fig. 4.14(a-c) shows the measured and simulated P1dB at RF frequency of 3.1 GHz, 6.6 GHz, and 10.6 GHz. The measured IIP3 at RF frequency are illustrated in Fig. 4.15. Fig. 4.16 shows the measured and simulated IIP3 versus RF frequency with a fixed IF frequency of 100 MHz and LO power of -2.5 dBm. The Measured and simulated double-sideband noise figure (DSB NF) from 3.1 to 10.6 GHz as shown in Fig. 4.17. The measured DSB NF is worst compared with simulated result about 4 dB. The mixer isolation are shown in Fig 4.18 and Fig.
4.19. The measured LO-to-RF isolation is better than 59 dB over the operation frequency due to the excellent isolation of CG configuration. The RF-to-IF isolation also has better than 31 dB performance. The performance summary is listed in table 4.1. The proposed core mixer is suitable for low power operation, which only consumes 4.68 mW power from 1.8 supply voltage.
-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6
RF frequency of 3.1 GHz
(a)
RF frequency of 6.6 GHz
(b)
RF frequency of 10.6 GHz
(c)
Fig. 4.11. Measured conversion gain versus LO power at (a) RF frequency of 3.1 GHz.
(b) RF frequency of 6.6 GHz. (c) RF frequency of 10.6 GHz.
2 3 4 5 6 7 8 9 10 11
Fig. 4.12. Measured and Simulated Conversion Gain of the proposed mixer.
2 3 4 5 6 7 8 9 10 11 12
RF Port Return Loss (dB) Measurement Simulation
Fig. 4.13. Measured and simulated RF port return loss.
-30 -25 -20 -15 -10 -5 0 RF Input Power (dBm)
-4
RF Input Power (dBm) -5
RF Input Power (dBm) -8
Fig. 4.14. Measured and simulated P1dB at (a) RF frequency of 3.1 GHz. (b) RF frequency of 6.6 GHz. (c) RF frequency of 10.6 GHz.
-30 -25 -20 -15 -10 -5 0 5 10 RF Input Power (dBm)
-80
IF Output Power (dBm)
RF frequency of 3.1 GHz
-30 -25 -20 -15 -10 -5 0 5 10
RF Input Power (dBm) -80
IF Output Power (dBm)
RF frequency of 4.9 GHz
(a) (b)
-30 -25 -20 -15 -10 -5 0 5 10
RF Input Power (dBm) -80
IF Output Power (dBm)
RF frequency of 6.6 GHz
-30 -25 -20 -15 -10 -5 0 5 10
RF Input Power (dBm) -80
IF Output Power (dBm)
RF frequency of 8.6 GHz
(c) (d)
-30 -25 -20 -15 -10 -5 0 5 10
RF Input Power (dBm) -80
IF Output Power (dBm)
RF frequency of 10.6 GHz
(e)
Fig. 4.15. Measured IIP3 at (a) RF frequency of 3.1 GHz. (b) RF frequency of 4.9 GHz.
(c) RF frequency of 6.6 GHz. (d) RF frequency of 8.6 GHz. (e) RF frequency of 10.6 GHz.
2 3 4 5 6 7 8 9 10 11
Fig. 4.16. Measured and simulated IIP3 with a fixed IF frequency of 100 MHz and LO power of -2.5 dBm.
Fig. 4.17. Measured and simulated double sideband noise figure.
2 3 4 5 6 7 8 9 10 11
Fig. 4.18. RF-to-LO isolation.
2 3 4 5 6 7 8 9 10 11
Fig. 4.19. LO-to-RF isolation.
Table 4.1
Performance summary of the proposed mixer
Specification Measurement Post Simulation
RF Return Loss (dB) -11.4~-10.8 -11.4~-10.6
IF Return Loss (dB) -26 -20.3
Conversion Gain (dB) -0.7± 2.6 2.2 ± 0.9
DSB Noise Figure (dB) 14.3~19.6 13.3~15
P1dB (dBm) -6.5~-2.5 -5~-3
IIP3 (dBm) 3~8 5.6~7.8
RF-to-IF Isolation (dB) 31.2~53.5 47.1~48
LO-to-RF Isolation (dB) 59.1~62.5 66~76
VDD (V) 1.8 V 1.8 V
Core Mixer Power (mW) 4.68 4.3
4.4.3 Comparison with other literatures
The performances of the proposed UWB mixer are listed and compared with other works as shown in Table 4.2. The conversion gain of this work is worse than simulation and other works perhaps owning to transistor variation, thus the DSB NF also degrades about 4 dB at high frequency. The propose UWB mixer achieves better IIP3 than other works. It requires the smallest power of 4.68 mW, which is suitable for UWB low power application.
Table 4.2
Comparison of the UWB mixer
Ref. Process
Chapter 5
Conclusion and Future Work
5.1 Conclusion
This thesis contains three works: the low voltage low-noise amplifier with image-rejection function for WLAN system, the low-noise amplifier for UWB system, and the low-power high-linearity inductorless mixer for UWB system. These three circuits are fabricated in TSMC 0.18 um CMOS process supported by CIC. The design concepts and research results will be described as follow.
5.1.1 Design of LNA with IR function for WLAN system
This work presents a new design of the LNA with IR function by adding a simple parallel LC tank into the inter-stage of the current-reused structure to obtain satisfying performance and IR function. Comparing with other researches, no complex circuit is required in this design, thus it is easier to achieve for designers.
Due to the use of passive filter, there are no additional power and noise contribution than active filter. In general, on-chip inductor is usually considered as low quality factor, thus filter with on-chip inductors is difficult to achieve better performance.
Thus the Q enhancement technique is also adopted in the proposed LNA to successfully achieve better IR ability than [3] with active filter. In addition, all reported researches exploit cascode configuration and improve it by adding IR filter, while this work employs current-reused technique, which is suitable for low voltage, low power operation and obtains high gain. The proposed LNA only uses 1 V supply voltage to lower power consumption.
5.1.2 Design of current-reused LNA for UWB system
The input impedance matching of wideband LNA for matching 50 Ω to external antenna is a challenge. One of wideband impedance matching approach is resistive shunt feedback, which can reduce input resistance throughout resistor feedback due to Miller effect, but the drawback is degradation of gain. This work improves resistive shunt feedback by stacking PMOS and NMOS to enhance the transconductance, thus the gain can be increased. By adding gate inductor and source inductor, the high frequency input return loss can be improved. The measured results shows the proposed UWB LNA can achieve average gain of 14.1 dB while consumes 14.4 mW power.
5.1.3 Design of low-power high-linarity inductorless mixer for UWB system.
For conventional Gilbert-cell mixer, the use of common-source structure as transconductance stage requires input matching network for wideband application.
The matching network usually contains inductors, which occupies large die area. The proposed mixer exploits common-gate structure with source resistor as transconductance stage to achieve inductorless wideband input matching. Except for saving area, this design has wider bandwidth to achieve better linearity. The dynamic current-injection technique is also adopted to improve voltage headroom and no contribution of noise compared to traditional current-injection method. The measured results show the good IIP3 of 3 dBm to 8 dBm. The proposed mixer only consumes 4.68 mW power from 1.8 V supply voltage.
5.2 Future work
In this thesis, there are some directions that can be improved for the future. For the proposed LNA with IR function, the image frequency can be designed closer to the RF frequency, and the NF has potential to achieve better performance, For the proposed current-reused LNA, we can retune the component value in the LNA to flatten the gain. For the inductorless mixer, an object is to increase conversion gain and maintain high linearity at the same time. Because both LNA and mixer are application for UWB system, we can combine these two circuits to design a RF front-end.
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