Chapter 2 Design of LNA with Image-Rejection Function for WLAN system
2.6 Chip implementation and measured results
2.6.3 Comparison with other literatures
The performances of the proposed IR LNA are listed and compared with other works shown in Table 2.2. It reveals that this work has the lowest power comsumption and supply voltage due to the current-reused configuration. The proposed LNA also has good IR capability compared with [3]. Although [4] and [5]
shows the better performance of IR, it is only simulated results. It is difficult to filter
out the unwanted signal with a deep peak due to the low quality factor Q of the on-chip component. The performances of the proposed LNA satisfy the system specification and chip size is comparatively small.
Table 2.2
Comparison of the IR LNA performances S11
Chapter 3
Design of Current-Reused LNA for UWB
3.1 Introduction
The requirement for high-speed wireless communication systems has increased significantly during the last few years. The FCC has allocated 7500-MHz bandwidth in the 3.1–10.6 GHz frequency range (low-frequency band: 3.1–5 GHz;
4high-frequency band: 6–10.6 GHz) for UWB application. The UWB technology, including the IEEE 802.15 standard, is considered as an attracted wireless interface because of its potential to provide high data rate, low power consumption, and low cost. The UWB communication is allowed very low average transmit power compared with more conventional systems for short range and high rate connectivity, that can be applied to Wireless Personal Area Network (WPAN).
The design of the front-end LNA is one of the challenges in the RF receivers.
LNA’s purpose is to amplify the received signal from the antenna with as weak signal and additional noise as possible. Because it is a first building block in the RF receiver, its performance dominates the sensitivity of the overall system. Hence, for the achievement of high receiver sensitivity, the LNA is required to have a low noise figure with good matching network between the antenna and the LNA as well as sufficient gain with flatness in the wide frequency range of operation.
3.2 Numerous topology of wideband LNA
The amplifiers that can provide 50 Ω input impedance over a wide bandwidth are the challenge. Some researches about wideband amplifier will be discussed as follow.
Fig. 3.1 shows resistor-terminated common-source amplifier, common-gate amplifier, and resistive shunt-feedback amplifier .
Fig. 3.1. Conventional wideband configurations. (a) Resistor-terminated common-source amplifier. (b) Common-gate amplifier. (c) Resistive shunt-feedback amplifier.
The three configurations of amplifiers all can achieve 50 Ω wideband input matching, however, they have some drawbacks. In Fig. 3.1(a), The Resistor-terminated common-source amplifier achieves wideband matching by setting RT equal to 50 Ω, but it loses a lot of voltage due to the loading effect, the voltage gain will decrease. In Fig. 3.1(b), the CG amplifier has small input resistance of 1/gm
to achieve wideband input matching, however it is noisier than common-source amplifier. The noise figure can be improved by increasing gm, but the input matching will be difficult to obtain over wide bandwidth. In Fig. 3.1(c), an alternate approach for wideband amplifier is the resistive shunt-feedback amplifier. It exploits negative feedback method to get lower input impedance, more stability, but lower voltage gain, so that noise of next stages won’t be suppressed due to gain degradation.
Fig. 3.2 shows the distributed amplifier that can provide wide band matching by several stages, and relatively flat gain over 3.1-10.6 GHz UWB band can be achieve in recent research [6]. However, the drawback is large power consumption due to multiple transistors stages, and the usage of much inductors occupies large die area, which make them unsuitable for integration. In addition, the research shows the distributed amplifier cannot achieve sufficient gain compared with other configurations.
Fig. 3.2. Conventional distributed amplifier.
In recent research, a wideband input matching approach has been presented.
Fig. 3.3 is the simple small signal equivalent circuit of common-source amplifier with inductive source degeneration, and load resistance and capacitance at the drain of transistor are shown in the diagram. The input impedance depends on resistive load and capacitive load at high frequency and low frequency, respectively. The wideband impedance matching and noise matching can be achieved without extra matching network [7].
Fig. 3.3. The small signal equivalent circuit of CS amplifier with inductive source degeneration.
Here, this work is designed based on resistive shunt-feedback amplifier. To improve gain performance, the current-reused technique will be adopted to enhance gm. The traditional current-reused amplifier [8] is expressed in Fig. 3.4.
V
inV
outFig. 3.4. Current-reused amplifier.
3.3 Architecture
The proposed UWB LNA employs three stages as shown in Fig. 3.5. This circuit is designed to require two bias voltage sources of 1.5 V (Vdd) and 0.7 V (Vbias).The first input stage including M1n and M1p is current-reused configuration. It can achieve wideband matching and no degradation of the gain. The second stage M is
common-source which be used to enhance the gain. The output stage M3 is also common-source configuration. But its main object is to make output impedance match 50 Ω for measurement purpose. Each inter-stage places an on-chip bypass capacitor (3 pF) to avoid DC bias current flowing into the front stage. A large resistor (17 kΩ) is employed in each bias circuit to isolate noise of voltage source from internal circuit.
The function of Cg (1 pF) in input stage is to make the gate voltages of M1p and M1n
can be set different. M1n always operates at saturation region due to Rf feedback, whereas M1p can change its gate voltage due to Cg for fine tuning.
Fig. 3.5. Schematic of the proposed UWB LNA.
3.4 Design considerations
For resistive shunt-feedback amplifier in Fig. 3.1(c), because the transfer function has a dominant pole by Miller effect, the -3 dB bandwidth can be given by
( )
transistor. From (3-1), wider bandwidth can be obtained by higher |AV| and smaller RF. However, small RF leads to degradation of noise figure and gain. The better approach to enlarge bandwidth is increase of |AV|. For this purpose, this work improves resistive shunt-feedback amplifier to current-reused amplifier for enhancement of transconductance to obtain higher gain. The analysis of current-reused amplifier is similar to resistive shunt-feedback amplifier.3.4.1 Gain analysis
By stacking NMOS M1n and PMOS M1p transistors, the RF signal will be amplified by two common-source amplifiers, which share the same bias current so as to lower the power consumption. In other words, the transconductance of input stage will be increased from gm to approximately 2gm. In addition, Rf is designed large value (6 kΩ) to avoid gain degradation.
3.4.2 Input matching analysis
The proposed LNA is designed to match to 50 Ω, the input small signal equivalent circuit is shown in Fig. 3.6, where Zo is output impedance of current-reused stage; ro is shunt channel length modulation resistor of both M1n and M1p;Ls =Ls1// Ls2; gm =gmn+gmp. For simplicity, parasitic capacitances of input stage transistors are neglected. Because Cg is DC block capacitor, it can also be ignored from following analysis.
Fig. 3.6. The small signal equivalent circuit of input stage.
We can observe that the input impedance of resistive shunt-feedback amplifier is equal to (3-2), except for enhancement of gm in this design. By (3-2), the common-source amplifier can reduce input resistance by Rf feedback because of the Miller effect so as to achieve 50 Ω impedance matching. Note that Rf must be enough large value to maintain gate-to-drain isolation and minimize the noise.
If we consider parasitic capacitance of input stage, the input return loss will be degraded at higher frequency due to the large input parasitic capacitance by Miller effect. The current-reused configuration by stacking NMOS and PMOS increases not only transconductance by gm=gmn+gmp, but also parasitic capacitance by Cgs=Cgsn+Cgsp and Cgd=Cgsn+Cgsp. The effective input capacitance will be amplified more seriously. For this purpose, Ls and Lg are added for better input matching at high frequency. Here, the input impedance Zin including Ls and Lg can be derive as
( )
The simulated results of input and output reflection coefficients are shown in Fig. 3.7 and Fig. 3.8. We can observe that the curve is around the center of the Smith chart over UWB band from 3.1GHz to 10.6GHz. It shows that this design and analysis can successfully achieve wideband input impedance matching.
Fig. 3.7. Simulated result of input reflection coefficient.
Fig. 3.8. Simulated result of output reflection coefficient
3.5 Chip implementation and measured results
3.5.1 Layout considerations
The layout is very important for radio-frequency integrated circuit, because high frequency will make more parasitic and coupling effects occur to influence performances. All pads and important path line use bottom ground metal and guard-rings are added with all components for shielding to prevent noise and interference from substrate. The RF pad size is 50 x 50 um2, which is the smallest accepted size according to CIC testing rule. Because the bottom ground metal is used as shielding, the RF pad has parasitic capacitance which will degrade the RF signal.
Thus the smaller pad can lead to a smaller parasitic capacitance. In this design, the pas size of 50 x 50 um2 has capacitance value approximately equal to 22fF, which be contained in simulation. All interconnections between elements are taken as a 45°
corner. The bypass capacitors are added between each voltage source node and ground node to ensure voltage source working like ground in AC and filter out noise.
A DC-blocking capacitor is needed in the input of the UWB LNA circuit to isolate DC current between the circuit and instrument. All transmission lines of signal path are simulated by an electromagnetic software to find out the parasitic and coupling effects in order to make the simulated results more accurate.
3.5.2 Measurement considerations
The layout of the proposed LNA is shown in Fig. 3.9. The chip layout must be according to CIC’s probe station testing rules for on-wafer measurement. This circuit requires two RF GSG probes placed on opposite sides of the layout for RF signal input and output, a 3-pin DC probe, and a 6-pin DC probe. The fabricated chip photo with testing probes is shown in Fig. 3.10. All probes are pitch 100 µm for saving area.
Fig. 3.11 expresses the arrangement of RF and DC probes.
Fig. 3.9. Chip layout of the UWB LNA.
Fig. 3.10. Microphotograph of the UWB LNA with probes.
RF
inRF
outDC
DC
Fig. 3.11. On-wafer measurement of UWB LNA test diagram.
The chip is measured in CIC RFIC testing environment. The measurement equipments include a network analyzer, a noise analyzer, a spectrum analyzer, two signal generators, and several dc power supplies. The measurement setup for S-parameters, noise figure, input 1dB compression point and input-referred third-order intercept point are shown in Fig. 3.12(a-d).
Network Analyzer
(a)
(b)
(c)
Signal Generator 1
Spectrum Analyzer
Signal Generator 2
Combiner
(d)
Fig. 3.12. Measurement setups for (a) S-parameter. (b) noise figure. (c) P1dB. (d) IIP3.
3.5.3 Measured and simulated results
The proposed LNA for UWB system has been fabricated on TSMC 0.18 µm mixed-signal/RF CMOS 1P6M technology with chip size of 0.949 x 0.912 mm2. The total power consumption is 14.4 mW with bias voltage source 1.5 V and 0.7 V. The S-parameter are shown in Fig. 3.13-3.16. The input return loss (S11) in Fig. 3.13 shows the measured S11 lower than -10 dB, which degrades about maximum 2 dB compared with simulated result at 7 GHz. Fig. 3.14 indicates the measured and simulated output return loss (S22). The measured S22 is lower than -17 dB and the experimental result reveals measured S22 is better than simulated S22. The gain (S21) is an important parameter of a LNA. The measured S21 degrades about 2 dB and 1 dB at low frequency and high frequency than simulated S21, respectively. The measured S21 in 3.1-10.6 frequency band is 11.9 dB to 16.4 dB, which is not flat in UWB band.
The noise figure (NF) performance is shown in Fig. 3.17. The measured NF has maximum 5.28 dB and minimum 3.33 dB, which is higher than simulated NF perhaps due to the inaccurate noise model and post-simulation. The input-referred 1dB compression point (P1dB) are shown in Fig. 3.18(a-e). The measured P1dB are -18.3 dBm at 3.1 GHz, -18.5 dBm at 4.9 GHz, -18.5 dBm at 6.8 GHz, -15.6 dBm at 8.7 GHz, and -11.7 dBm at 10.6 GHz. The input-referred third-order intercept point (IIP3) at five frequency points are shown in Fig. 3.19(a-e). The measured IIP3 shows -8.2 dBm at 3.1GHz, -9.5 dBm at 4.9 GHz, -9 Bm at 6.8 GHz, -2.6 dBm at 8.7 GHz, and 0 dBm at 10.6 GHz. The performance summary is listed in table 3.1.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.13. Measured and simulated results of S11.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.14. Measured and simulated results of S22.
2 3 4 5 6 7 8 9 10 11 12
Fig. 3.15. Measured and simulated results of S21.
2 4 6 8 10 12
Fig. 3.16. Measured and simulated results of S12.
2 3 4 5 6 7 8 9 10 11 12
Frequency (GHz)
2 3 4 5 6 7
NF (dB)
Measurement Simulation
Fig. 3.17. Measured and simulated results of noise figure.
-30 -25 -20 -15 -10
-30 -25 -20 -15 -10
Fig. 3.18. Measured and simulated results of P1dB at (a) 3.1 GHz. (b) 4.9 GHz. (c) 6.8GHz. (d) 8.7 GHz. (e) 10.6 GHz.
-40 -35 -30 -25 -20 -15 -10 -5
Measured IIP3 @ 3.1GHz
(a)
Measured IIP3 @ 4.9GHz
(b)
Measured IIP3 @ 6.8GHz
(c)
-40 -35 -30 -25 -20 -15 -10 -5 0
Measured IIP3 @ 8.7GHz
(d)
Measured IIP3 @ 10.6GHz
(e)
Fig. 3.19. Measured result of IIP3 at (a) 3.1 GHz. (b) 4.9 GHz. (c) 6.8GHz. (d) 8.7 GHz.
(e) 10.6 GHz.
Table 3.1
Performance summary of the proposed LNA
Specification Measurement Post Simulation
Input Return Loss (dB) -16.8~-10.6 -19.8~-14.1
Output Return Loss (dB) -58~-16.7 -21.4~-13.6
Gain (dB) 14.1± 2.3 14.75 ± 1.85
Isolation (dB) -64.6~-40 -73.8~-36.8
P1dB (dBm) -18.7~-11.7 -20.2~-13.7
IIP3 (dBm) -9.5~0 -12.5~-3.5
Noise Figure (dB) 3.3~5.3 2.7~3.8
Vdd (V) 1.5 V 1.5 V
Total LNA Power (mW) 14.4 11.6
3.5.4 Comparison with other literatures
The performances of the proposed UWB LNA are compared with other works for UWB band listed in Table 3.2. This work has the smallest ratio of average gain to power approximately equal to 1. It reveals that the current-reused configuration can efficiently enhance the gain performance. In 3.1-10.6 GHz, the proposed LNA exhibits average gain of 14.1 dB while consumes 14.4 mW power. The NF of the proposed LNA also has better performance at lower frequency than other works based on CMOS 0.18 um process. In addition, no buffer is required in this design, however, table 3.2 shows that this work has the best output return loss, which is lower than -16.7 dB over UWB band.
Table 3.2
Comparison of Ultra Wide-band LNA
Ref. Process
Chapter 4
Design of Low-Power High-Linearity Inductorless Mixer for UWB
4.1 Introduction
RF CMOS technology is developed to achieve higher frequency and wider bandwidth application. Large-scale availability of CMOS allows devices to be manufactured at a much lower cost as compared with devices that depend on non-silicon technologies. The UWB communication system over 3.1 GHz to 10.6 GHz frequency band will be widely used in the short distance WPAN, providing high data rates to a large number of users over large area.
In the chain of down-conversion UWB receiver, the mixer plays a key role to shift RF signal to IF. The researches of wideband matching for the mixer have developed. For example, the matching network for the mixer can employ distributed network [14] and LC ladder network [15] as shown in Fig. 4.1 and Fig. 4.2, respectively. However, both methods require inductors that occupy large die area that is unsuitable for integration.
Fig. 4.1 The mixer using the distributed matching network.
Fig. 4.2. The mixer using the LC ladder matching network.
High linearity receiver is essential for high data rate communication system. The second stage should consider the linearity performance because the last stage is a prominent contributor to degrade the linearity. For a cascaded amplifier, the total input-referred third-order intercept point (IIP3total) can be expressed as
2 2 2
1 2 3
1 1
3total 3 3 3 .
IIP IIP IIP IIP
α α β
≅ + + +" (4-1) where α and β are the linear gain for the first and second stages, respectively. From
(4-1), we can observe that the IIP3 of the last stage significantly affects the total IIP3.
In addition, because LNA usually designed for high gain to suppress the noise of next stage, it is difficult to maintain comparatively better linearity. In general, the linearity of the receiver is dominated by a mixer. The linearity performance requirement becomes more significant in modern RF mixer for improvement of the receiver dynamic range and immunity to the various interferer signals from other communication standards.
In this work, a low-power, high-linearity wideband down-conversion mixer without the use of inductors is designed and implemented using TSMC 0.18 µm CMOS process. The circuit will be analyzed and discussed.
4.2 Architecture
In Fig. 4.3, the proposed mixer is based on Gilbert-cell topology, which is double balance mixer to suppress LO-to-IF feed though compared to single balance mixer.
Three voltage sources (VDD=1.8 V, VB=0.77 V, VS=0.63 V) are used in the circuit. The bias voltage, VB, at switching stage is not shown in the diagram. The transistors of switching stage with small W/L are sufficiently fast to steer the RF current from transconductance stage to switching stage. The gate-to-source voltage (Vgs) is set near threshold voltage (Vt) for completely current commutation. The differential output employs the buffer to provide 50 Ω output impedance for on-wafer measured requirement. In this work, some techniques will be exploited to improve linearity of the mixer.
Fig. 4.3. Schematic of the proposed mixer.
4.3 Design considerations
4.3.1 Common-gate transconductance stage with source resistor
The proposed mixer employs common-gate (CG) amplifier as transconductance stage. The CG configuration adding a source resistor can improve linearity. To observe this phenomenon, we derived the voltage gain (AV) of CG amplifier as
= +In2 1.
V
S In
A R
R R (4-2)
where In1≅ 1 .
m
R g (4-3)
and RIn2 is second stage input resistance. From (4-2), additional source resistor RS will
stabilize the voltage gain throughout operation. If the transconductance value gm
varies, the operation point will not vary as much. Therefore, CG amplifier with source resistor can maintain stability of operation point against variation in transistor parameters. However, the trade-off is that the voltage gain will degrade because of source resistor.
The CG configuration also has wide bandwidth to achieve better linearity compared to common-source (CS) configuration. The high-frequency response of CG amplifier is shown in Fig. 4.4, where CIn2 is second stage input capacitance. For simplicity, channel length modulation is negligible because RIn2 is relatively small. In such case, there are two poles given by
( )
The frequency response can be derived as
( )
= + 2(
+ ω 1)(
+ ω 2)
Fig. 4.4. CG amplifier.
Besides, in Fig. 4.5, CS amplifier also has two poles obtained as If CS voltage gain is enough large, ωP1 will dominate the high-frequency response due to Miller effect. Therefore, the voltage gain of CS configuration begins to decay at lower frequency. Here, although RIn2 is relatively small, which reduces the gain, the CG bandwidth is still better than CS bandwidth.
In general, 50 Ω input matching is difficult for CS stage due to its large input resistance. For this purpose, matching network including inductors is required.
However, inductors are usually large so that impedes the level of integration. In this work, CG configuration provides excellent input-matching over wide bandwidth by setting RS+1/gm ≅50 Ω, which is suitable for UWB application.
Fig. 4.5. CS amplifier.
4.3.2 Current-Injection Technique
For Gilbert-cell mixer, the conversion gain and IP3 are expressed as
2 . Both the conversion gain and the input third-order intercept point (IIP3) are proportional to the square root of the bias current. However, the consequence of increasing bias current will increase the voltage dropped across load resistor. Thus the mixer remains less voltage headroom to degrade the linearity. One method to deal with this problem is current-injection technique [16]. It can be achieved by injecting the required additional bias current into the drain of the transconductance stage MOSFETs to reduce the bias current in the switching stage. The small bias current in the switching stage also allows the usage of large load resistor without consuming large voltage drop from the limited headroom. However, current source will contribute to the mixer noise.
Because flicker noise of the switching stage is only present at the switching instant of the LO differential pairs, we can inject a dynamic current equal to bias current at only the switching event. The dynamic current-injection technique [17] is shown in Fig. 4.6, where MP1 and MP2 are switching pairs to control when current source (MP3) injects to the transconductance stage. Using this technique can improve the flicker noise and minimize the bias current in the switching stage. In this design, only 350 µA current flows through each load resistor. In addition, because the bias
Because flicker noise of the switching stage is only present at the switching instant of the LO differential pairs, we can inject a dynamic current equal to bias current at only the switching event. The dynamic current-injection technique [17] is shown in Fig. 4.6, where MP1 and MP2 are switching pairs to control when current source (MP3) injects to the transconductance stage. Using this technique can improve the flicker noise and minimize the bias current in the switching stage. In this design, only 350 µA current flows through each load resistor. In addition, because the bias