This thesis covers theoretical analysis of data and power telemetry and practical circuit design implementation. After introducing the fundamentals of power and data telemetry, the design challenge of system is discussed. According to the target specifications of the telemetry, the design procedure from system level to transistor
Power
level is introduced in detail. The transistor level simulation and prototype chip measurement are also presented. The thesis is organized as following:
Chapter 1 consists of simple introduction and motivation of this thesis.
Chapter 2 is an overview of general telemetry. The principles of channel capacity and power efficiency are also described. The fundamental of modulation scheme is introduced briefly, such as ASK and BPSK. Furthermore, advance techniques of BPSK demodulator are introduced, which can achieve lower power consumption.
Finally, the related paper is also discussed.
Chapter 3 proposes the system level design procedure. Due to bandwidth of coil, demodulator must be designed carefully. Power efficiency and channel capacity are estimated roughly. Finally, a system which connects the coil and demodulator is simulated by h-spice.
In Chapter 4, practical circuits design and implementation is introduced. Some non-idealities of practical circuit implementation are considered. The building block designs of proposed demodulator are detailed. Finally, the transistor level simulation of BPSK demodulator is presented.
Chapter 5 and Chapter 6 cover the test environment and the experimental result and conclude the thesis and future work respectively.
Chapter 2
Fundamentals of Power and Data Telemetry _________________________________________
2.1 Relation of Power Efficiency and Channel Capacity
An inductive power link is composed of a transmitter’s and receiver’s coils (L1
and L2), as shown in Figure 6 (a). The coupling coefficient of two coils k (0 < k < 1) depends on the portion of the total flux lines that cuts both primary and secondary coils. An AC voltage Vin is applied across the transmitter’s coil, and this induces an AC voltage Vc1 on the receiver’s coil. Receiving coil is connected to a load Rload
(Figure 6 (a) [4]). Vpeak is a fixed value according to data rate, if rectifier output has to achieve 1.8 volts. Rectifier input power is defined by equation (1). Therefore, we estimate the AC resistance by equation (2).
power The equivalent AC parallel resistance can be transform into equivalent AC series resistance Figure 6 (b) [4]. The quality factor of the series LC transmitting circuit is
resistance. Re represents reflected impedance from secondary coil to primary coil. efficiency η between transmitted and received powers (P0 and P1) is represented by
1 provides the maximum power efficiency given these circuit parameters.
Figure 6. Basic circuit for wireless power transmission
This paper presents a scheme that the coils transmit power and data simultaneously, so we must calculate the system capacity to estimate the limitation of transmission data rate. However, received power is one of important factors for determination of the system capacity. This is well known that higher capacity can be achieved with the higher received signal power.
Power
Figure 7. Basic communication system
According to Figure 7 in this book, as shown in [4], data rate can be discussed by three part, where are transmitter part, receiver part, and the channel. At first, the transmitter baseband data rate is half of signal bandwidth, as shown in Figure 8 and [4].
Figure 8. BPSK modulator and power spectrum
log(1 P
R) C B
N
(8) The received power also affects the data transmission. In order to evaluate the maximum data rate, channel capacity is evaluated, as shown in [10]. Channel capacity C is impacted by the received signal power PR, LC tank bandwidth B, and noise power N. Considering only thermal noise, the noise power N is given by the Johnson’s noise formula: (10)
Communication bandwidth = 2*data rate -2
( )
carrier frequency f0 is described below. (10)2 2 2 2 2 2 2 SNRout are signal-to-noise ratios measured at the circuit input and output respectively.
Bandwidth is the twice of baseband data rate.
,
Where Psig,total is received power, PRS is thermal noise, and Pin is the minimum received power without error. Once the transmitter, channel capacity, and receiver specs are fixed, we can estimate the highest data rate. The bottleneck of this system data rate will be the channel capacity, because the transmitter bandwidth is decided by the data rate we want to transmit, and the receiver bandwidth is wider than channel capacity because of high received power. There is another issue we have to discuss, the bit error rate in the communication system. Because the receiver circuit is implanted, we have to ensure the high BER performance avoiding from additional circuit to check and
correct the data, as shown in equation (14), equation (15) and [4]. The BER is estimated by the formula which is use for the binary modulation, where fb is bit rate, and the BW means channel bandwidth:
BW
2.2 Modulator Scheme Comparison
The common used modulation schemes are ASK, FSK and PSK as shown in Figure 9. ASK modulate the baseband data with the amplitude. One means that the carrier will be transmitted, zero means that a DC voltage is transmitted. FSK modulate the baseband data with the frequency. One means that the carrier1 is transmitted, zero means the carrier2 is transmitted, where the carrier1 and carrier2 is at different frequency tone. PSK modulate the baseband data with the phase. One means that the 0o will be transmitted, zero means that the 180o is transmitted. 1 and -1 are the baseband data, the modulator is like a switch which changes data back and forth. The modulated data is transmitted by coil operating at the carrier frequency.
Amplitude-shift keying (ASK) or on-off keying (OOK) is frequently used for data transmission due to its simplicity. However, ASK and OOK modulations suffer from low data rate and instability for power transmission. In contrast, frequency-shift keying (FSK) modulation requires a LC resonator with a low quality factor, but this leads to low power efficiency. Constant-envelope, fixed-carrier frequency modulations conveys stable power regardless of data pattern, which is a better
solution for simultaneous data and power transmission. Binary phase-shift keying (BPSK) is preferred in order to reduce the power consumption of demodulator.
Another advantage of BPSK is that it requires less transmitted power to achieve the same bit-error rate (BER) when compared to FSK or ASK, as shown in Table 1.
Figure 9. Common modulation scheme
Table 1. Pros and cons of the different modulation scheme Mod.
scheme Bit Error Rate Advantage Disadvantage
ASK worst of all 1.easy to implement 2.low power consumption
1.increased susceptibility to amplitude noise
2.low data transmission rate FSK worse than
BPSK or QPSK high power efficiency poor bandwidth efficiency BPSK Better than FSK increased noise immunity 1 bit/symbol
QPSK same as BPSK better bandwidth efficiency increased susceptibility to phase noise
Figure 10 shows the BPSK modulator [6], the baseband data is modulated by a switch.For BPSK demodulation, phase-locked loop (PLL) was proposed and it provides stable data and power transmission [6][7]. However, the high power consumption of PLL-based demodulator is not suitable for implantable devices since
A(t)cos[2πfct]
baseband data
1 0 1
ASK
FSK
PSK
t
t
t cos[2π(fc+f(t))t]
cos[2πfct+θ(t)]
PLL requires phase synchronization for coherent detection. For instance, the most commonly used squaring or COSTAS loop, as shown in Figure 11 (b). Extracting clock from received data can be used to eliminate the use of PLL, as shown in Figure 12 (a). This clock-recovery technique was adopted for data transmission [9][10][18], but applying this technique to simultaneous data and power transmission has not been explored.
In this work, we propose a clock-recovery-based BPSK demodulator for data and power telemetry targeting for epilepsy seizure detection. Since power consumption is an important issue for implantable devices, a symbol edge detector is used instead of a power-hungry oscillator, as shown in Figure 12 (b). This replacement further reduces power consumption.
Figure 10. BPSK modulator
Figure 11. (a) Squaring loop (b) Costas loop XBB(t)
comparator clipping
Reset
Generator Clock and Data Recovery Oscillator
Data Clock
clipping
Reset Generator
Clock and Data Recovery
Data Clock comparator Symbol Edge
Detection (a)
(b)
Figure 12. (a) Conventional clock-recovery-based demodulator and (b) proposed oscillator-less demodulator.
2.3 Related Telemetry Paper Review
As we introduce in section 2.2, we prove the theory by the related work. Every work is used for different telemetry, so data rate and power efficiency demand will be different. Reference [12][13][14][15] use the ASK modulation, as we can see the data-to-carrier ratio range is from 0.01 to 0.1. It means that if we transmit 13.56MHz carrier frequency, the most data rate will be 1.356 Mbps, not mention that these systems are not take stable power into account. The only one work which transmits power simultaneously is reference [10]. According the record of this paper, power varies with the data.
FSK demodulator is introduced in reference [17]. FSK is not use frequently in biomedical telemetry. The data-to-carrier ratio is high to 0.5, but the power supply and
power consumption is not mentioned in paper.
BPSK modulation is implemented by reference. Data-to-carrier ratio is from 0.0015 to 1. The reference [18] and [19] successfully transmit a stable 22.5mW to implant. The reference [22] provides a scheme improving the data-to-carrier ratio to 100%, and the demodulator power consumption is low compared to another scheme, but this demodulator is not connected to any communication channel.
Table 2. Comparison of the related demodulator
Article Data Transmission Power Transmission
CMOS DPSK modulation [23], this paper transmit power and data separately (using two coils) for the optimal power efficiency and data rate. The most important issue of two coils is the interference between two channels. This paper implements a DPSK modulation to
cancel the interference by inter-symbol noise subtraction. The other modulation is QPSK [24][25], as the theory, outstanding data-to-carrier ratio which is high to 0.58, but the power consumption is much higher than BPSK scheme. According to theory, the QPSK demodulator is two sets of BPSK basically, so the power consumption of QPSK will be twice the BPSK using the same circuit.
For a stable power transmission, low demodulator power consumption and high BER. BPSK modulation scheme is used in this paper.
Chapter 3
System Level Design
_________________________________________
3.1 System Level Parameters
Figure 13 shows the block diagram of this power and data transmission system.
First at all, the coil parameter is defined. Owing to the constraint of implant size, the inductance of internal coil must be low, where the quality factor of internal coil is low.
The quality factor of internal coil is 30.99. Higher quality factor of coil achieves higher power efficiency, and High power efficiency upgrade the channel capacity, so external quality factor of coil must be great for better power efficiency and channel capacity. In our work, the external quality factor is 165.66 [1].
Figure 13. A data and power telemetry block diagram
We use a bridge rectifier to convert AC voltage to DC. For the high frequency (13.56MHz) operation in this power and data telemetry, Schottky diode is chosen to rectify the received signal. Once the rectifier spec is known, the rectifier efficiency and the implant circuit power consumption are fixed. In this paper, efficiency of rectifier achieves 70% based on the datasheet. 5mW is needed for implant circuits.
Primary data
Modulator Power
Amp. Rectifier Demod.
Demodulated External Skin Implant data
R1 R2
Rac
L1 L2
The minimum power received by the inter coil is 7.14mW=5mW/0.7. Rload is rectifier input resistance parallel with the demodulator input resistance, and input resistance of the demodulator is high impedance. The input resistance of internal implants is about Rload. When we measure the coil and rectifier to estimate the power efficiency, demodulator circuit is no need to connect. We want to rectify a 1.8 DC voltage for the demodulator circuit, and Vpeak of internal coil is 5.8Vpp. Once the internal coil Vpeak
and received power is obtained, the Rac is known to be 2356Ω. The parameter of coil power efficiency is known, the coupling coefficient is 0.05122, the quality factor of L1
is 165.66, and the quality factor of L1 is 30.99. R2 is 1.05Ω. The power efficiency is about 26.84%. The external coil has to transmit 26.6mW=7.14mW/0.2684.
Once the received signal is obtained, the channel capacity could be estimated.
We know that the C=Blog(1+S/N). The channel bandwidth B is 78kHz which is calculated by equation. The S is the received power 7.14mW. The N=BW*K*T. In our simulation we have assumed that the system is operating at the room temperature of about 27o in the resonance frequency 13.56MHz. If the communication bandwidth is varied with data rate, N=828*data rate*10-17. We assume that the data bandwidth is 1 Mbps. Then the channel capacity is estimated to 942.9 kbps. After the SNR is known, the BER is estimated as well. Eb/N0=(SNR*(channel bandwidth))/bit rate.
Eb/N0=6.81*1010 (BER < 10-9).
3.2 Coil and Rectifier Architecture
Once the implant physical size constraint is decided by system application, the coupling coefficient(k) can be maximize by proper choosing the outer diameter size of coils, and the Q factor can be maximize by the coils’ structure and coils’ material. Since Q factor and coupling coefficient are increase as the outer diameter increase, the first step of efficient near-field coils design maximizing the coupling coefficient would not conflict
the design parameter of maximizing the Q factor. Once we maximize the coupling coefficient by deciding the primary and outer diameter of secondary coil, that recent research have been widely studied [34], we can maximize the Q factor by using allowable wide copper metal and low loss coil structure. The coil structure mainly divides into three parts: multi-layer cylindrical coil, single layer cylindrical coil and spiral coil, as shown in Figure 14 (c). The different structure have different Q factor, because the skin effect and the proximity effect [35]. In this paper, the single layer cylindrical coil is used for external coil because the greater quality factor. The internal coil which we choose is the spiral coil, because the cylindrical coil is too thick to implant.
Figure 14. (a) Single layer cylindrical coil (b) Multi-layer cylindrical coil (c) Spiral coil which is winded by copper conductor
The carrier resonance frequency is set to 13.56MHz.The parameters of coils are summarized in Table 3.
Table 3. External and internal coil spec
Primary coil Secondary coil
L (μH) 7 0.382
C (pF) 18.8 374.25
R (Ω) 3.6 1.05
Q 165.66 30.99
diameter (cm) 4.2 1.1
thickness(cm) 1.8 0.2
After coil parameters are fixed, the rectifier spec is known. We use simple bridge rectifier by using schottky diode, as shown in Figure 15 (a). When the positive cycle
r
r
(b) (c)
(a)
is applied to the rectifier (the solid line), D1 and D3 is conducting, and the D2 and D4 are cut off. The induced current in internal coil goes through the red path, as shown in Figure 15 (b). When the negative cycle is applied to the rectifier (the solid line), D2 and D4 is conducting, and the D1 and D3 are cut off. The induced current in internal coil goes through the red path, as shown in Figure 15 (c).
Figure 15. (a) Bridge rectifier (b) Positive cycle function of the bridge rectifier (c) Negative cycle function of the bridge rectifier
Once the rectifier function is working, we let that the rectifier conducting voltage be Vr. DC voltage applied to the Rload is that Vpeak minus 2Vr as shown in Figure 16.
Rload is input resistance of VDD and GND in demodulator which is 1.2kΩ. We connect a large capacitor 1μF to make the ripple of Vo as small as we can.
If we transmit all 0 or all 1 data (a 13.56 MHz sine wave without modulated), we can derive the rectified DC value by the equation (16)-(19) and Figure 16.
O S 2 V V V
(16)
D1
D3 D2 D4
Rload
Rload
Rload
(a)
(b)
(c)
min exp
Figure 16. (a) Relation of rectifier drop-out voltage and input Vpeak (b) Ripple of Vr
3.3 BPSK Demodulator Architecture
A clock-recovery-based demodulator architecture is adopted to reduce the complexity induced by PLL. The BPSK demodulator circuit is presented in Figure 17.
There are four blocks, and the first block of comparator and clipping which is connected to internal coil. The second block is enable circuit, and it’s an important part to power on at the symbol edge. The third block is reset generator which is used for generating the right reset signal at inter-symbol. The last block is data and clock recovery, where is used to regenerate the baseband data and carrier frequency.
Figure 17. A BPSK demodulator block diagram in this work
T/2 T 2T
Generator Clock and Data Recovery
Data
Clock
Figure 18 shows waveform of first block. BPSK modulation converts baseband data 0 and 1 into two in-phase waveforms. It converts analog signals to digital signals through comparator and clipping circuit. When the Vc1 > 0 and Vc2 < 0, the comparator_out+ is high and comparator_out- is low. When Vc1 > 1.05V, the clip_out+ is high and clip_out- is low. When the Vc2 > 0 and Vc1 < 0, the comparator_out- is high and comparator_out+ is low. When Vc2 > 1.05V, the clip_out- is high and clip_out+ is low. Once these four signals are obtained, the later circuit will start by detecting these signals.
Figure 18. Comparator and clipping circuits function
Figure 19. Start circuit’s function
The right symbol edge should be detected in order to recover the data. There are two circuits to generate the enable signal. The first is a circuit named start circuit, one of the differential outputs of the clipping circuit (clip+ or clip-) is used to extract the clock frequency and trigger the start signal. Figure 19 shows the functionality of the
Vc1
Vc2
comparator_out+
comparator_out-clip+
clip-Vc1 Vc2
comparator_out+
clip+ & clip-Power on
q1 q2 q1 xnor q2 start
start circuit. An external power on signal is switched to enable the detection process.
The second circuit is named enable circuit. Because the start circuit is triggered at the clip_out edge, which will make the enable signal is leading for a half cycle. We use a 3-bit counter which counts to 7 to start the enable signal as shown in Figure 20. The counter counts to 7, so the signal is triggered leading for a half cycle also. The final enable signal is triggered at symbol edge correctly.
Figure 20. Enable circuit’s function
The third block is the reset generator, as shown in Figure 21. After digital signals are extracted, there is an edge detection circuit to detect rising or falling edges. When two falling edges are detected, the reset signal is pulled to high. The reset signal goes down if a rising edge is detected. The reset generator is working until the enable signal is pulled to low.
Figure 21. Reset circuit’s function
Vc1
Vc2
comparator_out+
start q0 q1 q2 enable
Vc1
Vc2 comparator_out+
clip+
clip-enable
reset
We propose an area-efficient circuit implementation for data-and-clock recovery (DCR). It consists of two D flip-flops whose clocks come from the differential outputs of the comparator and data input is connected to high. Timing diagram of the key signals are shown in Figure 22.
Figure 22. Data and clock recovery circuit’s function
The q0 and q1 signals are generate by the comparator_out+ and comparator_out- respectively. Reset signal is used to reset the q0 and q1 signal at symbol edge. The q0 and q1 generate a clock. Frequency of this clock is the same as carrier from the coil.
Once the reset signal goes high, an edge detector generates right signals to DCR.
3.4 System Level Simulation
We simulation the coil and demodulator circuit simultaneously by h-spice. If we transmit the same power to the external coil, the received coil amplitude changes with different data rate as shown in Figure 23. The last line is the received waveform at 13.56 Mbps data rate, and it’s clearly that the power is not transmitted to the internal at all. Figure 23 shows that the data rate higher than channel capacity. It’s clearly that the received input waveform’s distortion is too large to detect by our BPSK demodulator. We estimate that comparator_out+ is wrong at every symbol edge. The
Vc1
Vc2
comparator_out+
enable reset
comparator_out-q0 q1 clock data
data is impossible to be recovery.
Figure 23. Received waveform in internal coil at data rate higher than 678 kbps with PRBS
Primary data Vin Vc1 Primary data
Vin Vc1 Primary data
Vin Vc1 Primary data
Vin Vc1 13.56 Mbps
1.356 Mbps
452 kbps
135.6 kbps
0 1u 2u 3u 4u 5u 6u 7u 8u
Chapter 4
Circuit Design and Implementation
_________________________________________
4.1 Comparator and Clipping Circuit
As introduced in Chapter 3, we have to digitize the modulated signals. In the beginning, comparator and clipping circuits are needed. The most important issue of
As introduced in Chapter 3, we have to digitize the modulated signals. In the beginning, comparator and clipping circuits are needed. The most important issue of