Transistor Level Simulation

We use radio-frequency h-spice to simulate our BPSK demodulator. In this section, we show the simulation results of each part which we mention in 4.1 to 4.4.

At first, transistor size of comparator and clipping circuits are showed in Figure 38.

We have to sure that the common mode DC value of these two circuits. When input V_c1 and V_c2 common mode DC is ground, the comparator differential output 0 and 1 transition will occur at 133mV which is near to 0 volt, as shown in Figure 39 (a).

Table 4 shows the input offset versus the comparator and clipping transition. If the input offset is higher than 0.6 volts, the comparator and clipping output transition will be at the same input voltage. This situation will make the later circuit malfunction.

Figure 38. Comparator and clipping circuit with transistor size Q

Figure 39. (a) Pre-simulation waveforms of comparator and clipping DC analysis at 0V offset (b) 0.6 V offset

Table 4. DC offset versus comparator and clipping transition voltage

offset (V) comparatot_out+(mV) comparatot_out- (mV) clip+ (V) clip- (V)

0 0.133 0.133 1.05 -1.06

0.6 1.11 1.11 1.11 -0.126

After the comparator and clipping circuit is determined, we have to ensure that the later circuit delay is smaller than our function limitation. There are four states

when we transmit data. They were one to zero、zero to zero、zero to one and one to one.

Case I: Symbol edge at transition of data from 1 to 1 is shown in Figure 40 (a).

The enable circuit delay from comparator output to enable is less than 1.04ns. As we can see that the clip- is 4.3ns far from comparator output. The enable will be triggered before the transition of clip+. The reset generator circuit latency is less than 0.425ns.

The comparator output transition is 3ns from clip+. So the reset signal is working at the right time here. Once the enable and reset signal are ready, data and clock will be right.

Case II: Symbol edge at transition of data from 0 to 0 is shown in Figure 40 (b).

The enable circuit delay is less than 1.02ns. The clip- is 4.6ns far from comparator output. Enable is triggered before the transition of clip+. The reset generator circuit latency is less than 0.425ns. The comparator output transition is 0.8ns from clip+.

Reset signal is working at the right time here. Once the enable and reset signal are ready, data and clock will be right.

Case III: Symbol edge at transition of data from 0 to 1 is shown in Figure 40 (c).

Start circuit’s latency is 0.64ns. The enable circuit delay is less than 1.04ns. The clip- transition is 7.4ns far from clip+ transition. The enable will be triggered after the transition of clip-. Correctness of the reset generator circuit is sure. Reset generator circuit output will be wrong if the comparator transition is complete before clipping transition, but the comparator transition won’t happen in this case. So the reset signal is always right. Once the enable and reset signal are ready, data and clock will be right.

Case IV: Symbol edge at transition of data from 1 to 0 is shown in Figure 40 (d).

The enable circuit delay from is less than 1.02ns. As we can see that the clip-

transition is 7ns from clip+ transition. Enable is triggered after the transition of clip-.

It is sure that the correctness of the reset generator circuit. The reset generator circuit output will be wrong if the comparator transition is complete before clipping transition, but the comparator transition won’t happen in this case. Reset signal is always right. Once the enable and reset signal are ready, data and clock will be right.

Figure 41 shows that the transient simulation of comparator and clipping output.

Once the data transition occurs, one end of clipping differential output is low, and the other end has two pulses. One end of comparator differential output is high, and the other end is high.

Figure 40. (a) Transition of data from 1 to 1 (b) Transition of data from 0 to 0 (c) Transition of data from 0 to 1 (d) Transition of data from 1 to 0

14.9u 14.92u 14.94u 14.96u 14.98u 15u 15.02u 15.04u

TIME(sec) (lin)

15.06u 15.08u 15.1u 15.12u 15.14u 15.16u 15.18u

(a) (b)

14.98u 15u 15.02u15.04u 15.06u15.08u 15.1u 15.12u 15.86u 15.88u 15.9u 15.92u 15.94u 15.96u 15.98u 16u

TIME(sec) (lin)

Figure 41. Pre-simulation waveforms of differential input, comparator and clipping output

At the beginning, we simulate the delay between power on signal and start signal.

As we introduce in 4.2, when the power on is triggered by user, the start signal is triggered at the data transition (0 to 1 or 1 to 0). Table 5 shows the gate delay of this circuit. When the data is from zero to one, we can know that the start signal pulls to high after 0.64ns delay from clip+ and clip-. Figure 42 (a) shows the simulation waveform. When the data is from one to zero, we can know that the start signal pulls to high after 0.6ns delay from clip+ and clip-. Figure 42 (b) shows the simulation waveform.

Table 5. Delay of the start circuit with data from 1 to 0 or 0 to 1

Data=1-0 Data=0-1

input output rise_delay (ns) input output rise_delay (ns)

clip start 0.64 clip start 0.6

Figure 42. (a) Pre-simulation waveform of start circuit which the data is from 0 to 1 (b) Pre-simulation

waveform of start circuit which the data is from 1 to 0

After the start signal is obtained, there is a 3 bit counter to generate the enable signal. The start signal is always trigger at symbol edge. If the start signal is triggered when the transmitted data is one, the total gate delay from comparator_out+ and comparatot_out- are 1.04ns and 0.77 ns separately. Figure 43 (a) shows the simulation waveform. If the start signal is triggered when the transmitted data is zero, the total gate delay from comparator_out+ and comparatot_out- are 0.74ns and 1.02 ns

0 100n 200n 300n 400n 500n 600n 700n 800n 900n

TIME(sec) (lin)

0 100n 200n 300n 400n 500n 600n 700n 800n

TIME(sec) (lin)

separately. Figure 43 (b) shows the simulation waveform.

Figure 43. (a) Pre-simulation waveform of enable circuit which the data is 0 (b) Pre-simulation waveform of enable circuit which the data is 1

Table 6. Delay of enable circuit with data 1 or 0

Data=1 Data=0

input output rise_delay (ns) input output rise_delay (ns)

comparator_out+ enable 1.04 comparator_out+ enable 0.74

comparator_out- enable 0.77 comparator_out- enable 1.02

700n 800n 900n 1u 1.1u 1.2u 1.3u 1.4u

TIME(sec) (lin)

600n 700n 800n 900n 1u 1.1u 1.2u

(b)

Once the enable signal is high, the reset generator is triggered. The reset circuit’s inputs are clip+ and clip-. The rising delay of the circuit is 0.391ns and the falling delay is 0.425ns. Figure 44 (a) shows the simulation waveform. Table 7 and Table 8 show delay of reset generator and data and clock recovery respectively.

Table 7. Delay of the reset circuit

input output rise_delay (ns) fall_delay (ns)

clip+ reset x 0.425

clip- reset 0.391 x

Table 8. Delay of the data and clock circuit

input output rise_delay (ns) fall_delay (ns)

comparator_out+ clock 0.495 x

comparator_out+ data 0.62 0.894

comparator_out- clock 0.448 x

comparator_out- data 0.606 0.91

reset clock x 0.492

When the reset signal is obtained, DCR circuit is triggered. Delay from comparator_out+ to clock is 0.495n, and delay between comparator_out- and clock is 0.448n. comparator_out+ and comparator_out- delays to data are 0.62ns and 0.606ns separately. We know that the reset will pull these DFFs to low level to make the clock transition. Delay from reset to clock is 0.492ns. Figure 44 (b) shows the functionality of the DCR circuit.

Figure 44. (a) Pre-simulation waveform of reset circuit (b) Pre-simulation waveform of data and clock circuit