Chapter 1 Introduction
1.3 Thesis Organization
This thesis is organized as follow:
In Chapter 1, the overview of poly-Si TFTs and motivations of this thesis are described.
In Chapter 2, a novel fluorine-based plasma treatment, CF4 plasma treatment, is employed to treat the solid-phase-crystallized (SPC) poly-Si TFT. The electrical characteristics and reliability of the CF4 plasma-treated poly-Si TFTs are explored.
The fluorine passivation effect on SPC ploy-Si TFTs using CF4 plasma is investigated.
In Chapter 3, CF4 plasma treatment, combined with excimer laser annealing (ELA), is proposed to fabricate CF4 plasma-treated ELA poly-Si TFTs. The electrical characteristics as well as the device reliability of the ELA poly-Si TFTs are greatly improved. The mechanisms responsible to the device improvements are comprehensively discussed.
In Chapter 4, fabricating poly-Si TFTs on an FSG buffer layer is proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine incorporation in the poly-Si. Furthermore, the fluorine also increases the poly-Si TFTs reliability against hot carrier stressing, which is attributed to the formation of Si-F bonds.
However, too much fluorine incorporation causes an unwanted degradation phenomenon. The relation between the device characteristics and the amount of fluorine incorporated is analyzed.
In Chapter 5, the Ion and Ioff instabilities of poly-Si TFTs are investigated under various electrical stress conditions. The stress-induced device degradation is studied by measuring the dependences of Ion and Ioff on the drain/gate voltages. From the experimental results, dissimilar variations in Ion and Ioff are observed, which can be attributed to the variances in the amount of trap charges in the gate oxide and the spatial distributions of the trap states generated in the poly-Si channel. A comprehensive model for the degradation of Ion and Ioff in poly-Si TFTs under various stress conditions is presented.
In Chapter 6, scanning capacitance microscopy (SCM), combined with atomic
force microscopy (AFM), is employed to investigate the dielectric breakdown phenomena in thin SiO2 films. The localized breakdown spots can be clearly imaged by SCM. Moreover, these breakdown spots are carefully analyzed, which exhibit signals with low differential capacitance (dC/dV) signals.
In Chapter 7, conclusions of this thesis and recommendations for further research are given.
References:
[1] T. Yamanaka, T. Hashimoto, N. Hasegawa, T. Tanaka, N. Hashimoto, A. Shimizu, N. Ohki, K. Ishibashi, K. Sasaki, T. Nishida, T. Mine, E. Takeda and T. Nagano,
“ Advanced TFT SRAM cell technology using a phase-shift lithography,” IEEE Trans. Electron Devices, vol. 42, no. 7, pp. 1305-1313, 1995.
[2] N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch and I. D. French, “The fabrication and characterization of EEPROM arrays on glass using a low temperature poly-Si TFT process,” IEEE Trans. Electron Devices, vol. 43, no. 11 pp. 1930-1936, 1996.
[3] T. Kaneko, Y. Hosokawa, M. Tadauchi, Y. Kita and H. Andoh, “400 dpi integrated contact type linear image sensors with poly-Si TFT’s analog readout circuits and dynamic shift registers,” IEEE Trans. Electron Devices, vol. 38, no. 5 pp.
1086-1096, 1991.
[4] Y. Hayashi, H. Hayashi, M. Negishi and T. Matsushita, “A thermal printer head with CMOS thin-film transistors and heating elements integrated on a chop,”
IEEE Solid-State Circuits Conference (ISSCC), pp. 266, 1988.
[5] N. Yamauchi, Y. Inada and M. Okamura, “An intergated photodetector-amplifier using a-Si p-i-n photodiodes and poly-Si thin-film transistors,” IEEE Photonic Tech. Lett., vol. 5, pp. 319, 1993.
[6] M. G. Clark, “Current status and future prospects of poly-Si,” IEE Proc. Circuits Devices Syst., vol. 141, no. 1, pp. 3, 1994.
[7] Y. Oana, “Current and future technology of low-temperature poly-Si TFT-LCDs,”
Journal of the SID, vol. 9, pp. 169-172, 2001.
[8] S. Morozumi, K. Oguchi, S. Yazawa, Y. Kodaira, H. Ohshima, and T. Mano, “B/W and color LC video display addressed by poly-Si TFTs,” in SID Tech. Dig.,
pp.156, 1983.
[9] R. E. Proano, R. S. Misage, D. Jones, and D. G. Ast, “Guest-host active matrix liquid-crystal display using high-voltage polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 38, pp. 1781, 1991.
[10] C. H. Fa, and T. T. Jew, “The polysilicon insulated-gate field-effect transistor,”
IEEE Trans. Electron Devices, vol. 13, no. 2, pp. 290, 1966.
[11] W. G. Hawkins, “Polycrystalline-silicon device technology for large-area electronics,” IEEE Trans. Electron Devices, vol. 33, pp. 477-481, 1986.
[12] I. -W. Wu, “Cell design considerations for high-aperture-ratio direct-view and projection polysilicon TFT-LCDs,” in SID Tech. Dig., pp. 19, 1995.
[13] A. Nakamura, F. Emoto, E. Fujii and A. Tamamoto, “A high-reliability, low-operation-voltage monolithic active-matrix LCD by using advanced solid-phase growth technique,” in IEDM Tech. Dig., pp.847, 1990.
[14] R. B. Iverson and R. Reif, “Recrystallization of amorphized polycrystalline silicon films on SiO2: temperature dependence of the crystallization parameters,”
J. Appl. Phys., vol. 62, no. 5, pp. 1675-1681, 1987.
[15] F. Emoto, K. Senda, E. Fujii, A. Nakamura, A. Yamamoto, Y. Yamamoto, Y.
Uemoto, and Gota Kano, “ Solid phase growth technique for hogh cut-off frequency polysilicon TFT integrated circuits on a quartz substrate,” IEEE Trans.
Electron Devices, vol. 37, pp. 1462, 1990.
[16] M. K. Hatalis and D. W. Greve, “Large grain polycrystalline silicon by low-temperature annealing of low-pressure chemical vapor deposited amorphous silicon films,” J. Appl. Phys., vol. 63, no. 7, pp. 2260-2266, 1988.
[17] G. K. Guist, and T. W. Sigmon, “High-performance laser-processed polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 20, no. 2, pp. 77-79, 1999.
[18] N. Kudo, N. Kusumoto, T. Inushima, and S. Yamazaki, “Characterization of
polycrystalline-Si thin-film transistors fabricated by excimer laser annealing method,” IEEE Trans. Electron Devices, vol. 41, no. 10, pp. 1876-1879, 1994.
[19] T. Sameshima, S. Usui and M. Sekiya, “XeCl excimer laser annealing used in the fabrication of poly-Si TFT’s,” IEEE Electron Device Lett., vol. 7, no. 5, pp.
276-278, 1986.
[20] D. H. Choi, E. Sadauyki, O. Sugiura and M. Matsumra, “Excimer-laser crystallized poly-Si TFT’s with mobility more than 600 cm2/V.s,” IEEE Trans.
Electron Devices, vol. 40, no. 11, pp. 2129, 1993.
[21] K. Shimizu, O. Sugiura and M. Matsumra, “High-mobility poly-Si thin-film transistors fabricated by a novel excimer laser crystallization method,” IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 112-117, 1993.
[22] S. Y. Yoon, K. Hyung, C. O. Kim, J. Y. Oh and J. Jang, “Low temperature metal induce crystallization of amorphous silicon using a Ni solution,” J. Appl. Phys., vol. 82, pp. 5865-5867, 1997.
[23] G. Radnoczi, A. Robertsson, H. T. G.. Hentzell, S. F. Gong and M. A. Hasan, “Al induced crystallization of a-Si,” J. Appl. Phys., vol. 69, pp. 6394-6399, 1991.
[24] Z. Jin, G. A. Bhat, M. Yeung, H. S. Kwok and M. Wong, “Nickel induced crystallization of amorphous silicon thin films,” J. Appl. Phys., vol. 84, pp.194-200, 1998.
[25] S. W. Lee and S. K. Joo, “Low temperature poly-Si thin-film transistor fabrication by metal-induced lateral crystallization,” IEEE Electron Device Lett., vol. 17, pp. 160-162, 1996.
[26] H. Kim, J. G. Couillard and D. G. Ast, “Kinetic of silicide-induced crystallization of polycrystalline thin-film transistors fabricated from amorphous chemical-vapor deposition silicon,” Appl. Phys. Lett., vol. 72, pp. 803-805, 1998.
[27] Z. Jin, H. S. Kwok and M. Wong, “Performance of thin-film transistors with
ultrathin Ni-NILC polycrystalline silicon channel layers,” IEEE Electron Device Lett., vol. 20, pp. 167-169, 1999.
[28] G. Y. Yang, S. H. Hur and C. H. Han, “A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation,” IEEE Trans. Electron Devices, vol. 46, pp. 165-172, 1999.
[29] K. R. Olasupo and M. K, Hatalis, “Leakage current mechanism in sub-micron polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 43, pp.
1218-1223, 1996.
[30] C. H. Hong, C. Y. Park and H. J. Kim, “Structure and crystallization of low-pressure chemical vapor deposited silicon films using Si2H2 gas,” J. Appl.
Phys., vol. 71, pp.5427-5432, 1992.
[31] J. H. Jeon, M. C. Lee, K. C. Park, M. K. Han, “A new polycrystalline silicon TFT with a single grain boundary in the channel,” IEEE Electron Device Lett., vol. 22, no. 9, pp. 429-431, 2001.
[32] A. Yin, and S. J. Fonash, “High-performance p-channel poly-Si TFT’s using electron cyclotron resonance hydrogen plasma passivation,” IEEE Electron Device lett., vol. 15, no. 12, pp. 502-503, 1994.
[33] C. K. Yang, T. F. Lei, C. L. Lee, “The combined effects of low pressure NH3
annealing and H2 plasma hydrogenation on polysilicon thin-film-transistors,”
IEEE Electron Device lett., vol. 15, pp. 389-390, 1994.
[34] J. W. Lee, N. I. Lee, J. I. Kan, C. H. Han, “Characteristics of polysilicon thin-film transistor with thin-gate dielectric grown by electron cyclotron resonance nitrous oxide plasma,” IEEE Electron Device lett., vol. 18, pp.
172-174, 1997.
[35] K. C. Moon, J. H. Lee, M. K. Han, “Improvement of polycrystalline silicon thin film transistor using oxygen plasma pretreatment before laser crystallization,”
IEEE Trans. Electron Devices, vol. 49, pp. 1319-1322, 2002.
[36] T. Unagami and O. Kogure, “Large on/off current ratio and low leakage current poly-Si TFTs with multichannel structure,” IEEE Trans. Electron Devices, vol.
35, no. 11, pp. 1986-1989, 1988.
[37] B. H. Min, C. M. Park and M. K. Han, “A novel offset gated polysilicon thin film transistor without an additional offset mask,” IEEE Electron Device lett., vol. 16, no. 5, pp. 161-163, 1995.
[38] Z. Xiong, H. Liu, C. Zhu and Sin, J.K.O., “Characteristics of high-K spacer offset-gated polysilicon TFTs,” IEEE Trans. Electron Devices, vol. 51, no. 8, pp.
1304-1308, 2004.
[39] P. S. Shih, C. Y. Chang, T. C. Chang, T. Y. Huang, D. Z. Peng and C. F. Yeh, “A novel lightly doped drain polysilicon thin-film transistor with oxide sidewall spacer formed by one-step selective liquid phase deposition,” IEEE Electron Device lett., vol. 20, no. 8, pp. 421-423, 1999.
[40] K. Y. Choi and M. K. Han, “A novel gate-overlapped LDD poly-Si thin-film transistor,” IEEE Electron Device lett., vol. 17, no. 12, pp. 566-568, 1996.
[41] A.Bonfiglietti, M. Cuscuna, A.Valletta, L. Mariucci, A. Pecora, G. Fortunato, S.
D. Brotherton and J. R. Ayres, “Analysis of electrical characteristics of gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors with different LDD doping concentration,” IEEE Trans. Electron Devices, vol. 50, no.
12, pp. 2425-2433, 2003.
[42] Y. Mishima and Y. Ebiko, “Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure,” IEEE Trans. Electron Devices, vol.
49, no. 6, pp. 981-985, 2002.
[43] H. C. Lin, C.-M Yu, C.-Y. Lin, K.-L.Yeh, T. Y. Huang and T. F. Lei, “A novel thin-film transistor with self-aligned field induced drain,” IEEE Electron Device lett., vol. 22, no. 1, pp. 26-28, 2001.
[44] C. S. Lai, C. L. Lee, T. F. Lei and H. N. Chern, “A novel vertical bottom-gate polysilicon thin film transistor with self-aligned offset,” IEEE Electron Device lett., vol. 17, no. 5, pp. 199-201, 1996.
[45] M. J. Tasi, F. S. Wang, K. L. Cheng, S. Y. Wang, M. S. Feng, and H. C. Chen,
“Characterization of H2/N2 plasma passivation process for poly-Si thin-film transistors (TFTs),” Solid State Electronics, vol. 38, no. 5, pp.1233-1238, 1995 [46] H. C. Cheng, F. S. Wang, and C. Y. Huang, “Effects of NH3 plasma passivation
on n-channel Polycrystalline silicon thin-film-transistors,” IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 64-68, 1997.
[47] H. N. Chern, C. L. Lee, and T. F. Lei, “H2/O2 plasma on polysilicon thin film transistor,” IEEE Electron Device Lett., vol. 14, pp.115-117, 1993.
[48] C. W. Lin, M. Z. Yang, C. C. Yeh, L. J. Cheng, T. Y. Huang, H. C. Cheng, H. C.
Lin, T. S. Chao and C. Y. Chang, “Effects of plasma treatments, substrates type, and crystallization methods on performance and reliability of low temperature polysilicon TFTs” in IEDM Tech. Dig., pp.305, 1999.
[49] I.-W. Wu, W. B. Jackson, T.-Y. Huang, A. G. Lewis and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,” IEEE Electron Device Lett., vol. 11, no. 4, pp. 167-170, 1990.
[50] M. Hack, A. G. Lewis, and I.-W. Wu, “Physical models for degradation effects in polysilicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 40, pp.
890-897, 1993.
[51] H. N. Chern, C. L. Lee, and T. F. Lei, “The effects of fluorine passivation on polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 41, pp.
698-702, May 1994.
[52] S. Maegawa, T. Ipposhi, S. Maeda, H. Nishimura, T. Ichiki, M. Ashida, O.
Tanina, Y. Inoue, T. Nishimura and N. Tsubouchi, “Performanc and reliability improvements in poly-Si TFT’s by fluorine implantation into gate poly-Si,”
IEEE Trans. Electron Devices, vol. 42, pp. 1106-1111, June 1995.
[53] J. W. Park, B. T. Ahn, and K. Lee, “Effects of F+ implantation on the characteristics of poly-Si films and low-temperature n-ch poly-Si thin-film transistors,” Jpn. J. Appl. Phys., vol. 34, pp. 1436-1441, Mar. 1995.
[54] C. H. Fan and M. C. Chen, “Performance improvement of excimer laser annealed Poly-Si TFTs using fluorine ion implantation” Electrochemical and Solid State Lett., vol. 5, pp. G75-G77, 2002.
[55] C. H. Kim, S. H. Jung, J. S. Yoo, and M. K. Han, “Poly-Si TFT fabricated by laser-induced in-situ fluorine passivation and laser doping,” IEEE Electron Device lett., vol. 22, pp. 396-398, Aug. 2001.
[56] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou, and N. Economou,
“Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures,” IEEE Trans. Electron Devices, vol. 39, pp. 598-606, Mar. 1992.
[57] F. V. Farmakis, J. Brini, G. Kamarinos and C. A. Dimitriadis, “Anomalous turn-on voltage degradation during hot-carrier stress in polycrystalline silicon thin-film transistors,” IEEE Electron Device Lett., vol. 22, no. 2, pp. 74-76, 2001.
[58] G. Fortunato, A. Pecora, G. Tallarida, L. Mariucci, C. Reita and P. Migliorato,
“Hot carrier effects in n-channel polycrystalline silicon thin-film transisitors: A correlation between off-current and transconductance variations,” IEEE Trans.
Electron Devices, vol. 41, no.3, pp. 340-346, 1994.
[59] B. Kaczer, R. Degraeve, M. Rasras, K. Van de Mieroop, P. J. Roussel, G..
Groeseneken, “Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability,” IEEE Trans. Electron Devices, vol. 49, no.3, pp.
500-506, 2002.
[60] J. S. Suehle, “Ultrathin gate oxide reliability: physical models, statistics, and characterization,” IEEE Trans. Electron Devices, vol. 49, no.6, pp. 958-971, 2002.
[61] M. Nafria, J. Sune, and X. Aymerich, “Exploratory observations of post-breakdown conduction in polycrystalline-silicon and metal-gated thin-oxide metal-oxide-semiconductor capacitors,” J. Appl. Phys., vol. 73, pp. 205-215, 1993.
[62] S. Lombardo, A. La Magna, C. F. Spinella, C. Gerardi, and F. Crupi,
“Degradation and hard breakdown transient of thin gate oxides in metal–SiO2–Si capacitors: Dependence on oxide thickness,” J. Appl. Phys., vol. 86, pp.
6382-6391, 1999.
[63] J. W. Hong, S. M. Shin, C. J. Kang, Y. Kuk, Z. G. Khim, and S. Park, “Local charge trapping and detection of trapped charge by scanning capacitance microscope in the SiO2/Si system,” Appl. Phys. Lett., vol. 75, pp. 1760-1762, 1999.
[64] C. Y. Nakakura, D. L. Hetherington, M. R. Shaneyfelt, P. J. Shea and A. N.
Erikson, “Observation of metal–oxide–semiconductor transistor operation using scanning capacitance microscopy,” Appl. Phys. Lett., vol. 75, pp. 2319-2321, 1999.
Chapter 2
CF
4Plasma Treatment on
Solid-Phase-Crystallized (SPC) Poly-Si TFTs
2.1 Introduction
In comparison with conventional a-Si TFTs, poly-Si TFTs have many advantages including high driving current, superior carrier mobility and great CMOS capability, which make the integration of switching-pixels and their peripheral driver circuits on a single glass substrate possible. It is known that trap states in the poly-Si can degrade the carrier transport and also increase the device leakage current [1], [2]. To eliminate these trap states has become the main topic for the current and future production of high performance poly-Si TFTs. Conventionally, hydrogen-based plasma treatment is the most popular method to passivate trap states in the current production [3], [4].
Although hydrogenation can eliminate the intra-grain and grain boundary trap states in the poly-Si film, the hydrogenated poly-Si TFTs suffer from a serious reliability issue, which can be attributed to the weak Si-H bonds.
Recently, several studies have demonstrated the use of fluorine (F) atoms to passivate the poly-Si films, which can improve both the performance and reliability of poly-Si TFTs, particularly when devices are under long-term electrical stress tests [5]-[9]. It is known that fluorine atoms can terminate dangling bonds and replace weak bonds in the grain boundaries and SiO2/poly-Si interface and thus reduce the trap states in the poly-Si channel. In addition, the strong Si-F bonds, more stable than Si-H bonds, can greatly improve the device reliability under an electrical stress.
Fluorine ion implantation (FII), the most adoptive fluorinating technique, has been widely investigated [5]-[8]. It is worth noting that ion implantation technique is not suitable for large-sized glass substrate. Moreover, a subsequent high temperature annealing to recover the defects created by FII is required in this method, which is not compatible with current production. Therefore, C. H. Kim et al. demonstrated the use of fluorinated oxide (SiOxFy) to replace FII, which can be served as a diffusion source [9]. However, this technique increases manufacturing processes since extra film deposition and etching are required.
To date, although the effects of fluorination have been clarified, there is still a lack of a process-compatible technique to effectively introduce fluorine atoms into poly-Si films. In this chapter, we proposed a new fluorine passivation technique by employing CF4 plasma treatment, which is a simply and efficient process. To avoid an unwanted etching effect, we controlled the RF to apply a very low power (5 Watts) to dissociate fluorine atoms, which were used to fluorinate the poly-Si film. Using this technique, the fluorinated poly-Si TFTs have been fabricated and the device characteristics and reliability were investigated.
2.2 Experimental
The schematic diagram of the fabrication process is illustrated in Fig. 2.1. First, a 100-nm-thick amorphous-silicon layer was deposited on thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) at 550°C. Subsequently, solid phase crystallization (SPC) was performed at 600°C for 24 hours in N2 ambient for the phase transformation. Individual active regions were then patterned and defined. After a standard RCA cleaning, samples were subjected to the CF4 plasma treatment, conducted in a plasma-enhanced chemical vapor deposition
(PECVD) system at 350°C for 15 seconds, with a pressure of 200 mTorr and a power of 5 Watts. Then, a 50-nm-thick tetraethyl orthosilicate (TEOS) oxide was deposited to serve as the gate insulator and a 200-nm-thick poly-Si film was deposited and patterned for the gate electrode. A self-aligned phosphorous ion implantation was preformed with the dosage and energy of 5×1015 cm-2 and 40 KeV, respectively. The dopant activation was performed at 600°C furnace annealing at N2 ambient for 24 hours, followed by a deposition of the passivation layer and a definition of contact holes. Finally, a 500-nm-thick Al electrode was deposited and patterned. The control samples were prepared without the fluorinating process. To concentrate on revealing the fluorine passivation effects of the CF4 plasma treatment, none of additional hydrogenation process was performed on the control samples. The electrical and reliability characteristics were performed by using HP 4156B.
2.3 Results and Discussion
2.3.1 Comparison of Device Characteristics
Figure 2.2(a) shows the transfer characteristics (ID-VGS) for the control and fluorinated poly-Si TFTs. The measurements were performed at two different drain voltages of VDS = 0.1 V and 5 V. The parameters of the devices, including the threshold voltage (Vth) and subthreshold swing (S.S.), maximum On-current (Ion) and the minimum Off-current (Ioff) were measured at VDS = 5 V. The threshold voltage is defined as the gate voltage required to achieve a normalized drain current of ID = (W/L) ×100 nA. Accordingly, the performance of the fluorinated poly-Si TFT is significantly improved. The Vth and S.S. of the fluorinated poly-Si TFT were found to be 8.3 V and 1.73 V/dec., which are superior to those of the control one (12 V and 2.06 V/dec., respectively). It’s known that the Vth and S.S. are strongly influenced by
the deep trap states, associated with dangling bonds in the channel, which have energy states near the middle of the silicon band gap. Therefore, one can infer that CF4
plasma treatment can terminate the dangling bonds in the poly-Si and SiO2/poly-Si interface. Additionally, the Ion and On/Off current ratio of the fluorinated TFT are also better than those of the control TFT.
The minimum Off-current of the fluorinated device is nearly unsuppressed, which is consistent with the previous reports by Chern et al. [6] and Kim et al. [9]
However, while the applied gate voltage was toward more negative (VGS < -2 V ), the fluorinated poly-Si TFT shows smaller leakage current compared with that of the control TFT. It is known that under a high electric field leakage current of the poly-Si TFT mainly comes from the trap-assisted band to band tunneling near the drain edge [10]. This observation suggests that there must be fewer trap states existed in the fluorinated poly-Si TFT, and thus the leakage current under a high electric field is reduced.
Figure 2.2(b) shows field-effect mobility versus the gate voltage of control and fluorinated poly-Si TFTs. The field-effect mobility was calculated from the value of transconductance at VDS = 0.1V. The fluorinated poly-Si TFT shows approximately 22.8 % enhancement in the maximum field-effect mobility. Note that the field-effect mobility is significantly affected by the tail states near the band edge, which is resulted from the strain bonds in poly-Si and SiO2/poly-Si interface [1]. These results imply that the CF4 plasma treatment may not only terminate the dangling bonds, but also relieve the strain bonds. The extracted device parameters are listed in Table 2.1.
2.3.2 Extraction of Trap State Density
The grain boundary trap state densities (QT) of the conventional and fluorinated poly-Si TFTs were estimated by Levison and Proano method [11], [12]. Figure 2.3
exhibits the plots of the ln[ID/(VGS-VFB)] versus 1/(VGS-VFB)2 curves at low VDS and high VGS. The QT was extracted from the slopes of these curves. The fluorinated poly-Si TFT exhibits a QT of 1.32×1013 cm-2, whereas the control TFT has 1.67×1013 cm-2. This result implies that the CF4 plasma treatment can terminate the grain boundary trap states in the poly-Si film. To further study the fluorine passivation effect near the interface, the effective interface trap states densities (NT) near the
exhibits the plots of the ln[ID/(VGS-VFB)] versus 1/(VGS-VFB)2 curves at low VDS and high VGS. The QT was extracted from the slopes of these curves. The fluorinated poly-Si TFT exhibits a QT of 1.32×1013 cm-2, whereas the control TFT has 1.67×1013 cm-2. This result implies that the CF4 plasma treatment can terminate the grain boundary trap states in the poly-Si film. To further study the fluorine passivation effect near the interface, the effective interface trap states densities (NT) near the