Chapter 2 CF 4 Plasma Treatment on Solid-Phase-Crystallized (SPC) Poly-Si
2.3 Results and discussion
2.3.4 Device Reliability
Additionally, the hot carrier stress was carried out to examine the reliability of the device. The device degradation under hot carrier stress can be attributed to two mechanisms: oxide trap charges and the creation of trap states in the poly-Si. This can be attributed to channel-hot-electron (CHE) and self-heating (SH) phenomenon. For
CHE, electrons were injected and trapped in the gate oxide; then, the carrier flow in the channel is disturbed, therefore reducing the Ion. SH-induced damage is due to the large Joule heat, resulted from a high drain current [15], [16]. Because TFTs are fabricated on a poor thermal-conducting substrate, devices can reach a very high temperature during operation. Such high temperature enhances bonds breaking to generate trap states in the poly-Si, and thus degrade the TFT performance.
Figure 2.8 shows the variation of On-current under a hot carrier stress. The stress condition is performed at VDS=30V and VGS=30V for 4500 s. The variation in Ion is defined as (Ion,stressed–Ion,initial)/ Ion,initial×100%, where the Ion,initial and Ion,stressed are the measured Ion prior to and after the electrical stress. As can be seen, the fluorination process can greatly alleviate the On-current degradation under a hot carrier stress. We deduce that the the interface quality is greatly improved because of the fluorine incorporation after CF4 plasma treatment,. The improved interface can result in a great enhancement of gate oxide integrity [17]. Moreover, Si-F bonds are form to replace weak bonds in the poly-Si, and therefore the bonds breaking can be eliminated. Hence, damage caused by channel-hot-electron and self-heating was suppressed for the fluorinated sample. As a result, device reliability was great improved for the fluorinated poly-Si TFT.
2.4 Summary
A new fluorinating technique of SPC poly-Si TFTs by employing CF4 plasma treatment is demonstrated. Using this technique, significant improvements in the performance of fluorinated poly-Si TFTs have been presented. A steeper S.S., smaller Vth and better ON/OFF current ratio can be obtained. Moreover, the fluorinated poly-Si TFT shows approximately 22.8 % enhancement in the maximum field-effect
mobility. These results can be attributed to the reduction of the trap states in the poly-Si and the SiO2/poly-Si interface. Moreover, the CF4 fluorinating process also improves the hot-carrier immunity. It is concluded that CF4 plasma treatment can provide a simple, effective and process-compatible method to introduce fluorine atoms into poly-Si film to fabricate high-performance and high-reliability poly-Si TFTs.
References:
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(a) Thermal oxidation, depositing amorphous-silicon.
(b) Recrystallization by SPC, defining active region and CF4 plasma treatment.
(c) Deposition of TEOS gate oxide by PECVD and poly-Si gate by LPCVD.
(100) N-Type Si Wafer Buffer Thermal Oxide
Poly-Si Channel
(100) N-Type Si Wafer Buffer Thermal Oxide
TEOS Oxide Poly-Si Gate
Poly-Si Channel
(100) N-Type Si Wafer Buffer Thermal Oxide
a-Si
CF
4Plasma Treatment
(d) Defining the gate electrode and self-aligned S/D implantation.
(e) Dopant activation by furnace annealing.
(100) N-Type Si Wafer Buffer Thermal Oxide
Poly-Si Channel
Phosphorous ion implantation
(100) N-Type Si Wafer Buffer Thermal Oxide
Poly-Si
n+ n+
(f) Depositing passivation oxide, opening contact holes and patterning metal pads.
Fig. 2.1 Schematic diagram of fabrication process for SPC poly-Si TFTs with CF4 plasma treatment.
(100) N-Type Si Wafer Buffer Thermal Oxide
Poly-Si
Fig. 2.2(a) Transfer characteristics of the control and fluorinated SPC poly-Si TFTs
Drain Current, I D (A)
Gate Voltage, V
GS (V)
W/L = 40µm/ 10µm
Oxide Thickness = 50nm
CF4 Flow Rate = 20 sccm Chmber Pressure = 200 mT RF Power = 5 W
Treatment Time = 15 s
Fig. 2.2(b) Field-effect mobility of the control and fluorinated SPC poly-Si TFTs with VDS=0.1V.
0 5 10 15
0 5 10 15 20 25 30
Conventional Fluorinated
F ie ld- E ff e c t M obi li ty (c m
2/ V s )
Gate Voltage, V
GS
(V)
W/L = 40µm/ 10µm
Oxide Thickness = 50nm
VDS = 0.1 V
Table 2.1 Comparison of device characteristics of the control and fluorinated SPC poly-Si TFTs.
SPC Poly-Si TFTs Conventional Fluorinated
Vth (V) 12 8.3
S.S.(V/dec.) 2.06 1.73
µeff (cm2/V.s) 10.5 13.6
Ion (µA) 180 279
Ioff (pA) 38.7 40.7
On/Off Ratio(106) 4.65 6.85
QT (1013 cm-2) 1.67 1.32
NT (1013 cm-2) 1.45 1.21
-20 -18 -16 -14 -12
0 0.002 0.004 0.006 0.008 0.01
Conventional Fluorinated
In [ I DS/(V GS-V FB)] (Ω-1 )
1/ (V
GS-V
FB)2 (V-2)
N
T=1.67*10
13cm
-2N
T=1.32*10
13cm
-2Fig. 2.3 ln[ID/(VGS-VFB)] versus 1/(VGS-VFB)2 curves at VDS = 0.1V and high VGS for control and fluorinated SPC poly-Si TFTs.
(a) Conventional poly-Si
(b) Fluorinated poly-Si
Fig. 2.4 SIMS analyses of (a) control and (b) fluorinated SPC poly-Si films.
0
(a) Without CF4 plasma
(b) With CF4 plasma
Fig. 2.5 Schematic cross-sectional view of SiO2/poly-Si interface (a) without CF4 plasma and (b) with CF4 plasma treatment.
O
0 100 200 300 400 500 600 700
0 5 10 15 20 25
Fluorinated Conventional
Drain Curr ent, I
D( µA)
Drain Voltage, V
DS
(V)
W/L=40µm/10µm TOX=50nm
VGS=25V
VGS=15V
VGS=10V
Fig. 2.6 Output characteristics of the control and fluorinated SPC poly-Si TFTs with VGS= 10V, 15V and 25V.
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-10 -5 0 5 10 15 20
Fluorinated Conventional
E
a(eV)
Gate Voltage (V)
W /L = 40µm /10µm VDS = 1 V
Fig. 2.7 Activation energy versus gate voltage of the control and fluorinated SPC poly-Si TFTs.
-6 -5 -4 -3 -2 -1 0
0 1000 2000 3000 4000 5000
Conventional Fluorinated
On-cu rrent V a ri ation (% )
Stress Time (s)
Stress condition:
VDS=V
GS=30V
Fig. 2.8 On-current variation as a function of stress time under a hot carrier stress of the control and fluorinated SPC poly-Si TFTs.
Chapter 3
Improved Performance and Reliability of Excimer-Laser-Annealed (ELA) Poly-Si TFTs
with CF
4plasma treatment
3.1 Introduction
Poly-Si TFTs have been used to integrate driving circuits and pixel elements on one glass substrate in active matrix liquid crystal displays (AM-LCDs) [1]. Recently, much attention has been paid on their potential to realize the System-on-Panel (SOP).
To accomplish this goal, high-performance poly-Si TFTs with excellent device reliability are required. Excimer laser annealing (ELA) has been utilized to gain the device performance of poly-Si TFTs [2], [3]. ELA process can enlarge poly-Si grain size to enhance carrier mobility of TFT devices. Hydrogenation process is also used to terminate the trap states in the ELA-processed poly-Si. Unfortunately, although the device performance can be improved due to the hydrogen termination, hydrogenated poly-Si TFTs have a very serious instability issue due to the Si-H bonds breaking under an electrical stress [4], [5]. To solve this problem, it has been reported that fluorine can both terminate the trap states of the poly-Si, and maintain the device characteristics under a long-term electrical stress [6]-[11]. This reliability improvement is believed to be due to the high binding energy of Si-F bonds.
It is known that conventional ion implantation may be not so suitable for large-sized glass substrate. Moreover, a subsequent high temperature annealing is
required to activate the fluorine atoms and to recover the implantation-induced defects, which is not compatible with the current low-melting point glass substrates. Therefore, fluorinated oxide (SiOxFy) films have been proposed to serve as a fluorine diffusion source [10]. However, extra film deposition and etching are required. Low process-temperature and good process-compatibility are demanded in current TFTs production. For these reasons, a fluorine-based plasma treatment seems to be a very good solution to fluorinate ELA poly-Si TFTs.
In this chapter, ELA poly-Si TFTs are demonstrated with a novel CF4 plasma treatment technique. This technique is a simple and process-compatible method to effectively reduce trap states of ELA poly-Si and thus improve the device performance. Moreover, to investigate the reliability of the CF4 plasma-treated ELA poly-Si TFTs, hot-carrier and self-heating stress are carried out. Using this technique, high-performance and high-reliability poly-Si TFTs can be achieved.
3.2 Experimental
The schematic diagram of fabrication processes is illustrated in Fig. 3.1. First, a 100-nm-thick amorphous silicon layer was deposited on thermally oxidized Si wafer by dissociation of SiH4 gas in a low-pressure chemical vapor deposition (LPCVD) system at 550 . ℃ Next, a semi-Gaussian-shaped KrF excimer laser (λ= 248 nm) with an energy density of 420 mJ/cm2 was performed for the phase transformation from amorphous-Si to poly-Si. The average grain size of the poly-Si is approximately 300 nm. Individual active regions were then patterned and defined. After RCA clean, the samples were subjected to the CF4 plasma treatment, conducted in a plasma-enhanced chemical vapor deposition (PECVD) system at 350 for 15 seconds, under a ℃ pressure of 200 mTorr and a power of 10 Watts. Then, a 100-nm-thick TEOS oxide
and a 200-nm-thick poly-Si were deposited to serve as the gate dielectric and the gate electrode. A self-aligned phosphorous ion implantation was preformed with the dosage and energy of 5×1015 cm-2 and 40 keV, respectively. The dopant activation was performed by excimer laser annealing (ELA), followed by a deposition of passivation layer and the definition of contact holes. Finally, a 500-nm-thick Al electrode was deposited and patterned. For comparison, the control sample was prepared without the CF4 plasma treatment process. No hydrogenation process was carried out on these devices. The dimensions of the transistors tested in this study are W/L = 40/20 µm.
3.3 Results and Discussion
3.3.1 Material Analysis
To exclude the plasma cleaning effect, the surface contaminations of the poly-Si samples after RCA clean were examined using Total Reflection X-Ray Fluorescence (TRXRF), and the results show that no significant surface contamination were detected. Also, the thickness variations of the poly-Si films before and after CF4
plasma treatment measured using ellipsometer were within 5 %. Therefore, both the plasma cleaning effect and the poly-Si thinning by the CF4 plasma treatment are eliminated.
Figure 3.2 exhibits the SIMS profiles of the control and CF4 plasma-treated poly-Si films. As can be seen, lots of fluorine atoms were introduced into the SiO2/poly-Si interface by using the CF4 plasma treatment. We believe that these piled-up fluorine atoms provide an effective trap states passivation, because the channel is formed near the interface. Moreover, Electron Spectroscopy for Chemical Analysis (ESCA) was carried out to identify the incorporation of fluorine in the ploy-Si film with the CF4 plasma treatment, as shown in Fig. 3.3. A strong signal of F
bonds is detected in the CF4 plasma treated sample. Also, Fourier Transform Infrared Spectroscopy (FTIR) spectra of the conventional and CF4 plasma-treated poly-Si films are also shown in Fig. 3.4. The spectra exhibit absorption peaks corresponding to Si-F bonds and Si-O bonds centered at round 940 and 1100 cm-1. The strong peak of Si-O bond is related to the SiO2 substrate. These results indicate that by employing this CF4
plasma treatment technique not only the fluorine atoms were introduced into the poly-Si but also the Si-F bonds were formed in the SiO2/poly-Si interface.
3.3.2 Device Characteristics
The transfer characteristics (ID-VGS) and field-effect mobility (µeff) versus the gate voltage of devices are shown in Fig. 3.5. The measurements were performed at VDS = 0.5 V and 5 V. The threshold voltage (Vth) was defined as the gate voltage required to achieve a normalized drain current of ID = (W/L) × 100 nA at VDS = 5 V. As can be seen, excellent device characteristics are observed for the CF4 plasma-treated TFT. The Vth and the subthreshold slope (S.S.) of the CF4 plasma-treated TFT are 4.35 V and 1.28 V/dec., respectively, which are superior to 5.75 V and 1.92 V/dec. of the control TFT. The leakage current of the CF4 plasma treated TFT is more than one order in magnitude lower than that of the control TFT, especially at VGS = -5V.
Moreover, the corresponding On/Off current ratio of the CF4 plasma-treated TFT is approximately 8 times larger than that of the control one. Also, the CF4 plasma-treated TFT has an about 50% enhancement in the maximum field-effect mobility (µeff). The comparison of the extracted device parameters for the control TFT and the CF4
plasma-treated TFT is listed in Table 3.1. We believe that these significant device characteristic improvements are due to the effective fluorine passivation effect in poly-Si TFTs by using the CF4 plasma treatment. Figure 3.6 shows the output characteristics (I -V ) of the control and the CF plasma treated poly-Si TFTs. As can
be seen, the driving currents of the CF4 plasma-treated poly-Si TFT increase dramatically due to the fluorine passivation. The driving current at VGS = 17.5 V and 25 V with VDS = 20 V increase 176.3 % and 92.6 %, respectively. Therefore, the output characteristics can be greatly improved with the CF4 plasma treatment.
It is worth noting that compared with SPC poly-Si TFTs with CF4 plasma treatment (Chapter 2), we found that the Vth shift was smaller and the leakage current improvement was more significant in ELA poly-Si TFTs. We attribute these to the reasons discussed below. Considering the SPC poly-Si TFTs, during the long-time source/drain activation process (600℃ for 24 hours), we believe that fluorine atoms would be evolved and diffused into the gate oxide to induce oxide trap charges, whereas, for in ELA poly-Si TFTs, the gate oxide above the poly-Si channel would screen the laser energy during the source/drain activation. Therefore, few fluorine atoms were evolved in ELA poly-Si TFTs. As a result, the SPC poly-Si TFTs with CF4
plasma treatment show more Vth shift than ELA poly-Si TFTs .
On the other hand, there are two types of tarp states in poly-Si affecting the carrier transport. One is the grain boundary trap states, the other is interface states.
For the ELA poly-Si TFTs, the grain boundary trap states are fewer than those in the SPC poly-Si TFTs, so the interface states dominate the device performance. However, for SPC poly-Si TFTs, grain boundary trap states dominate. With CF4 plasma treatment, the pilled-up fluorine atoms near the interface provide great interface state passivation. Therefore, the device characteristics of ELA poly-Si TFTs including the Ion, Ioff, and µef are improved more significantly than those in SPC poly-Si TFTs.
3.3.3 Extraction of Trap State Density
In order to verify the fluorine passivation effect of the devices, the effective trap states densities (Nt) were calculated from the S.S.. the Nt can be expressed as [11]:
Nt = [(S.S./ln 10)(q / kT)-1)](Cox/q) (1)
where the Cox is the capacitance of the gate oxide. The Nt of the control TFT and the CF4 plasma treated TFT are 6.72 × 1012 cm-2 and 4.42 × 1012 cm-2, respectively.
The Nt values reflect both interface sates and grain boundary trap states near the SiO2/poly-Si interface. Therefore, those traps near the SiO2/poly-Si interface were effectively terminated by fluorine atoms using CF4 plasma treatment. Also, the grain boundary trap densities (QT) of the devices were evaluated using Proano’s method [12], [13]. As shown in Fig. 3.7, the QT of the CF4 plasma-treated TFT and the control TFT are 3.47×1012 cm-2 and 4.11×1012 cm-2, respectively. This proves that the grain boundaries trap states of the poly-Si TFT were effectively reduced with the CF4
plasma treatment.
To clarify how the fluorine passivate the trap states of poly-Si TFTs, the density of states (DOS) in the energy band gap were calculated using field-effect conductance method [14]. As shown in Fig. 3.8, both deep states and tail states are significantly reduced in the CF4 plasma treated TFT. We deduce that for the control TFT, there exist many dangling bonds and strain bonds at the SiO2/poly-Si interface, resulting in high deep states and tail states [15], [16]. However, for the CF4 plasma treated TFT, fluorine atoms were introduced into the SiO2/poly-Si network to terminate the dangling bonds, release the strain bonds and form the S-F bonds, reducing the trap states and resulting in a great improvement of the device characteristics. This fluorine termination effect in the SiO2/poly-Si interface network has been discussed in Chapter 2 and has been schematically plotted in Fig. 2.5.
3.3.4 Gate oxide integrity
It is known that the oxide integrity is an important challenge for law temperature poly-Si TFTs. It has been reported that fluorine incorporation can improve the
integrity of the gate dielectric [17], [18]. The effect of the CF4 plasma treatment on the gate oxide of the poly-Si TFT has been also investigated. Figure 3.9 shows the cumulative distributions of the time-zero-dielectric-breakdown (TZDB) characteristics and leakage current of the gate oxides with and without CF4 plasma treatment. As can be seen, the CF4 plasma treated oxide exhibits approximately 65 % enhancement in the breakdown voltage compared to the control. Also, the leakage current of the gate oxide is significantly suppressed by using CF4 plasma treatment.
These improved breakdown voltage and leakage current can be attributed to the formation of Si-F bonds to replace weak bonds at the SiO2/poly-Si interface [18].
Those results prove that the CF4 plasma treatment can effectively improve in both gate dielectric integrity and the device performance of poly-Si TFT due to the fluorine termination.
3.3.5 Device Reliability
The instability issue of devices is the bottleneck for poly-Si TFT circuits developing. To investigate the reliability of the CF4 plasma-treated poly-Si TFT, two accelerating electrical stress tests were carried out. One is hot-carrier stress (HCS) and the other is self-heating stress (SHS), as shown in Fig. 3.10. The HCS, which occurs at Vth ≤ VGS ≤ VDS, have been reported can cause the most severe device degradation in poly-Si TFTs. The HCS-induced damage is attributed to the creation of numerous trap states near the drain side, and the degradation rate depends on the strength of the drain
The instability issue of devices is the bottleneck for poly-Si TFT circuits developing. To investigate the reliability of the CF4 plasma-treated poly-Si TFT, two accelerating electrical stress tests were carried out. One is hot-carrier stress (HCS) and the other is self-heating stress (SHS), as shown in Fig. 3.10. The HCS, which occurs at Vth ≤ VGS ≤ VDS, have been reported can cause the most severe device degradation in poly-Si TFTs. The HCS-induced damage is attributed to the creation of numerous trap states near the drain side, and the degradation rate depends on the strength of the drain