Chapter 4 Performance and Reliability of Poly-Si TFTs on FSG Buffer Layer
4.3.2 Device Uniformity
Fig. 4.6 displays the statistical distributions of the field-effect mobility (µeff) and the leakage current (Ioff) of the poly-Si TFTs fabricated on different buffer layers. The vertical bars in the figure indicate the minimum and maximum values of the devices characteristics and the squares present the average values. The average values of the µeff
for the control, FSG1, FSG2 and FSG3 samples were 57.7, 66.7, 63.9 and 45.2 with standard deviations of 4.05, 2.98, 3.09 and 4.15, respectively. This tendency indicates that with moderate fluorine content in FSG layers the average values and the deviations of µeff
can be greatly improved. Also, the average values of the Ioff for the control, FSG1, FSG2, and FSG3 samples were 6.8×10-8, 7.8× 10-9, 1.3×10-9 and 1.8×10-9 with standard deviations of 8.14×10-8, 2.46× 10-9, 6.55×10-10 and 1.93×10-9, respectively. The uniformity of the poly-Si TFTs is strongly affected by the random distribution of grain boundaries. Therefore, using fluorine to terminate those trap states can effectively alleviate the influence of grain boundaries.
4.3.3 Device Reliability
Hot-carrier-stress was performed at VDS = 20 V and VGS = 10 V for 1000s to investigate the device reliability. Fig. 4.7 plots the variations of On-current (Ion), threshold voltage (Vth) and µeff over hot carrier stress time. The variations of Ion, Vth and µeff were defined as (Ion,stressed–Ion,0)/ Ion,0×100 %, (Vth,stressed–Vth,0)/Vth,0×100 % and (µeff,stressed–µeff,0)/ µeff,0×100 %, respectively, where Ion,0, Vth,0, µeff,0 and Ion,stressed, Vth,stressed,
µeff,stressed, represent the measured values before and after stress. Notably, the control shows relatively large variations in both Vth and µeff after 1000s stress, whereas the FSG2 stays almost unchanged. These results imply that poly-Si TFTs fabricated on the FSG layer greatly reduced the device degradation under hot carrier stress, which is due to the formation of the Si-F bonds.
Since the calculated percentages of F content in the FSG layers are 2%, 4% and 7%
for FSG1, FSG2, and FSG3, respectively, we deduce based on the above experimental results that the trap states can be effectively terminated when the fluorine content in the FSG is above 2%; while the absorbed moisture in the FSG as the content is above 4%
starts to induce visible corrosion of the poly-Si structures after competing with the trap states termination. Definitely, the corrosion becomes more severe as the content reached 7%. As a result, the optimized condition of fluorine content of FSG is probably within 2% to 4%.
4.4 Summary
A novel fabricating scheme for poly-Si TFTs on an FSG buffer layer is proposed.
Significant improvements in the device performance and uniformity have been successfully demonstrated with fluorine incorporation in the poly-Si layer. The incorporation of fluorine also promotes the hot-carrier immunity. Fabricating poly-Si TFTs on FSG buffer layers with appropriate fluorine contents (2% to 4%) improves not only the electrical performance, uniformity, but also the device reliability.
References:
[1] T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, “Low-temperature fabrication of high-mobility poly-Si TFT’s for large-area LCD’s,” IEEE Trans. Electron Devices, vol. 36, pp. 1929-1933, Sept. 1989.
[2] G. K. Guist and T. W. Sigmon, “High-performance thin-film transistors fabricated using excimer laser processing and grain engineering,” IEEE Trans. Electron Devices, vol. 45, pp. 925-932, Apr. 1998.
[3] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device lett., vol. 12, pp. 181-183, May 1991.
[4] I. W. Wu, W. B. Jackson, T. Y. Huang, A. G. Lewis, and A. Chiang, “Mechanism of device degradation in n- and p-channel polysilicon TFT’s by electrical stressing,”
IEEE Electron Device lett., vol. 11, pp. 167-170, Apr. 1990.
[5] E. Fujii, K. Senda, F. Emoto, A. Yamamoto, A. Nakamura, Y. Uemoto, and G. Kano,
“A leaser-recrystallization technique for silicon-TFT integrated circuits on quartz substrates and its application to small-size monolithic active-matrix LCD’s,” IEEE Trans. Electron Devices, vol. 37, pp. 121-127, Jan. 1990.
[6] M. Cao, S. Talwar, K. J. Kramer, T. W. Sigmon, and K. C. Saraswat, “ A high-performance polysilicon thin-film transistor using XeCl excimer laser crystallization of pre-patterned amorphous Si films,” IEEE Trans. Electron Devices, vol. 43, pp. 561-567, Apr. 1996.
[7] K. Kitahara, A. Moritani, A. Hara, and M. Okabe, “Micro-scale characterization of crystalline phase and stress in laser-crystallized poly-Si thin films by Raman spectroscopy,” Jpn. J. Appl. Phys., vol. 38, pp. L1312-1314, 1999.
[8] S. Higashi, N. Ando, K. Kamisako, and T. Sameshima, “Stress in
pulsed-laser-crystallized silicon films,” Jpn. J. Appl. Phys., vol. 40, pp. 731-735, 2001.
[9] H. N. Chern, C. L. Lee, and T. F. Lei, “The effects of fluorine passivation on polysilicon thin film transistors,” IEEE Trans. Electron Devices, vol. 41, pp. 698-702, May 1994.
[10] S. Maegawa, T. Ipposhi, S. Maeda, H. Nishimura, T. Ichiki, M. Ashida, O. Tanina, Y. Inoue, T. Nishimura and N. Tsubouchi, “Performance and reliability improvement in poly-Si TFT’s by fluorine implantation into gate poly-Si,” IEEE Trans. Electron Devices, vol. 42, pp. 1106-1112, June 1995.
[11] J. W. Park, B. T. Ahn and K.Lee, “Effects of F+ implantation on the characteristics of poly-Si films and low-temperature n-ch poly-Si thin-film transistors,” Jpn. J. Appl.
Phys., vol. 34, pp. 1436-1441, Mar. 1995.
[12] C. H. Kim, S. H. Jung, J. S. Yoo, and M. K. Han, “Poly-Si TFT fabricated by laser-induced in-situ fluorine passivation and laser doping,” IEEE Electron Device lett., vol. 22, pp. 396-398, Aug. 2001.
[13] Y. Mitani, H. Satake, Y. Nakasaki, and A. Toriumi, “Improvement of charge-to-breakdown distribution by fluorine incorporation into thin gate oxides,”
IEEE Trans. Electron Devices, vol. 50, pp. 2221-2226, Nov. 2003.
[14] R. E. Proano, R. S. Misage, and D. G. Ast, “Development and electrical properties of undoped polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 36, pp. 1915-1922, Sep. 1989.
[15] H. Miyajima, R. Katsumata, Y. Nakasaki, Y. Nishiyama, and N. Hayasaka, “Water absorption properties of fluorine-doped SiO2 films using plasma-enhanced chemical vapor deposition,” Jpn. J. Appl. Phys., vol. 35, pp. 6217-6225, 1996.
[16] G. Passemard, P. Fugier, P. Nobl, F. Pries, and O. Demolliens, “Study of fluorine stability in fluoro-silicate glass and effects on dielectric properties,” Microelectronic
Engineering, vol. 33 pp. 335-342, 1997.
Thermal Oxide Si Wafer
(a) Thermal oxidation by furnace.
Thermal Oxide Si Wafer FSG Layer
(b) FSG layer deposition by PE-CVD.
Thermal Oxide Si Wafer
FSG Layer
a-Si
(c) Amorphous Si (a-Si) deposition by LPCVD.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel
(d) Recrystallization of a-Si into poly-Si by ELA and defining active region d.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel TEOS Gate Oxide
Poly-Si Gate
(e) Deposition of TEOS gate oxide and poly-Si gate.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si Channel
Phosphorous self-aligned ion implantation
(f) Defining gate electrode and self-aligned phosphorous ion implantation.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si
n
+n
+n
+(g) Dopant activation by ELA.
Thermal Oxide Si Wafer
FSG Layer
Poly-Si
n
+n
+n
+(h) Deposition of passivation oxide, opening contact holes and defining metal pads.
Fig. 4.1 Schematic diagram of the fabrication process for the proposed poly-Si TFTs with a FSG buffer layer.
Table 4.1 Conditions of gas flow rates to deposit FSG buffer layers.
Fig. 4.2 SIMS profiles of the as-deposited FSG samples.
10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
-10 -5 0 5 10 15 20 25
FSG3 Control FSG1 FSG2
Dr a in Curr e n t, I
D(A )
Gate Voltage, V
G
(V)
V
DS=5V
W/L = 40µm/10µm
Oxide thickness = 100nm
Fig. 4.3 Transfer characteristics of the conventional and the proposed poly-Si TFTs with different FSG layers.
1017 1018 1019 1020 1021
0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7
Control FSG1 FSG2 FSG3
F C o n c en tr a tion ( c m
-3)
Depth ( µm )
Oxide Poly-Si Buffer
Oxide Substrate
Fig. 4.4 SIMS profiles of the conventional and the proposed poly-Si TFTs with different FSG layers.
-17 -16 -15 -14 -13 -12
0 0.005 0.01 0.015 0.02 0.025
Control FSG1 FSG2 FSG3
y = -12.252 - 392.15x R= 0.99345 y = -12.109 - 188.04x R= 0.99922 y = -11.714 - 193.92x R= 0.99991 y = -11.827 - 235.27x R= 0.999
ln [ I DS/(V GS-V FB) ] (Ω-1 )
1/(VGS-V
FB)2 (V-2) Nt=5.64x1012cm-2
Nt=3.91x1012cm-2 Nt=3.97x1012cm-2
Nt=4.01x1012cm-2
Fig. 4.5 Trap state density extraction of the conventional and proposed poly-Si TFTs with different FSG layers.
Table 4.2 Comparison of device characteristics of the conventional and the proposed poly-Si TFTs (W/L = 40μm/10μm).
Poly-Si TFTs Control FSG1 FSG2 FSG3
Vth (V) 5.07 4.77 4.82 4.96
S.S (V/dec.) 1.55 1.42 1.44 1.45
μeff (cm2/Vs) 57.5 69.1 65.4 43.1
Maximum Ion
(A) 4.33 ×10-4 7.01 ×10-4 6.39 ×10-4 5.11 ×10-4 Minimum Ioff
(A) 1.45 ×10-10 1.12 ×10-10 9.73 ×10-11 8.79 ×10-11 On/Off Ratio 2.98 ×106 6.26 ×106 6.56 ×106 1.12 ×106
Ioff @
VG = -10V(A) 1.14 ×10-7 3.08 ×10-9 3.32 ×10-10 9.95 ×10-10 NT(cm-2) 5.64 ×1012 3.91 ×1012 3.97 ×1012 4.01 ×1012
Buffered FSG Oxide
Fig. 4.6 Distribution of (a) filed-effect mobility and (b) leakage current of the poly-Si TFTs on different buffer layers. The vertical bars indicate the minimum and maximum values of the device characteristics and the squares are the average values.
ID @ VDS = 5 V; VGS = -10 V
-35
(a) On-current degradation with stress time
0
(b) Threshold voltage degradation with stress time
-70 -60 -50 -40 -30 -20 -10 0 10
0 200 400 600 800 1000
Control FSG1 FSG2 FSG3 µ eff Variations (%)
Stress time (s) Stress condition
VG=10V ; V
D=20V
(c) Field-effect mobility degradation with stress time
Fig. 4.7 (a) On-current, (b) threshold voltage and (c) field-effect mobility degradation as a function of stress time under hot-carrier stress.
Chapter 5
Drain/Gate-Voltage-Dependent On-Current and Off-Current Instabilities in Poly-Si TFTs under
Electrical Stress
5.1 Introduction
Poly-Si TFTs have higher driving current and greater carrier mobility compared with conventional a-Si TFTs [1] [2]. However, due to low-temperature processes, numerous defects in grains and grain boundaries of the poly-Si channel degrade device characteristics. Traps resulted from these defects raise the potential barrier for carrier transport in the On-state and enhance the leakage current by the field-enhanced emission in the Off-state [3], [4]. Moreover, these defects are also responsible for the instability of device characteristics, particularly under electrical stress tests [5]. It is known that studying the instabilities in the device characteristics of poly-Si TFTs is more complicated than doing that in single-crystal metal-oxide-semiconductor field-effect transistors (MOSFETs), which is due to the random distribution of grain boundaries in the poly-Si and the poor quality of the gate oxide as well as the oxide/poly-Si interface. From the previous reports in studying single-crystal MOSFETs, we believe that the amounts and the spatial distributions of the trap states (or charges) in the gate oxide and in the poly-Si play important roles in the instabilities of poly-Si TFTs.
On-current (Ion) and Off-current (Ioff) are two of the most important parameters in designing poly-Si TFT circuits, which are related to the driving capacity and the
charge storage. Also, they are very sensitive to the oxide trap charges and trap states (or charges) in the poly-Si. Their instabilities, with regard to the electrical stress, have constrained poly-Si TFT applications. Although several groups have studied the variations in the device characteristics of poly-Si TFTs in the On-state or Off-state after the electrical stress separately, a comprehensive mechanism for the degradation of both Ion and Ioff under various stress conditions is not yet well known [6]-[8].
In this chapter, we adopt a new strategy for investigating the mechanism of the Ion and Ioff instabilities in poly-Si TFTs. On the basis of correlations between the trap states (or charges) and the applied drain/gate voltages, the effects of the trap states (or charges) on the variations of Ion and Ioff are investigated. From systematic measurements, a comprehensive model is proposed, which thereby extends our understanding of the correlation between the defects and the instabilities of device characteristics in poly-Si TFTs.
5.2 Experimental
The device structure used in this study is illustrated schematically in Fig. 5.1(a).
N-channel non-LDD (non-lightly-doped-drain) excimer-laser-annealed poly-Si TFTs were used in this study. First, a 100-nm-thick amorphous silicon layer was deposited on a thermally oxidized Si wafer by LPCVD. Subsequently, a semi-Gaussian-shaped KrF excimer laser with a wavelength of 248 nm was used to induce phase transformation. Individual active regions were then patterned and defined. After a 100-nm-thick TEOS oxide was deposited by PECVD at 350°C, a 200-nm-thick poly-Si film was deposited and patterned. Next, a self-aligned phosphorous ion implantation was conducted at a dose of 5×1015 cm-2. The dopant was activated by excimer laser annealing, followed by ammonia plasma hydrogenation. A passivation
oxide was then deposited and contact holes were defined. Finally, a 500-nm-thick Al electrode was deposited and patterned.
The gate width and length of the devices investigated in this study were 40 µm / 8 µm, respectively. The average grain size of the poly-Si is approximately 300 nm.
Figure 5.1(b) shows the transfer curves of the poly-Si TFT before electrical stress.
The electrical stress conditions were applied at various stress gate voltages (VG,stress), with a fixed stress drain voltage (VD,stress) of 20 V and a grounded source for 1000 s.
Ion and Ioff were defined at a drain voltage of 5 V and gate voltages of 25 V and -7 V, respectively. The variations in Ion and Ioff were defined as (Ion,stress – Ion,0)/ Ion,0 ×100
% and (Ioff,stress – Ioff,0)/ Ioff,0 ×100 %, where Ion,0, Ion,stress, Ioff,0 and Ioff,stress are the currents measured prior to and after the electrical stress.
5.3 Results and Discussion
Figure 5.2 shows plots of the variations in Ion with various stress conditions. As can be seen, while VG,stress < Vth, the channel is not formed yet and therefore a slight current leads to little damage under these stress conditions; consequently, minimal degradation of Ion can be observed. As VG,stress increases, the device will be turned on and operate in the saturation mode. Then, carriers are greatly accelerated by the lateral electric field and become “hot”. Subsequently, the impact-ionization phenomenon occurs, which is also called drain-avalanche-hot-carrier (DAHC) injection. Numerous hot carriers are generated, which damage the device and create a substantial amount of trap states or charges (negative) near the drain region, degrading Ion. For VG,stress
larger than 15 V, the electric field near the drain region decreases with increasing VG,stress and the acceleration of carriers drops. Thus, the degradation of Ion is small.
In the poly-Si TFT’s channel, defects in grain boundaries and intra-grains would
trap carriers and form potential barriers, affecting the current transport [9]-[11].
During the DAHC injection, more trap states (acceptor-like) or negative charges are created, raising the barrier height [12]-[14]. Therefore, serious degradation on Ion can be observed clearly. Figure 5.3 shows plots of the potential barrier for carrier transport induced by filled negative trap states (or negative charges) in the poly-Si channel. It is worth noting that the trap states (or charges) created by DAHC are crowded near the drain region, not distributed uniformly throughout the entire channel. To evaluate the increase in the number of trap states in the poly-Si channel after electrical stress, the trap state density (NT) was calculated from the square root of the slope of the ln(IDVDS/VGS) versus 1/VGS2 plots, which was proposed by Proano et al. [15]. The NT
for the sample before stress is approximately 4.04 × 1012 cm-2. After electrical stress, the NT for samples with VG,stress = 0 V, 5 V, 7.5 V, 10 V and 20 V are 4.67 × 1012, 5.72
× 1012, 6.07 × 1012, 5.70 × 1012, and 5.12 × 1012 cm-2, respectively. These results therefore indicate that DAHC most seriously damages poly-Si TFTs, which is consistent with the observation in other reports [12]-[14].
Considering that Ioff is associated with the amount of defects or traps in the drain depletion region, the schematic diagram of the depletion region and the corresponding energy band diagram of the drain in the Off-state are shown in Fig. 5.4. The generation of Ioff is attributed to thermionic emission at a low electric field and the field-enhanced emission (i.e., F-P emission or trap-assisted band-to-band tunneling) at a high electric filed [4]. Hence, the magnitude of the electrical field and the amount of traps within the drain depletion region are the two important factors considered in studying the variations in Ioff. On the basis of these inferences, the instabilities of Ioff
in poly-Si TFTs after electrical stress are investigated. Figure 5.5 shows the variations of Ioff under various VG,stress with a fixed VD,stress of 20 V for 1000 s. As can be seen, while VG,stress is small, Ioff is reduced after the stress. This is because some positive
charges are created in the poor-quality gate oxide (PE-TEOS oxide) near the drain.
These positive oxide charges lower the local electric field in the drain depletion region.
The electric field near the drain side before and after the creation of positive oxide charges is schematically depicted in Fig. 5.6. The positive oxide charges lift the electric field in the gate oxide but reduce that in the poly-Si. Thus, the reduction of the local electric field in the drain depletion region decreases Ioff. However, as VG,stress
increases, the DAHC-induced damage in the drain depletion region dominates the variation of Ioff, leading to the marked increase in Ioff. For VG,stress larger than 15 V, the variation of Ioff decreases, which is due to the reduction of the impact ionization with increasing VG,stress.
Now we know that for poly-Si TFTs in the On-state, Ion is strongly affected by the barrier height raised by the trap states (or charges) in the poly-Si channel. In the Off-state, the magnitude of the electric field and the amount of traps near the drain side are the two main factors determining the instability of Ioff. To further investigate the effects of these trap states (or charges) and the oxide charges on the instabilities of Ion and Ioff, a new strategy based on the correlations between the trap states (or charges) and the applied drain/gate voltages was adopted. Figure 5.7 shows the schematic diagrams of the experimental processes. Ion and Ioff were measured and compared before and after subjection to various electrical stress conditions with the same stress time of 1000 s by applying different drain or gate voltages. Figure 5.8 shows ∆Ioff, defined as Ioff,stress – Ioff,0, as a function of drain voltage (VDS). As can be seen, when VDS is low, a very slight ∆Ioff is observed, which can be attributed to thermionic emission. The ∆Ioff becomes larger for VDS > 6 V because field-enhanced emission dominates. For the curve of VG,stress= 0 V, we found that the positive charges in the gate oxide reduce the local electrical field in the poly-Si and make ∆Ioff negative.
However, as the drain depletion region increases with V , the number of trap sites in
the depletion region also increases and thus the curve shows a turnaround point near VDS = 11 V. For the curve of VG,stress = 10 V, the dominance of DAHC-generated trap states increases ∆Ioff. However, for the curve of VG,stress = 20 V, ∆Ioff remains nearly unchanged. In fact, under this stress conditions (VG,stress = VD,stress = 20 V), although not shown, the degradation of the subthreshold swing is more severe than that of Ion
and Ioff. The main mechanism involves the creation of interface states and intra-grain defects [7]. Under this high current stress, some weak bonds (Si-H bonds) are broken by the self-heating phenomenon, generating interface states at the oxide/poly-Si interface [16], [17]. Notably, these states distribute uniformly throughout the channel, rather than accumulating near the drain side. Therefore, ∆Ioff shows a weak dependence on the drain voltage.
Figure 5.9 shows plots of the variations of Ion as a function of drain voltages under three stress conditions. As can be seen, increasing the drain voltage increases Ion. This result reveals that the increasing VDS reduces the potential barrier established by the trap states (or charges) near the drain side, minimizing the effects of traps on the transport of carriers [3], [18]. This drain-induced trap state barrier lowering phenomenon is schematically depicted in Fig. 5.10. For VG,stress= 0 V, the variations in Ion become positive for VDS > 8V. This implies that after the trap-induced barrier is reduced with increasing VDS, the positive charges in the gate oxide govern the increase in the variation of Ion, making the variations of Ion positive. For the curve of VG,stress= 10 V, the numerous traps created by DAHC lead to a large degradation of Ion. However, for the curve of VG,stress = 20 V, Ion remains unchanged, because the distribution of the interface states is uniform throughout the channel. Moreover, by measuring the dependence of the variations of Ion on the drain voltage, one can also monitor the positions of the traps distributed in the poly-Si channel. For example, the variations of Ion measured at low a VDS reveal the effect of the traps located near the
drain side. In contrast, the variations of Ion measured at a high VDS reveal the effect of the traps located toward the channel. As can be seen in Fig. 5.9, for VG,stress=10 V, a severe degradation of the variations of Ion is found at a low VDS, which suggests that a substantial number of traps are generated near the drain side during DAHC stress.
Comparing the three stress conditions, VG,stress=10 V causes the most serious damage, which is distributed from drain to channel. However, for VG,stress= 0 V, the damage is mostly located near the drain side. For VG,stress= 20 V, the damage of interface states is distributed throughout the channel uniformly and the amounts are less than those caused by DAHC stress.
On the other hand, as we know, traps are generated in the poly-Si during the electrical stress. One considers that two types of traps are possibly created in the poly-Si channel of TFTs during the stress. One is the acceptor-like trap state; the other
On the other hand, as we know, traps are generated in the poly-Si during the electrical stress. One considers that two types of traps are possibly created in the poly-Si channel of TFTs during the stress. One is the acceptor-like trap state; the other