Thesis Organization

In this thesis, we concentrate our efforts on detailed sub-gate TFTs` performance and related process improvement.

In chapter 1, a brief overview of LTPS TFT technology and related applications were introduced,

In chapter 2, the fabrication process flow of sub-gate TFT, experimental recipes,

and device parameter extraction methods will be described.

In chapter 3, excimer laser system will be introduced. And the detailed discussion of characteristics of sub-gate TFT（comparison between SPC and ELA ） includes electrical properties, SEM graph analysis and reliability issue are discussed.

In chapter 4, sub-gate TFT with a novel ONO stacked gate dielectric is fabricated. The device performance and reliability are discussed, and the plasma passivation is also carried out.

Finally, conclusions and future works as well as suggestion for further research are given in chapter 5.

Chapter 2

Fabrication and Characterization of Low-Temperature Poly-Si TFTs

2.1 Typical Polysilicon TFT Fabrication Flow

In our experiment, all TFT devices with new structures are compared with the conventional TFT device. The conventional TFT device is fabricated by 4 masks on the 4-inch-diameter silicon wafer, and the cross-section view of our conventional structure is shown in Fig. 2-1. The main fabrication procedure is listed as follows:

1. Thermal wet oxidation to grow starting SiO2 film 2. a-Si deposition by LPCVD system

3. Low-temperature crystallization of a-Si film to obtain poly-Si film 4. Mask #1: Poly-Si island definition (poly-Si dry etching by RIE system) 5. Deposition of gate dielectric layer by PECVD system

6. Poly-Si gate deposition by LPCVD system

7. Mask #2: Gate definition (poly-Si dry etching by RIE system) 8. Ion implantation for source/drain doping

9. Source/drain dopant activation

10. Deposition of final passivation layer by PECVD system 11. Mask #3: Contact holes definition

12. Thermal evaporation of aluminum layer 13. Mask #4: Metal pad definition

14. Aluminum sintering

The detail parameters are illustrated in table 2-1.And the new sub-gate structure will be introduced in chapter 2 and 3, including cross-section view, fabrication procedure and operation principle.

2.2 Excimer Laser System

The setup of excimer laser system used in our experiment is shown in Fig. 2-2.

The key to the experiment is the KrF excimer laser and the wavelength of the one is 248 nm. In our experiment, the laser system was operated with frequency of 10 Hz and the pulse width of the laser pulse is approximately 30 ns. The samples are crystallized in a vacuum chamber at 320 mJ/cm² energy density and 400℃ substrate heating with a pressure of ＜ 10^-3 torr.

2.3 Methods of Device Parameter Extraction

To evaluate the characteristics of poly-Si TFTs, we often depend on some parameters such as threshold voltage, subthreshold swing, field effect mobility and on/off current ratio. For quantitative analysis, explicit measurement methods and equations are necessary. Hence, we make brief definitions for these parameters and list some useful equations in this section. All the following measurement in my experiment is based on these definition and equations.

2.3.1 Determination of Threshold Voltage

The threshold voltage Vth is the most important parameter in MOSFET. But the way to decide the value is various. In this thesis, we use “linear extrapolation method”

[2.1], and it is the most popular threshold voltage measurement technique at a low drain voltage. First, find the point of maximum slope on the ID-VGS curve by a maximum in the transconductance, _m ^DS

GS

2.3.2 Determination of Subthreshold Swing

Subthreshold swing S is that gate voltage necessary to change the drain current by one decade, and is given by ln(10)

60 ( / 300)

S nKT n

= q = T mV/decade [2.2]. It is a typical parameter to describe the control ability of gate toward channel.

In this thesis, the subthreshold swing is defined as one-third of the gate voltage required decreasing the threshold current by three orders of magnitude. The threshold current is specified to be the drain current when the gate voltage is equal to threshold voltage.

2.3.3 Determination of Field Effect Mobility

While the effective mobility is derived from the drain conductance, the field-effect mobility is determined from the transconductance [2.1]. The transconductance is defined by _{FE ox DS}

GS

solve the equation （assume VDS approaches zero）, and then the “field effect mobility” is given by： = _{(max) →0}

2.3.4 Determination of On/Off Current Ratio

In order to express not only large on-state current but also small off（leakage）

current, we define a “on/off current ratio”, and it is one of the most important parameters of poly-Si TFTs. Theoretically, the leakage current is as smaller as better.

But in poly-Si TFTs, the leakage mechanism is field emission via grain boundary traps by a high electric field near the drain. When the drain voltage increases, the leakage current will increase severely. Therefore, the voltage drops between drain and

source is as smaller as better when measures the on/off current ratio. In this thesis, the ratio is defined as following equation：

V

The low process temperature makes the reliability issues in LTPS TFTs different from those in the conventional MOSFETs. First, crystallized poly-Si is full of weak Si-Si bonds and dangling bond, and they will result in the variation of device electrical characteristics [2.3]. Then, the gate oxide grown at low temperature by PECVD system exhibits poor quality, such as low breakdown field, and high gate leakage current. Besides, the surface roughness of poly-Si resulting from laser crystallization will enhance local electrical field between the interface between poly-Si and gate oxide. Finally, “hot carrier effect” originates from high electric field near the drain region. It is also an important reliability issue in LTPS TFTs [2.4].

In this thesis, the stress condition is shown in table 2-1 [2.5]. The variations of the characteristics in different devices such as threshold voltage（Vth）, subthreshold swing（S.S） and transconductance（Gm） will be as tabled. The degradation mechanism will be discussed, and we will compare different kinds of sub-gate structure and make a conclusion in practical production.

Chapter 3

Poly-Si TFT with a Poly-Si Spacer Sub-Gate Structure

3.1 Device Architectures

Recently, LDD structure poly-Si TFTs are proposed to lower leakage current, but it also decrease the on-state current. Two years ago, our group proposed a new novel TFT structure with a self-aligned thicker sub-gate oxide near the drain/source region, which has a much lower off-state leakage current, and higher on/off current ratio than those of a conventional structure [3.1] At that time, the crystallization method for the deposited amorphous silicon is SPC（Solid Phase Crystallization）method at 600 for℃ 24 hr. Nowadays, the most popular crystallization method in LTPS TFT technology is ELA（Excimer Laser Annealing） method. Therefore, we plan to combine the novel device structure and ELA method and suppose the on-state current can be further improved without sacrificing the off-state current.

The schematic diagram of the proposed TFT structure is shown in Fig. 3-1. The top view of the proposed TFT structure is shown in Fig. 3-2, and the cross-section views along the line AA’ and BB’ are shown in Fig. 3-3(a) and (b). From the Fig.

3-3(b), we apply the voltage source on the sub-gates by opening new contact holes.

3.2 Process Flow

The TFTs were fabricated on 4-inch-diameter oxidized silicon wafer. A schematic graph of process flow is illustrated in Fig. 3-4. First, 100 nm-thick undoped a-Si thin films were deposited on 500 nm oxidized silicon （100）wafer by low-pressure chemical vapor deposition（LPCVD）system at 550 using silane℃

（SiH4）gas. The deposition pressure was 100 mtorr and the silane flow rate was 40 sccm.

Half the wafers were put into furnace and recrystallization was performed at 600 for 24 hr in N℃ 2 ambient using the SPC method. The other wafers were crystallized by KrF excimer laser annealing（ELA） in a vacuum ambient pumped down to 10^-3 torr, in which the substrate temperature was controlled at 400 . The ℃ excimer laser annealing was performed in the scanning mode at 320 mJ/cm² energy density.

After defining the device active regions, 50 nm-thick TEOS gate oxides were deposited by PECVD system. 300 nm-thick poly-Si films were then deposited by LPCVD system at 620 for the gate electrode. After defining the gate geometry, a ℃ 100 nm-thick PECVD TEOS oxide （Sub-gate oxide）and 400 nm-thick poly-Si layer were deposited alternately. The subsequent poly-Si films were etched by RIE system till the 100 nm-thick PECVD TEOS oxide, there were two sub-gate regions beside the gate electrode as shown in Fig. 3-1.

A self-aligned 5×10¹⁵ ions/cm² phosphorus implantation with a He-diluted PH3

gas at 50 KeV acceleration voltage was performed to form the regions of source, drain, sub-gate and gate electrodes. The dopant were activated at 600 in N℃ 2 ambient for 24 hr. Next, a 500 nm-thick TEOS oxide was deposited by PECVD system at 300 as a ℃ passivation layer. After contact holes were opened as shown in Fig. 3-2, a 500 nm-thick aluminum layer was deposited by thermal evaporation and the metal layer was patterned. Finally, the samples were sintered at 400 for 1 hr in N℃ 2 ambient.

The process conditions of every step are listed in table 3-1(a)-(d).

3.3 Analysis of Grain Size by Scanning Electron Microscope（SEM）

3.3.1 Sample Preparation

A-Si thin films with thickness of 100 nm were used as the starting material for SEM graph observation. The a-Si films were deposited on oxidized wafer with oxide

thickness of 0.5µm using LPCVD system. After crystallization（whether SPC or ELA）, the samples will be investigate the relation between the morphology of crystallized poly-Si thin films and electric characteristics through SEM observation. Before the analysis, the samples were processed by “Secco-etch”. “Secco-etch” preferably etches the grain boundaries in poly-Si and facilitate the SEM observation.

3.3.2 SEM Graph Analysis and Discussion

Fig. 3-5(a) shows the SEM image of poly-Si film crystallized by SPC after Secco-etch. In this graph, we can observe that grains are generally elliptical in shape due to preferential growth in the <112> direction [3.2]. But, the low process temperature makes many defects exist in crystallized poly-Si. The average grain size by SPC in our experiment is about 100~200 nm.

Fig. 3-5(b) and (c) show the SEM image of poly-Si film crystallized by ELA after Secco-etch. The graph indicates the grain size of ELA poly-Si film is indeed larger than the SPC one. In our experiment, the average grain size by ELA is about 1~1.5 µm. But there is a drawback in excimer laser system. In Fig. 3-5(d), the grain size are non-uniform distribution in poly-Si film [3.3]. It results in TFT devices which fabricated on these films have variant electrical characteristics. In order to give consideration to the consistency in our experiment, the device characteristic measurement is very important.

3.4 The Characteristics of Laser-Annealed Poly-Si TFTs

3.4.1 Laser-Annealed Poly-Si TFTs with Poly-Si Spacer Sub-Gate Structures Fig. 3-6(a) shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 1 V for SPC TFT, laser-annealed TFT and laser-annealed TFT with poly-Si spacer sub-gate structures. It was found that the characteristics

parameters of the TFTs crystallized by excimer laser annealing are better than the ones by SPC method, including threshold voltage（Vth）,subthreshold swing（S）,and on/off current ratio. It can be attributed to the larger grain size by excimer laser annealing, and there are no intra-grain defects in the grains. Thus, all the following devices in our experiment will be fabricated on excimer laser annealing poly-Si films.

Table 3-3 summarizes the statistical data of the electrical characteristics of different ELA TFT devices. It shows the non-uniform electrical characteristics compared to those fabricated by SPC of a-Si. The reason for non-uniformity is mentioned in section 3.3.2. Compare the spacer sub-gate TFTs and conventional TFTs, the on-state current decreased from 2.96×10^-4 A to 1.12×10^-5 A（about one order）, but the off-state current decreased substantially from 1.86×10^-8 A to 1.46×10^-10 A（at VGS=-5 V）. The main reason for much lower off-state leakage current of the sub-gate TFT is the drain electric field is greatly reduced for the thicker gate oxide in the sub-gate regions and the self-aligned offset PECVD oxide. Although the on-state current degraded due to thicker gate oxide at the same time, the on/off current ratio still in the acceptable range. Fig. 3-6(b) shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFTs and conventional TFTs. It was observed that the kink effect is weak in sub-gate TFTs at VGS=6 V even the driving current is smaller [3.4]. It confirms the reduction of drain electric field.

3.4.2 Laser-Annealed Poly-Si TFTs with Thicker Sub-Gate Nitride

In order to retrieve the degradation of driving current, we substitute nitride film for the gate dielectric of the sub-gate. Because the dielectric constant of nitride film is larger than oxide film, it can support higher driving current at the same thickness. In fig. 3-7, the sub-nitride TFT shows the better subthreshold swing and higher on-state current（about one order）. On the contrary, the leakage current is also higher and

on/off current ratio is close to the sub-oxide TFT. The rise leakage current might be attributed to the traps of nitride/oxide interface or the poor interface between poly-Si gate and nitride [3.5].

3.5 High Performance Sub-gate Structure TFTs with a Novel ONO Stack Gate Dielectric

In order to improve the quality of gate dielectric, W. Z. Yang et al. have proposed a novel ONO stack gate dielectric. “ONO” means that N2O plasma oxide/

Si3N4/TEOS oxide tri-layer structure, and it is found that LTPS TFTs with a novel ONO stack gate dielectric structure have superior electrical properties, more remarkable reliability and lower interface trap density than traditional TEOS oxide ones. It was attributed to the high quality N2O plasma oxide forming smoother surface and strong Si N bonds at the oxide/poly≣ -Si interface. Furthermore, the middle layer, Si3N4 film, which has higher dielectric constant than SiO2 results in promoting the on-state current of LTPS TFTs. Finally, the upper TEOS oxide layer was deposited due to improve the interface between gate dielectric and poly-Si gate.

In section 3.4, we know that excimer laser annealed poly-Si TFTs with sub-gate structures has lower leakage current and higher on/off current ratio than conventional structure ones. But the drawback of sub-gate structure is that on-state driving current also slightly decrease at the same time. For the sake of high on-state current and low leakage current, we fabricate excimer laser annealed sub-gate structure TFTs with ONO stack gate dielectric. It shows that they have more excellent electrical properties and good reliability. The ONO stacked gate dielectric grown parameters are listed in table 3-2.

Fig. 3-8(a) shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 1 V for sub-gate TFTs with TEOS oxide and ONO stack

gate dielectric. It was found that the characteristics parameters of the TFT with ONO are promoted obviously, including the higher on-state current（from 3.06×10^-5 to 1.95×10^-4, about one order）, the better subthreshold swing and threshold voltage. And the on/off current ratio is 8.44×10⁷. Thus, the combination of sub-gate structure and ONO gate dielectric can get excellent device characteristics. Fig 3-8(b) shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFTs with TEOS oxide and ONO stack gate dielectric. The driving current of sub-gate TFT with ONO at VDS=18 V is 3.08×10^-4（VGS=6V）and 9.71×10^-4（VGS=10V）. The reducing current by sub-gate structure could be compensated for ONO gate dielectric and the kink effect is also eased.

Fig. 3-9 shows the comparison of all the devices in this chapter and the detailed data were listed in table 3-4.

3.6 Reliability Issues

The stability of device characteristics under long-time operation is important especially as data driver in AMLCDs and pixel element in AMOLEDs. Many reasons will lead to device degradation such as gate oxide quality, poly-Si crystallization quality, self-heating, surface roughness of poly-Si and hot carrier effects. For this reason, reliability issues in LTPS TFTs are also very important research topics.

Fig. 3-10 (a) and (b) show the degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress which is defined as the TFT being kept at a high electric field in the drain junction. Notably, the dc stress conditions are VGS =10V and VDS =20V. The △Vth is defined as Vth,s –Vth, i where Vth, i denotes the initial Vth and Vth, s represents the Vth for etch stress time. Moreover, the degradation of the Gm max is defined as △Gm max /Gm max, i ,where △Gm max = △Gm max, s - △Gm max, i, Gm max, i denotes the initial Gm max and Gm max, s represents the Gm max for

each stress time. The △Vth and △Gm max /Gm max, i are measured at 1.0 V for etch stress time. In fig. 3-10 (a), the sub-gate structure TFT shows better reliability in transconductance than conventional one. It could be attributed to the reduction of drain electric field and weaken the hot carrier effect. At the region of the stress time between 1 sec and 100 sec, the slope of the threshold voltage shift of sub-gate structure was larger than that of the conventional structure. This is because that there were many weak bonds at the interface of the sub-gate oxide and active region, and the weak bonds were broken during the stress. Then, the traps were generated additionally and made threshold voltage increased rapidly [3.6]. After long time stress about 10000 sec, the stress generated traps of both structures saturated with time and the slope variations of them were almost the same.

3.7 Summary

The sub-gate structure with a self-aligned thicker sub-gate oxide near the drain/source regions has leakage current lower on order than those of the conventional one. For the sake of larger driving current, we introduce the silicon nitride to the thicker layer. Although the on-state driving current increased, the on/off current ratio is nearly unchanged due to higher leakage current. Finally, the sub-gate structure TFT with ONO stack gate dielectric shows the excellent properties. It shows the leakage current 100 times lower than those of the conventional ones and also shows on/off current ratio of 8.44×10⁷ at VGS=-5 V and VDS=1 V. The degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress of sub-gate structure is also less than conventional one.

Chapter 4

Laser-Annealed Poly-Si TFT with a Floating Sub-Gate Structure

4.1 Device Architectures

In order to reduce leakage current in LTPS TFTs, several structures have been proposed, for example, offset gated structures. But, it needs an additional photo-masking step and increases extra series resistance. The misalignment problem would also occur.

We proposed a poly-Si TFT with a sub-gate coupling structure and will reduce the off state current without degrading the on current [4.1]. Besides, an additional

We proposed a poly-Si TFT with a sub-gate coupling structure and will reduce the off state current without degrading the on current [4.1]. Besides, an additional