Summary

The sub-gate structure with a self-aligned thicker sub-gate oxide near the drain/source regions has leakage current lower on order than those of the conventional one. For the sake of larger driving current, we introduce the silicon nitride to the thicker layer. Although the on-state driving current increased, the on/off current ratio is nearly unchanged due to higher leakage current. Finally, the sub-gate structure TFT with ONO stack gate dielectric shows the excellent properties. It shows the leakage current 100 times lower than those of the conventional ones and also shows on/off current ratio of 8.44×10⁷ at VGS=-5 V and VDS=1 V. The degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress of sub-gate structure is also less than conventional one.

Chapter 4

Laser-Annealed Poly-Si TFT with a Floating Sub-Gate Structure

4.1 Device Architectures

In order to reduce leakage current in LTPS TFTs, several structures have been proposed, for example, offset gated structures. But, it needs an additional photo-masking step and increases extra series resistance. The misalignment problem would also occur.

We proposed a poly-Si TFT with a sub-gate coupling structure and will reduce the off state current without degrading the on current [4.1]. Besides, an additional interfacial amorphous silicon layer will be deposited. The following variation in device electrical characteristics and reliability is worthy to observe and discuss.

The schematic diagram of the sub-gate structure TFT is shown in Fig. 4-1. The top view of the proposed TFT structure is shown in Fig. 4-2(a), and the cross-section views along the line AA’ and BB’ are shown in Fig. 4-2(b) and (c).

4.2 Process flow

The process flow of fabricating sub-gate coupling structure TFT is the same as the conventional non-offset poly-Si TFT. And the process conditions are also the same as the conventional poly-Si TFT.

The detailed fabrication process flow is listed as follows.

1. (100) orientation Si wafer.

2. Initial cleaning.

3. Thermal wet oxidation at 1050^。C to grow 500 nm thermal SiO2 in furnace.

4. 1000 Å a-Si was deposited by LPCVD at 550^。C in SiH4 gas.

5. KrF excimer laser crystallization was carried out in 10^-4 Torr at 320 mJ/cm²

energy density and 400^。C substrate heating.

6. Mask #1：Define active regions (poly-Si dry etching by Poly-RIE system).

7. RCA cleaning.

8. 50 nm gate dielectric deposition by PECVD at 300^。℃.

9. 300 nm poly-Si was deposited by LPCVD at 620^。C in SiH4 gas.

10. Mask #2：Define gate regions (poly-Si dry etch by Poly-RIE system).

11. Ion implantation: P³¹ , 50KeV, 5x10¹⁵ ions/cm².

12. Dopant activation in N2 ambient at 600^。C for 24hrs in furnace.

13. 500 nm TEOS oxide was deposited by PECVD as passivation layer.

14. Mask #3：Open contact holes 15. 500 nm Al thermal evaporation.

16. Mask #4：Al pattern defined.

17. Etching Al and removing photoresist.

18. Al sintering at 400^。C in N2 ambient for 1 hr.

4.3 Electrical Properties and Characteristics

Fig. 4-3 shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 0.1V and 5V for laser-annealed TFT and laser-annealed TFT with a floating sub-gate structure. It was found that the laser-annealed TFT with a floating sub-gate structure has the smaller leakage current（about two order）, and on/off current ratio is close to the ratio of the conventional TFTs（2.12×10⁷ and 4.28×

10⁷）. Because of the lower leakage current, we suppose it is helpful to device reliability.

The sub-gate is floating and its potential is controlled by the main gate potential VGS, drain potential VDS, undoped channel potential VUC, and doped channel potential

VDC. The VSG can be expressed as： 1 1 2 3 4 and the bottom layer, drain region, undoped channel, and doped channel, respectively.

The parameter R=AMS/ASC where AMS is overlapping area between the metal pad and the sub-gate and ASC is overlapping area between the sub-gate and the channel. In off state, the VGS＜0 and the VDS＞0.Thus, the sub-gate potential determined by above equation is smaller than the main gate potential. The drain electric field can be reduced as compared to the conventional TFTs, so the sub-gate TFT can act as the offset poly-Si TFT in the off state if the area ratio R is properly adjusted. In the on state, both VGS and VDS＞0. The sub-gate potential is almost equivalent to the main gate potential at high VGS and VDS, so that the sub-gate TFT behaves as the conventional TFT in the on state.

Fig. 4-4 (a)-(c) shows the effect of area ratio R on IDS-VGS characteristics at VDS=0.1, 1 and 5V. As R increases up to 10, the sub-gate TFT behaves as the conventional TFT. On the other hand, as R decreases down to 1, the sub-gate TFT acts as an offset TFT. Fig. 4-5 (a) and (b) show the effect of area ratio R on IDS-VDS

characteristics at VGS=6 and 10V. It was found that the kink effect is weaker when R decreases, but the driving current is also degraded. Thus, modulating the R value is an important issue.

Fig. 4-6 shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V for various area ratio R. We need the on state current larger and the off state current smaller. Thus the optimum condition of the floating sub-gate TFT can be achieved at R=5. All the detailed data about sub-gate TFT with various R were listed in table 4-1.

4.4 Improving the Characteristics of Low-Temperature Poly-Si TFTs by an Additional Amorphous Silicon Interfacial Layer

Comparing to SPC method, the surface of the excmier laser crystallized poly-Si films is rather rough due to the explosive protrusion of grain boundaries during the grain growth, which results in the increase of the roughness at the poly-Si/gate oxide interface. It is also reported that the field-effect mobility of TFT devices is affected by the roughness of the gate insulator [4.2]. Considerable efforts have been paid to improve the surface roughness of poly-Si because the electrical characteristics of TFT’s are seriously affected by the interface roughness of the gate insulator [4.3]. In this section, we introduce a thin amorphous silicon nano layer on the poly-Si channel layer, and combine the floating sub-gate structure to investigate the effect of the surface roughness on the device performance, including studied the transfer characteristics.

The transfer characteristics（IDS-VDS） of laser-annealed sub-gate TFT（R=5）

with/without α-Si layer are shown in Figure 4-7(a) and (b). Both on state current (measured at VGS= 20 V) and off-state leakage current (measured at VGS= -5 V) are reduced with a-Si layer thickness increasing. The reason for lower leakage current of the laser-annealed TFT with ultra-thin a-Si layer is due to reduction of the drain electric field [4.4]. However, it was found that the turn-on current is also degraded when the a-Si layer thickness increased. We supposed the reduction of the turn-on current due to higher grain boundary trap density of a-Si layer became dominate. It is obviously that the optimum condition is ELA with 5 nm-thick a-Si layer. At VDS = 5 V, the on/off current ratios of the ELA TFT and the ELA TFT with 5-nm a-Si layer are 7.59 x 10⁴ and 2.96 x 10⁵, respectively. The detailed data and parameters are shown in table 4-2.

Fig. 4-8(a) and (b) shows the transfer characteristics measured under a constant

drain bias（VDS）of 1 V and 5 V for the floating sub-gate TFT with 5-nm a-Si layer.

The leakage current of the floating sub-gate TFT with 5-nm a-Si layer is still getting lower when the area ratio R decreased. But, the turn-on current at low drain voltage

（VD=1V）has the peak point to conduct. We suppose the dual channel layer（poly-Si and ultra-thin a-Si layer）result in a multi-conducting path and choose the lowest resistivity path. Fig. 4-9 shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFT（R=5） with/without 5-nm a-Si layer. Less kink effect is observed in sub-gate TFT with ultra-thin a-Si layer and we can further confirm that the drain electric field is effectively reduced as a-Si layer thickness increasing.

Because the kink current in TFT device is basically due to the avalanche or impact ionization in the device and it is strongly influenced by grain boundary traps. The grain boundary traps can prevent the channel carriers from gaining higher energy, and therefore the impact ionization probability can be reduced as the grain boundary trap density is increased.

Fig. 4-10(a) and (b) show the comparison of transfer characteristics（IDS-VGS） measured under a constant drain bias（VDS）of 1 V and 5 V for the conventional TFT and the floating sub-gate TFT with/without 5-nm a-Si layer. It was found that the lowest leakage current is gotten by combining the floating sub-gate structure and the ultra-thin a-Si layer. And the on/off current ratio is close to the one of conventional TFT. Fig. 4-11(a) shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V of the floating sub-gate TFT with 5-nm a-Si layer for various area ratio R. It is identical to fig. 4-6 that without a ultra-thin a-Si layer.

And fig. 4-11(b) shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V of the floating sub-gate TFT（R=5）for various a-Si layer thickness. It is shown that both on and off current degraded when a-Si thickness increased. All the detailed data and parameters are listed in table 4-3.

4.5 Reliability Issues

As usual, reliability issues are still the important topics that we are concerned.

Fig. 4-12 (a) and (b) show the degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress which is defined as the TFT being kept at a high electric field in the drain junction. Notably, the dc stress conditions are VGS =10V and VDS =20V. In fig. 4-12 (a), the sub-gate structure TFT shows better reliability in transconductance than conventional one. It has been extensively discussed that Gm max degradation during hot-carrier stress conditions is mainly due to interface state generation. Due to the sub-gate structure decreasing the drain electric field, the hot carrier effect is quite reduced. In fig. 4-12 (b), both structure show almost the same power-time dependence. The mechanism of Vth

variations includes hot carrier injection into the gate oxide and deep grain-boundary trap generation [4.5]. Due to the sub-gate structure decreasing the drain electric field, both of them are reduced. Thus, sub-gate structure shows better device reliability.

4.6 Summary

The floating sub-gate structure behaves as an offset gated structure by modulating overlapping area ratio R, and its fabrication processes is fully the same as the conventional TFT. The optimum condition is R=5 in this thesis. It shows the leakage current is 3.51×10^-10 A and is 100 times lower than those of the conventional ones at VGS=-5 V and VDS=1 V. It also shows on/off current ratio of 2.12×10⁷ at VGS=-5 V and VDS=1 V. In order to improve the surface roughness of poly-Si film, we cap an ultra-thin a-Si layer on the laser-annealed poly-Si film. And it show better electrical characteristics. The sub-gate structure（R=5）TFT with a 5 nm-thick a-Si capping layer shows the low leakage current of 2.4×10^-9 A and on/off current ratio of 5.85×10⁶ at VGS=-5 V and VDS=1 V. The degradation of the maximum

transconductance and the threshold voltage variations under static hot-carrier stress of sub-gate structure is also less than conventional one.

Chapter 5

Conclusions and Future Works

5.1 Conclusions

The sub-gate structure with a self-aligned thicker sub-gate oxide near the

drain/source regions has leakage current lower on order than those of the conventional one. For the sake of larger driving current, we introduce the silicon nitride to the thicker layer. Although the on-state driving current increased, the on/off current ratio is nearly unchanged due to higher leakage current. Finally, the sub-gate structure TFT with ONO stack gate dielectric shows the excellent properties. It shows the leakage current 100 times lower than those of the conventional ones and also shows on/off current ratio of 8.44×10⁷ at VGS=-5 V and VDS=1 V. The degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress of sub-gate structure is also less than conventional one.

The floating sub-gate structure behaves as an offset gated structure by modulating overlapping area ratio R, and its fabrication processes is fully the same as the conventional TFT. The optimum condition is R=5 in this thesis. It shows the leakage current is 3.51×10^-10 A and is 100 times lower than those of the conventional ones at VGS=-5 V and VDS=1 V. It also shows on/off current ratio of 2.12×10⁷ at VGS=-5 V and VDS=1 V. In order to improve the surface roughness of poly-Si film, we cap an ultra-thin a-Si layer on the laser-annealed poly-Si film. And it show better electrical characteristics. The sub-gate structure（R=5）TFT with a 5 nm-thick a-Si capping layer shows the low leakage current of 2.4×10^-9 A and on/off current ratio of 5.85×10⁶ at VGS=-5 V and VDS=1 V. And It also shows better device reliability than conventional structure TFT.

Therefore, the combination techniques of novel ONO stack gate dielectric, ELA

crystallization method, additional ultra-thin a-Si layer and sub-gate structures for fabricating poly-Si TFTs exhibit significantly superior electrical characteristics and reliability to the conventional poly-Si TFTs. Hence, they are promising for the application of integrated circuits on AMLCD panels.

5.2 Future Works

There are some interesting topics that are valuable for the future further research about the LTPS TFTs.

If appropriate plasma passivation is performed for optimized thinner silicon films, the carrier mobility and gate voltage swing would be further improved.

Although excimer laser has been shown to be the most promising candidate for the crystallization method of LTPS TFTs, the instability and short pulse duration of excimer laser makes the formation of uniform and large grained poly-Si thin films hard. The continuous-wave（CW）laser may be another alternative for crystallizing a-Si thin films due to the advantages of good stability of laser fluence and long melting duration during laser irradiation.

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