Chapter 3 Poly-Si TFT with a Poly-Si Spacer Sub-Gate Structure
3.3 Analysis of Grain Size by Scanning Electron Microscope（SEM）
3.3.2 SEM Graph Analysis and Discussion
Fig. 3-5(a) shows the SEM image of poly-Si film crystallized by SPC after Secco-etch. In this graph, we can observe that grains are generally elliptical in shape due to preferential growth in the <112> direction [3.2]. But, the low process temperature makes many defects exist in crystallized poly-Si. The average grain size by SPC in our experiment is about 100~200 nm.
Fig. 3-5(b) and (c) show the SEM image of poly-Si film crystallized by ELA after Secco-etch. The graph indicates the grain size of ELA poly-Si film is indeed larger than the SPC one. In our experiment, the average grain size by ELA is about 1~1.5 µm. But there is a drawback in excimer laser system. In Fig. 3-5(d), the grain size are non-uniform distribution in poly-Si film [3.3]. It results in TFT devices which fabricated on these films have variant electrical characteristics. In order to give consideration to the consistency in our experiment, the device characteristic measurement is very important.
3.4 The Characteristics of Laser-Annealed Poly-Si TFTs
3.4.1 Laser-Annealed Poly-Si TFTs with Poly-Si Spacer Sub-Gate Structures Fig. 3-6(a) shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 1 V for SPC TFT, laser-annealed TFT and laser-annealed TFT with poly-Si spacer sub-gate structures. It was found that the characteristics
parameters of the TFTs crystallized by excimer laser annealing are better than the ones by SPC method, including threshold voltage（Vth）,subthreshold swing（S）,and on/off current ratio. It can be attributed to the larger grain size by excimer laser annealing, and there are no intra-grain defects in the grains. Thus, all the following devices in our experiment will be fabricated on excimer laser annealing poly-Si films.
Table 3-3 summarizes the statistical data of the electrical characteristics of different ELA TFT devices. It shows the non-uniform electrical characteristics compared to those fabricated by SPC of a-Si. The reason for non-uniformity is mentioned in section 3.3.2. Compare the spacer sub-gate TFTs and conventional TFTs, the on-state current decreased from 2.96×10-4 A to 1.12×10-5 A（about one order）, but the off-state current decreased substantially from 1.86×10-8 A to 1.46×10-10 A（at VGS=-5 V）. The main reason for much lower off-state leakage current of the sub-gate TFT is the drain electric field is greatly reduced for the thicker gate oxide in the sub-gate regions and the self-aligned offset PECVD oxide. Although the on-state current degraded due to thicker gate oxide at the same time, the on/off current ratio still in the acceptable range. Fig. 3-6(b) shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFTs and conventional TFTs. It was observed that the kink effect is weak in sub-gate TFTs at VGS=6 V even the driving current is smaller [3.4]. It confirms the reduction of drain electric field.
3.4.2 Laser-Annealed Poly-Si TFTs with Thicker Sub-Gate Nitride
In order to retrieve the degradation of driving current, we substitute nitride film for the gate dielectric of the sub-gate. Because the dielectric constant of nitride film is larger than oxide film, it can support higher driving current at the same thickness. In fig. 3-7, the sub-nitride TFT shows the better subthreshold swing and higher on-state current（about one order）. On the contrary, the leakage current is also higher and
on/off current ratio is close to the sub-oxide TFT. The rise leakage current might be attributed to the traps of nitride/oxide interface or the poor interface between poly-Si gate and nitride [3.5].
3.5 High Performance Sub-gate Structure TFTs with a Novel ONO Stack Gate Dielectric
In order to improve the quality of gate dielectric, W. Z. Yang et al. have proposed a novel ONO stack gate dielectric. “ONO” means that N2O plasma oxide/
Si3N4/TEOS oxide tri-layer structure, and it is found that LTPS TFTs with a novel ONO stack gate dielectric structure have superior electrical properties, more remarkable reliability and lower interface trap density than traditional TEOS oxide ones. It was attributed to the high quality N2O plasma oxide forming smoother surface and strong Si N bonds at the oxide/poly≣ -Si interface. Furthermore, the middle layer, Si3N4 film, which has higher dielectric constant than SiO2 results in promoting the on-state current of LTPS TFTs. Finally, the upper TEOS oxide layer was deposited due to improve the interface between gate dielectric and poly-Si gate.
In section 3.4, we know that excimer laser annealed poly-Si TFTs with sub-gate structures has lower leakage current and higher on/off current ratio than conventional structure ones. But the drawback of sub-gate structure is that on-state driving current also slightly decrease at the same time. For the sake of high on-state current and low leakage current, we fabricate excimer laser annealed sub-gate structure TFTs with ONO stack gate dielectric. It shows that they have more excellent electrical properties and good reliability. The ONO stacked gate dielectric grown parameters are listed in table 3-2.
Fig. 3-8(a) shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 1 V for sub-gate TFTs with TEOS oxide and ONO stack
gate dielectric. It was found that the characteristics parameters of the TFT with ONO are promoted obviously, including the higher on-state current（from 3.06×10-5 to 1.95×10-4, about one order）, the better subthreshold swing and threshold voltage. And the on/off current ratio is 8.44×107. Thus, the combination of sub-gate structure and ONO gate dielectric can get excellent device characteristics. Fig 3-8(b) shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFTs with TEOS oxide and ONO stack gate dielectric. The driving current of sub-gate TFT with ONO at VDS=18 V is 3.08×10-4（VGS=6V）and 9.71×10-4（VGS=10V）. The reducing current by sub-gate structure could be compensated for ONO gate dielectric and the kink effect is also eased.
Fig. 3-9 shows the comparison of all the devices in this chapter and the detailed data were listed in table 3-4.
3.6 Reliability Issues
The stability of device characteristics under long-time operation is important especially as data driver in AMLCDs and pixel element in AMOLEDs. Many reasons will lead to device degradation such as gate oxide quality, poly-Si crystallization quality, self-heating, surface roughness of poly-Si and hot carrier effects. For this reason, reliability issues in LTPS TFTs are also very important research topics.
Fig. 3-10 (a) and (b) show the degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress which is defined as the TFT being kept at a high electric field in the drain junction. Notably, the dc stress conditions are VGS =10V and VDS =20V. The △Vth is defined as Vth,s –Vth, i where Vth, i denotes the initial Vth and Vth, s represents the Vth for etch stress time. Moreover, the degradation of the Gm max is defined as △Gm max /Gm max, i ,where △Gm max = △Gm max, s - △Gm max, i, Gm max, i denotes the initial Gm max and Gm max, s represents the Gm max for
each stress time. The △Vth and △Gm max /Gm max, i are measured at 1.0 V for etch stress time. In fig. 3-10 (a), the sub-gate structure TFT shows better reliability in transconductance than conventional one. It could be attributed to the reduction of drain electric field and weaken the hot carrier effect. At the region of the stress time between 1 sec and 100 sec, the slope of the threshold voltage shift of sub-gate structure was larger than that of the conventional structure. This is because that there were many weak bonds at the interface of the sub-gate oxide and active region, and the weak bonds were broken during the stress. Then, the traps were generated additionally and made threshold voltage increased rapidly [3.6]. After long time stress about 10000 sec, the stress generated traps of both structures saturated with time and the slope variations of them were almost the same.
3.7 Summary
The sub-gate structure with a self-aligned thicker sub-gate oxide near the drain/source regions has leakage current lower on order than those of the conventional one. For the sake of larger driving current, we introduce the silicon nitride to the thicker layer. Although the on-state driving current increased, the on/off current ratio is nearly unchanged due to higher leakage current. Finally, the sub-gate structure TFT with ONO stack gate dielectric shows the excellent properties. It shows the leakage current 100 times lower than those of the conventional ones and also shows on/off current ratio of 8.44×107 at VGS=-5 V and VDS=1 V. The degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress of sub-gate structure is also less than conventional one.
Chapter 4
Laser-Annealed Poly-Si TFT with a Floating Sub-Gate Structure
4.1 Device Architectures
In order to reduce leakage current in LTPS TFTs, several structures have been proposed, for example, offset gated structures. But, it needs an additional photo-masking step and increases extra series resistance. The misalignment problem would also occur.
We proposed a poly-Si TFT with a sub-gate coupling structure and will reduce the off state current without degrading the on current [4.1]. Besides, an additional interfacial amorphous silicon layer will be deposited. The following variation in device electrical characteristics and reliability is worthy to observe and discuss.
The schematic diagram of the sub-gate structure TFT is shown in Fig. 4-1. The top view of the proposed TFT structure is shown in Fig. 4-2(a), and the cross-section views along the line AA’ and BB’ are shown in Fig. 4-2(b) and (c).
4.2 Process flow
The process flow of fabricating sub-gate coupling structure TFT is the same as the conventional non-offset poly-Si TFT. And the process conditions are also the same as the conventional poly-Si TFT.
The detailed fabrication process flow is listed as follows.
1. (100) orientation Si wafer.
2. Initial cleaning.
3. Thermal wet oxidation at 1050。C to grow 500 nm thermal SiO2 in furnace.
4. 1000 Å a-Si was deposited by LPCVD at 550。C in SiH4 gas.
5. KrF excimer laser crystallization was carried out in 10-4 Torr at 320 mJ/cm2
energy density and 400。C substrate heating.
6. Mask #1：Define active regions (poly-Si dry etching by Poly-RIE system).
7. RCA cleaning.
8. 50 nm gate dielectric deposition by PECVD at 300。℃.
9. 300 nm poly-Si was deposited by LPCVD at 620。C in SiH4 gas.
10. Mask #2：Define gate regions (poly-Si dry etch by Poly-RIE system).
11. Ion implantation: P31 , 50KeV, 5x1015 ions/cm2.
12. Dopant activation in N2 ambient at 600。C for 24hrs in furnace.
13. 500 nm TEOS oxide was deposited by PECVD as passivation layer.
14. Mask #3：Open contact holes 15. 500 nm Al thermal evaporation.
16. Mask #4：Al pattern defined.
17. Etching Al and removing photoresist.
18. Al sintering at 400。C in N2 ambient for 1 hr.
4.3 Electrical Properties and Characteristics
Fig. 4-3 shows the comparison of transfer characteristics measured under a constant drain bias（VDS）of 0.1V and 5V for laser-annealed TFT and laser-annealed TFT with a floating sub-gate structure. It was found that the laser-annealed TFT with a floating sub-gate structure has the smaller leakage current（about two order）, and on/off current ratio is close to the ratio of the conventional TFTs（2.12×107 and 4.28×
107）. Because of the lower leakage current, we suppose it is helpful to device reliability.
The sub-gate is floating and its potential is controlled by the main gate potential VGS, drain potential VDS, undoped channel potential VUC, and doped channel potential
VDC. The VSG can be expressed as： 1 1 2 3 4 and the bottom layer, drain region, undoped channel, and doped channel, respectively.
The parameter R=AMS/ASC where AMS is overlapping area between the metal pad and the sub-gate and ASC is overlapping area between the sub-gate and the channel. In off state, the VGS＜0 and the VDS＞0.Thus, the sub-gate potential determined by above equation is smaller than the main gate potential. The drain electric field can be reduced as compared to the conventional TFTs, so the sub-gate TFT can act as the offset poly-Si TFT in the off state if the area ratio R is properly adjusted. In the on state, both VGS and VDS＞0. The sub-gate potential is almost equivalent to the main gate potential at high VGS and VDS, so that the sub-gate TFT behaves as the conventional TFT in the on state.
Fig. 4-4 (a)-(c) shows the effect of area ratio R on IDS-VGS characteristics at VDS=0.1, 1 and 5V. As R increases up to 10, the sub-gate TFT behaves as the conventional TFT. On the other hand, as R decreases down to 1, the sub-gate TFT acts as an offset TFT. Fig. 4-5 (a) and (b) show the effect of area ratio R on IDS-VDS
characteristics at VGS=6 and 10V. It was found that the kink effect is weaker when R decreases, but the driving current is also degraded. Thus, modulating the R value is an important issue.
Fig. 4-6 shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V for various area ratio R. We need the on state current larger and the off state current smaller. Thus the optimum condition of the floating sub-gate TFT can be achieved at R=5. All the detailed data about sub-gate TFT with various R were listed in table 4-1.
4.4 Improving the Characteristics of Low-Temperature Poly-Si TFTs by an Additional Amorphous Silicon Interfacial Layer
Comparing to SPC method, the surface of the excmier laser crystallized poly-Si films is rather rough due to the explosive protrusion of grain boundaries during the grain growth, which results in the increase of the roughness at the poly-Si/gate oxide interface. It is also reported that the field-effect mobility of TFT devices is affected by the roughness of the gate insulator [4.2]. Considerable efforts have been paid to improve the surface roughness of poly-Si because the electrical characteristics of TFT’s are seriously affected by the interface roughness of the gate insulator [4.3]. In this section, we introduce a thin amorphous silicon nano layer on the poly-Si channel layer, and combine the floating sub-gate structure to investigate the effect of the surface roughness on the device performance, including studied the transfer characteristics.
The transfer characteristics（IDS-VDS） of laser-annealed sub-gate TFT（R=5）
with/without α-Si layer are shown in Figure 4-7(a) and (b). Both on state current (measured at VGS= 20 V) and off-state leakage current (measured at VGS= -5 V) are reduced with a-Si layer thickness increasing. The reason for lower leakage current of the laser-annealed TFT with ultra-thin a-Si layer is due to reduction of the drain electric field [4.4]. However, it was found that the turn-on current is also degraded when the a-Si layer thickness increased. We supposed the reduction of the turn-on current due to higher grain boundary trap density of a-Si layer became dominate. It is obviously that the optimum condition is ELA with 5 nm-thick a-Si layer. At VDS = 5 V, the on/off current ratios of the ELA TFT and the ELA TFT with 5-nm a-Si layer are 7.59 x 104 and 2.96 x 105, respectively. The detailed data and parameters are shown in table 4-2.
Fig. 4-8(a) and (b) shows the transfer characteristics measured under a constant
drain bias（VDS）of 1 V and 5 V for the floating sub-gate TFT with 5-nm a-Si layer.
The leakage current of the floating sub-gate TFT with 5-nm a-Si layer is still getting lower when the area ratio R decreased. But, the turn-on current at low drain voltage
（VD=1V）has the peak point to conduct. We suppose the dual channel layer（poly-Si and ultra-thin a-Si layer）result in a multi-conducting path and choose the lowest resistivity path. Fig. 4-9 shows the comparison of output characteristics（IDS-VDS）of sub-gate structure TFT（R=5） with/without 5-nm a-Si layer. Less kink effect is observed in sub-gate TFT with ultra-thin a-Si layer and we can further confirm that the drain electric field is effectively reduced as a-Si layer thickness increasing.
Because the kink current in TFT device is basically due to the avalanche or impact ionization in the device and it is strongly influenced by grain boundary traps. The grain boundary traps can prevent the channel carriers from gaining higher energy, and therefore the impact ionization probability can be reduced as the grain boundary trap density is increased.
Fig. 4-10(a) and (b) show the comparison of transfer characteristics（IDS-VGS） measured under a constant drain bias（VDS）of 1 V and 5 V for the conventional TFT and the floating sub-gate TFT with/without 5-nm a-Si layer. It was found that the lowest leakage current is gotten by combining the floating sub-gate structure and the ultra-thin a-Si layer. And the on/off current ratio is close to the one of conventional TFT. Fig. 4-11(a) shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V of the floating sub-gate TFT with 5-nm a-Si layer for various area ratio R. It is identical to fig. 4-6 that without a ultra-thin a-Si layer.
And fig. 4-11(b) shows the off state leakage current measured at VGS=-5V and the on state current measured at VGS=20V of the floating sub-gate TFT（R=5）for various a-Si layer thickness. It is shown that both on and off current degraded when a-Si thickness increased. All the detailed data and parameters are listed in table 4-3.
4.5 Reliability Issues
As usual, reliability issues are still the important topics that we are concerned.
Fig. 4-12 (a) and (b) show the degradation of the maximum transconductance and the threshold voltage variations under static hot-carrier stress which is defined as the TFT being kept at a high electric field in the drain junction. Notably, the dc stress conditions are VGS =10V and VDS =20V. In fig. 4-12 (a), the sub-gate structure TFT shows better reliability in transconductance than conventional one. It has been extensively discussed that Gm max degradation during hot-carrier stress conditions is mainly due to interface state generation. Due to the sub-gate structure decreasing the drain electric field, the hot carrier effect is quite reduced. In fig. 4-12 (b), both structure show almost the same power-time dependence. The mechanism of Vth
variations includes hot carrier injection into the gate oxide and deep grain-boundary trap generation [4.5]. Due to the sub-gate structure decreasing the drain electric field, both of them are reduced. Thus, sub-gate structure shows better device reliability.
4.6 Summary
The floating sub-gate structure behaves as an offset gated structure by modulating overlapping area ratio R, and its fabrication processes is fully the same as the conventional TFT. The optimum condition is R=5 in this thesis. It shows the leakage current is 3.51×10-10 A and is 100 times lower than those of the conventional ones at VGS=-5 V and VDS=1 V. It also shows on/off current ratio of 2.12×107 at VGS=-5 V and VDS=1 V. In order to improve the surface roughness of poly-Si film, we
The floating sub-gate structure behaves as an offset gated structure by modulating overlapping area ratio R, and its fabrication processes is fully the same as the conventional TFT. The optimum condition is R=5 in this thesis. It shows the leakage current is 3.51×10-10 A and is 100 times lower than those of the conventional ones at VGS=-5 V and VDS=1 V. It also shows on/off current ratio of 2.12×107 at VGS=-5 V and VDS=1 V. In order to improve the surface roughness of poly-Si film, we