Thesis Organization

In the chapter 2 of the thesis, some basic concepts of RF design are introduced.

These basic concepts which include the introduction of receiver architecture, WLAN standards, noise and linearity provide the guidance for RF circuit design.

In the chapter 3 of the thesis, the design consideration of some circuit blocks which include LNA, phase splitter and mixer is introduced. Based on these circuits, a mixer and a front-end circuit are designed and verified in later chapter.

In the chapter 4 of the thesis, the nonlinear sources of the device are analyzed. The multiple gated transistors configuration is introduced and a compact equivalent circuit using a complex transconductance is proposed for linearity design in this configuration. Following the above analysis, a low-power and high-linearity direct down-conversion mixer is designed. Finally, measurement result of the mixer chip fabricated by TSMC 0.18um CMOS technology is discussed.

In the chapter 5 of the thesis, a low-power front-end circuit is designed. The first stage is the LNA using inductive source degeneration topology for input matching.

The second stage is the phase splitter which transforms single-ended signal into differential form. The last stage is the mixer which is the same as that in chapter 4.

Overall front-end circuit is implemented.

In the last chapter, the work is summarized and concluded.

CHAPTER 2

Basic Concepts in RF Design

2.1 Receiver Architecture

2.1.1 Heterodyne Receiver

In heterodyne architectures, the signal band is translated into much lower frequencies by down-conversion mixer, and the filters are used to select the band and channel of the interested signals. In general, the low noise amplifier is placed in front of the down-conversion mixer, since the noise of the down-conversion mixer is high.

A simple heterodyne architecture is shown in Fig. 2.1. This architecture is the most reliable reception technique today. But if the cost, complexity, integration and power dissipation are the primary criteria, the heterodyne receiver will become unsuitable due to its complexity and the need for a large number of external components.

Frequency planning is an important thing in heterodyne receiver. For high-side injection, an undesired signal (image) at a frequency of

)

( _{LO RF}

LO

IM ω ω ω

ω = + − is translated into the same frequency, intermediate frequency (IF), as the desired signal. Similarly, for low-side injection, the image

) cos(ω_LOt

Mixer

filter reject image

filter select channel LNA

Figure 2.1 Simple heterodyne architecture

frequency is at ω_IM =ω_LO −(ω_RF −ω_LO). Therefore the image would cause the distortion of the signal at the intermediate frequency. As shown in Fig. 2.2, some techniques are necessary to suppress the image, such as image reject filter. How to choose the intermediate frequency? If 2ω_IF is sufficiently large, the image reject filter will have a relatively small loss in the signal band and a large attenuation in the image band. But a lower 2ω_IF will release the quality factor of the channel select filter to get great suppression of nearby interferers. Therefore we must take a trade-off between image rejection and channel selection.

2.1.2 Homodyne Receiver

The homodyne receiver is also called “direct-conversion” or “zero-IF”

architecture, since the RF signal is directly down-converted to the baseband in the first downconversion. In the homodyne receiver, the LO frequency is equal to the

0

0

ω ω

ω

ω

ωLO

ωLO channel Desired

channel Desired

Interferer Interferer

image image

filter reject image

filter reject image

filter select channel

filter select channel

ωIF

ωIF

) (a

) (b ωIM

ωRF

Figure 2.2 Rejection of image versus suppression of interferers for (a) large ω_IF (b) small ω_IF

relatively sharp cutoff characteristics. The simple homodyne architecture is shown in Fig. 2.3. But quadrature outputs are needed for frequency and phase-modulated signals, since the two sides of FM or QPSK spectra carry different information.

In recent years, this architecture becomes the topic of active research gradually due to the following reasons:

(1) The problem of image is removed due to ω_IF = . Therefore no image filter is 0 required, and the LNA need not drive a 50-Ω load.

(2) It is attractive for monolithic integration because this architecture needs less external components.

For the above reasons, this architecture is suitable for low-power and single-chip design. But some extra issues that do not exist or are not as serious in a heterodyne receiver must be entailed, such as channel selection, DC offset, I/Q mismatch, even-order distortion, and flicker noise.

2.2 Wireless Local Area Network

In recent years, wireless local area networks (WLANs) become an important role in our life gradually. Some standards were established to regulate the development of the

LNA

Mixer

LPF

VCO signal

RF Baseband signal

Figure 2.3 Simple homodyne receiver architecture

WLNAs. A brief introduction of our application is listed below:

IEEE 802.11a

The IEEE 802.11a standard was defined by the Institute of Electrical and Electronics Engineers in 1999. The channelization scheme for this standard is shown in Table 2.1 and Fig. 2.4, and its physical layer is based on a 52 sub-carriers orthogonal frequency division multiplexing (OFDM) modulation scheme.

Table 2.1 - The set of the channelization

Regulatory domain Band Channel center frequencies United States U-NII lower band

5.15-5.25 (GHz) 5180 MHz, 5200 MHz 5220 MHz, 5240 MHz United States U-NII middle band

5.25-5.35 (GHz)

5260 MHz, 5280 MHz 5300 MHz, 5320 MHz United States U-NII upper band

5.725-5.825 (GHz)

5745 MHz, 5765 MHz 5785 MHz, 5805 MHz

This OFDM system provides a wireless LAN with data payload communication capabilities of 6, 9, 12, 18, 24, 36, 48, 54 Mbits/s, and its rate-dependent modulation parameters is shown in Table 2.2.

5180 5200 5220 5240 5260 5280 5300 5320

5150 5350

Edge Band

Lower Upper BandEdge

Spacing

5725 5745 5765 5785 5805 5825 Edge

Band

Lower Upper BandEdge

MHz

Figure 2.4 802.11a channel distribution

Table 2.2 - Rate-dependent parameters Data rate

(Mbits/s) Modulation Coding rate

Coded bits per subcarrier

Coded bits per OFDM symbol

Data bits per OFDM

symbol

6 BPSK 1/2 1 48 24 9 BPSK 3/4 1 48 36 12 QPSK 1/2 2 96 48 18 QPSK 3/4 2 96 72

24 16-QAM 1/2 4 192 96

36 16-QAM 3/4 4 192 144

48 64-QAM 2/3 6 288 192

54 64-QAM 3/4 6 288 216

For a NF of 10 dB and 5 dB implementation margins, the minimum input levels are shown in Table 2.3, and the maximum input power level is -30 dBm.

Table 2.3 – Receiver performance requirements Data rate

(Mbits/s) Minimum

sensitivity (dBm) Adjacent channel

rejection (dB) Alternate adjacent channel rejection (dB)

6 -82 16 32

9 -81 15 31

12 -79 13 29

18 -77 11 27

24 -74 8 24

36 -70 4 20

48 -66 0 16

54 -65 -1 15

2.3 Noise Basic

Noise can be loosely defined as any random interference unrelated to the signal of interest, and noise is characterized by a PDF and a PSD. In analog circuits, the signal-to-noise ratio (SNR), defined as the ratio of the signal power to the total noise power, is an important parameter. But in RF design, most of the front-end receiver blocks are characterized in terms of their noise figure, which is a measure of SNR degradation due to the added noise from the circuit/system, rather than the input-referred noise. Noise factor can be expressed as

source input to due power noise

output

power noise output total

factor

noise = (2-1)

the noise figure (NF) is simply the noise factor expressed in decibels. If a system has no noise, then noise figure is 0 dB regardless of the gain. In reality, the finite noise of a system degrades the SNR, yielding noise figure > 0 dB. For those whose noise factor is quite close to unity, noise temperature, TN, is an alternative way of expressing the effect of noise contribution due to its higher-resolution description of noise performance, and is defined as the increase in temperature required of the source resistance for it to account for all of the output noise at the reference temperature Tref (which is 290 K). It is related to the noise factor as follows:

1) -factor (noise T

T T 1 T factor

noise _{N ref}

ref

N ⇒ = ⋅

+

= (2-2)

2.3.1 Noise Source Thermal noise:

Thermally agitated charge carriers in a conductor constitute a randomly varying current that gives rise to a random voltage due to their Brownian motion. Thermal noise is often called Johnson noise or Nyquist noise. The noise voltage has a zero average value, but a nonzero mean-square value.

In a resistor R, thermal noise can be represented by a series noise voltage source

2 4

vn = kTR f∆ or by a shunt noise current source ² 4

n i kT f

R

= ∆ , where k is

Boltzmann’s constant (about 1.38×10^-23 J/K), T is the absolute temperature in Kelvins, and Δf is the noise bandwidth. However, purely reactive elements generate no thermal noise.

Shot Noise:

(1) There must be direct current flow.

(2) There must be energy barrier over which a charge carrier hops.

Charge comes in discrete bundles. The randomness of the arrival time gives rise to the whiteness of shot noise. Therefore the shot noise can be modeled by a shunt noise current source i_n² =2qI_DC∆ , where q is the electronic charge, If DC is the DC current in amperes, and ∆f is the noise bandwidth in hertz.

Flicker Noise:

Flicker noise appears as 1/f character and is found in all active devices, as well as in some discrete passive element such as carbon resistors. In diodes, flicker noise is caused by traps associated with contamination and crystal defects in the depletion regions. The traps capture and release carriers in a random fashion and the time constants associated with the process give rise to the 1/f nature of the noise power density. The flicker noise in diode can be represented as ²_j

j

i K I f

= f A⋅ ⋅ ∆ , where K is the process-dependent constant, Aj is the junction area, and I is the bias current. In MOSFET, charge trapping phenomena are invoked in surface, and his type of noise is much greater than that of the bipolartransistor. The flicker noise in MOSFET can be given by

2 2 2

2

n m T

ox

g

K K

i f A f

f WLC f ω

= ⋅ ⋅ ∆ ≈ ⋅ ⋅ ⋅ ∆ (2-3)

where K is the process-dependent constant and A is the area of the gate.

2.3.2 Noise Model of MOSFET

The dominant noise source in CMOS devices is channel noise, which basically is thermal noise originated from the voltage-controlled resistor mechanism of a MOSFET. This source of noise can be modeled as a shunt current source in the output

circuit of the device. The channel noise of MOSFET is given by device. Another source of drain noise is flicker noise and is given by (2-3). Hence, the total drain noise source is given by

WLC f

At RF frequencies, the thermal agitation of channel charge leads to a noisy gate current because the fluctuations in the channel charge induce a physical current in the gate terminal due to capacitive coupling. This source of noise can be modeled as a shunt current source between gate and source terminal with a shunt conductance gg, and may be expressed as

f

and δ is the gate noise coefficient. This gate noise is partially correlated with the channel thermal noise because both noise currents stem from thermal fluctuations in the channel, and the magnitude of the correlation can be expressed as

j

where the value of -0.395j is exact for long channel devices. Hence, the gate noise can be re-expressed as

where the first term is correlated and the second term is uncorrelated to channel noise.

From previous introduction of MOSFET noise source, a standard MOSFET noise model can be presented in Fig. 2.5, where i is the drain noise source, _nd² i is the _ng² gate noise source, and v is thermal noise source of gate parasitic resistor _rg² r . _g

2.3.3 Noise Figure of Cascaded Stages

For a cascade of m stages, the overall noise figure can be characterized by Friis formula

) 1 ( 1

1 2

... 1 ) 1

1 (

1

−

+ −

− + +

− +

=

m p

m p

total A

NF A

NF NF

NF (2-10)

where NF is the noise factor of stage n, and _n A denotes the power gain of _pn stage n. This equation indicates that the noise contributed by each stage decreases as the gain preceding the stage increases. Hence, the first few stages in a cascade are the most critical for noise figure. But if a stage exhibits attenuation, then the noise figure of the following circuit is amplified when referred to the input of that stage.

2.4 Linearity Basic

The nonlinearity of the system often leads to interesting and important phenomena,

G

S

C

gs

D

S

2

i

ng

v

^gs

g

m

v

gs

r

_o

i

_nd²

2

v

rg

r

_g

-+

Figure 2.5 Standard noise model of MOSFET

such as harmonics, gain compression, desensitization, blocking, cross modulation, intermodulation, etc. These distortions will degrade the performance of the system.

Volterra series will be used for distortion computations. It can provide designers some information to derive which circuit parameters or circuit elements they have to modify in order to obtain the required specifications. Therefore, we introduce Volterra series in the section.

2.4.1 Fundamental of the Volterra Series

In fact a Volterra series describes a nonlinear system in a way which is equivalent to the way Taylor series approximate an analytic function. A nonlinear system which is excited by a signal with small amplitude can be described by a Volterra series which can be broken down after the first few terms. The higher the input amplitude, the more terms of that series need to be taken into account in order to describe the system behavior properly. For very high amplitudes, the series diverges, just as Taylor series.

Hence, Volterra series are only suitable for the analysis of weakly nonlinear circuits.

The Volterra series approach has been proven to very attractive for hand calculations of small transistor networks. Since Volterra kernels retain phase information, they are especially useful for high-frequency analysis.

H

1

H

n

H

2

) (t

x y (t )

M M

Figure 2.6 Schematic representation of a system characterized by a Volterra series

The theory of Volterra series can be viewed as an extension of the theory of linear, first-order systems to weakly nonlinear systems. And a system is considered as the combination of different operators of different order in the Volterra series description, as shown in Fig. 2.6. Every block H1, H2, and Hn represents an operator of order 1, 2, and n, respectively. How much operators must be used is dependent on the input amplitude. In general, the weakly nonlinear effects can be described accurately by taking into account third-order effects only.

In the time domain, the transformation on an input signal, x(t), performed by a nth-order Volterra operator is given by

∫

the n-dimension integral is seen to be an nth-order convolution integral. The function

) be represented as the sum of the output of a first-order Volterra operator with the output of a second-order one, a third-order one, and so on, as shown in Fig. 2.6. The Volterra series representation of the nonlinear system can be expressed as

)]

In the frequency domain, the nth-order Volterra kernel can be given by

∫

and is called the nth-order nonlinear transfer function or the nth-order kernel transform.

2.4.2 Nonlinear Performance Parameters in Terms of Volterra Kernels When a system that can be described by a Volterra series up to order three, is excited by the sum of two sinusoidal excitations A₁cosω and ₁t A₂cosω , then the ₂t output is given by the sum of the responses listed in Table 2.4. From Table 2.4, the

Table. 2.4 Different responses at the output of a nonlinear system described by Volterra kernels.

Order Frequency of response Amplitude of response Type of response 1 compression or

expansion

expressions for the second and third harmonic distortion in terms of general Volterra

Furthermore, among the intermodulation products, the third-order intermodulation products at 2ω₁−ω₂ and 2ω₂ −ω₁ is important. Since if the difference between ω and 1 ω is small, the distortions at ₂ 2ω₁−ω₂ and 2ω₂ −ω₁ will appear in the vicinity of ω and ₁ ω . Using Table 2.4 the third-order intermodulation distortion in ₂ terms of Volterra kernel transforms

)

This effect causes some distortion at our desired frequency and damages desired signals. Therefore third intercept point (IP3) is used to characterize this behavior. This parameter is measured by supplying a two-tone signal to the system. This input signal must be chosen to be sufficiently small in order to remove higher-order nonlinear terms. In a typical test, A1=A2=A, hence the magnitude of third-order intermodulation products grows at three times the rate at which the fundamental signal on a logarithmic scale when input signal increases. The third-order intercept point is defined to be the point at which third-order intermodulation product equals to the fundamental signal, and the corresponding input signal is called input IP3 (IIP3) and the corresponding output signal is called output IP3 (OIP3). The A_IP3, therefore, can be obtained by setting IM₃ =1 and expressing as

)

Besides, a quick method of measuring IIP3 is as follows. As shown in Fig. 2.7, If the power of the two-tone signal, Pin, is small enough to ignore higher order nonlinear terms, then IIP3 can be expressed as

dBm

Pin input power(dBm) power(dBm)

= fundamenta lsignal

IM3

(a) (b)

Figure 2.7 (a) Growth of output components in an intermodulation test (b) Intermodulation distortion

CHAPTER 3

Design Consideration in Front-End Circuit Design

3.1 Low Noise Amplifier Basic

Low noise amplifier is the first gain stage in the receive path so its noise figure directly adds to that of the system. There, therefore, are several common goals in the design of LNA. These include minimizing noise figure of the amplifier, providing enough gain with sufficient linearity and providing a stable 50 Ω input impedance to terminate an unknown length of transmission line which delivers signal from antenna to the amplifier [5]. Among LNA architectures, inductive source degeneration is the most popular method since it can achieve noise and power matching simultaneously, as shown in Fig. 3.1. The following analysis is based on this architecture.

3.1.1 Low Noise Amplifier Architecture Analysis In Fig. 3.1, the input impedance can be expressed as

Zin

Ls

Lg

M1

Figure 3.1 Common-source input stage with inductive source degeneration

gs

As shown in (3-1), the input impedance is equal to the multiplication of cutoff frequency of the device and source inductor at resonant frequency. Therefore it can be set to 50 Ω for input matching while resonant frequency is designed to be equal to the operating frequency.

According to prior introduction, the equivalent noise model of common-source LNA with inductive source degeneration can be expressed as Fig. 3.2, where R is _l the parasitic resistance of the inductor, R_g is the gate resistance of the device. Note that the overlap capacitance Cgd has also been neglected in the interest of simplicity.

Then the noise figure can be obtained by computing the total output noise power and output noise power due to input source. To find the output noise, we first evaluate the transconductance of the input stage. With the output current proportional to the voltage on Cgs and noting that the input circuit takes the form of series-resonant network, the transconductance at the resonant frequency can be expressed as

s

Figure 3.2 Equivalent noise model of Figure 3.1

where Qin is the effective Q of the amplifier input circuit. So the output noise power

Furthermore, channel current noise of the device is the dominant noise contributor, and its noise power density associated with the correlated portion of the gate noise can be expressed as

, 2

The last noise term is the contribution of the uncorrelated portion of the gate noise, and its output noise power density can be expressed as

, 2

According to (3-3), (3-4), (3-5) and (3-8), the noise figure at the resonant frequency can be expressed as



From (3-11), we observe that χ includes the terms which are constant, proportional to Q_L, and proportional to Q . It follows that (3-11) will contain terms _L² which are proportional to Q_L as well as inversely proportional to Q_L. A minimum noise figure, therefore, exits for a particular Q_L.

3.1.2 Optimizations of Low Noise Amplifier Design Flow

The analysis of the previous section can now be drawn upon in designing the LNA.

In order to pick the appropriate device size and bias point to optimize noise performance given specific objectives for gain and power dissipation, a simple second-order model of the MOSFET transconductance can be employed which accounts for high-field effects in short channel devices. Assuming that the drain current, Id, has the form

ρ

The noise figure can be expressed in terms of PD and Vgs. Two parameters linked to

The noise figure can be expressed in terms of PD and Vgs. Two parameters linked to

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