Linearity

As far as cascaded stages are concerned, linearity is a very important performance in mixer stage. In general, it will dominate the distortion of the entire receiver. The detail analysis will be introduced in Chapter 4.

CHAPTER 4

5.5 GHz Low-Power and High-Linearity Mixer

The mixer is based on the conventional doubly balanced CMOS Gilbert Cell mixer, as shown in Fig. 3.7 and it is composed of transconductance stage, mixing stage, load impedance and current source. The doubly balanced configuration exhibits following advantages:

(a) It generates less even-order distortion resulted from transconductance stage.

(b) It has less LO-IF feed-through. Because the differential pairs M3-M4 and M5-M6 add the amplified LO signal with opposite phases, thereby providing a first-order cancellation.

4.1 Low-Power Design Consideration

Since each of conducting MOSFETs are ideally in saturation, the expected drain to source voltage is V_T +200mV , neglecting body effect. Consequently, this architecture needs at least 3V_T +600mV . This high voltage is not suitable for low-power design therefore we adopt following techniques to reduce supply voltage.

4.1.1 Low Voltage Topology

In order to reduce supply voltage, we adopt a typical low-voltage topology shown in Fig. 4.1(a). This topology uses two RF traps and one coupling capacitor. The function of the RF traps is provide a low impedance across its terminals at dc and high impedance at RF, and the function is usually realized by using on-chip LC tanks. The function of the coupling capacitor is used to couple the RF energy between the two

elements. Therefore the dc equivalent circuit becomes two independent biasing paths, as shown in Fig. 4.1(b), and the function of the ac equivalent circuit is the same as that of the cascode topology [3]. So this topology can achieve following advantages:

(a) Lower supply voltage.

(b) The property of the cascode topology is retained.

(c) The two paths can be biased at different bias condition based on the different consideration.

4.1.2 Narrowband Source-Coupled Pair

As shown in Fig. 4.2 (a), the first stage of the Gilbert cell mixer is the source-coupled pair transconductance stage. The high impedance of the current source forces the output currents to be balanced when input signal is unbalanced. On the other hand, if the input signal is perfectly differential, the output current is also balanced. The architecture is unsuitable for low-power design since the current source needs at least V_T +200mV . In some cases, the current source is removed to reduce

rail bias Bottom

rail bias Top

rail bias Top

rail bias Bottom

element1 element2 element1 element2 element2element1

trap RF trap

RF ACGND

GND AC pass

by circuit

equivalent

DC ACequivalentcircuit

(a)

(b)

(c) Figure 4.1 Low-voltage topology

supply voltage, but the drawback of the omission is that the mixer will not reject unbalance in the RF differential inputs. Therefore we adopt a LC tank to replace the conventional current source, as shown in Fig. 4.2 (b). In dc biasing condition, the inductor provides a low resistance path for the dc bias current of M1 and M2 to ground, hence it almost needs no dc voltage drop across the source-coupled pair. At the operating frequency, the high impedance of the tank exhibits the ac function of the current source when the resonance frequency of the tank is tuned at ω₀ (i.e.,

02

/

1 LC =ω ).

The detail analysis is as follows. In Fig. 4.2 (b), the current of the M1 and M2 can be expressed as

2 1

1 ( )

2 ^{B x}

n V v V

I = K + − (4-1)

2 2

2 ( )

2 ^{B x}

n V v V

I = K + − (4-2)

where K is the large signal transconductance parameter. The voltage _n V of the _x common-source node can be expressed as (4-3) by using Kirchoff’s current law

∫

+

=

+ Vxdt

L dt CdV I

I ^x 1

2

1 (4-3)

M1 M2

C L Vx

I1 I₂

ISS

1 th

B V v

V + + V_B +V_th +v₂

(a) (b)

Figure 4.2 Source-coupled pair (a) conventional approach (b) narrowband approach

Thus, from (4-1), (4-2) and (4-3), we can obtain (4-4) can be expressed as

ψ ω +

= A t

Vx sin ₀

2 (4-5)

where ψ represents the solution of the nonlinear differential equation, (4-6),

A t can be expressed as

ψ

=

Vx (4-7)

and the solution can be verified in Fig. 4.3.

50 100 150 200 250 300

time (ps) time (ps)

Voltage (mV) v1 v2 Vx Voltage (mV) v1 v2 Vx

(a) (b)

Figure 4.3 (a) Differential input signal (b) Single-ended input signal

As shown in Fig. 4.3, if the input signal is single-ended, the common-source terminals will have a voltage wave of 1/2 the input amplitude. On the other hand, the common-source terminals will exhibit no power at ω₀ when input signal is differential pair. Therefore the transconductance stage responds to difference between

v1 and v₂. In other words, the common-mode gain is reduced by the LC tank.

Besides, the differential output current can be expressed as )

sin(

)

sin( _{0 0}

2 1

0 I I g A t K A t

I = − = _m ω − _nψ ω (4-8)

In (4-8), the first term is the linear transform, and the second term is the distortion signals. Of particular interest is the third-order distortion term which is generated by multiplying the second-harmonics (2ω₀) of the ψ and the sin(ω₀t). Thus the low impedance at 2ω₀ will cause lower second-harmonics and get better linearity than that of the conventional current source.

4.2 Analysis of Linearity

In low-power RF transceiver design, linearity requirement becomes more and more challenging. Circuit nonlinearity results in various system distortions associated with the even- and odd-order nonlinearities. Of these distortions, the third-order intermodulation is one of the most critical terms responsible for linearity degradation in general RF systems. Due to the fact, how to improve the linearity of RF circuits without extra power consumption becomes an important topic to be studied.

As far as cascaded stages are concerned, system design calls for high linearity in the mixer stage to alleviate the distortion issues. A mixer is generally composed of a transconductance amplifier and a switching stage. Linearity is most limited by the transconductance amplifier, and therefore we will discuss the nonlinear effect of the

common-source amplifier in section 4.2.1.

In recent years, several techniques have been proposed to improve the linearity of MS/RF circuits by linearization of the nonlinear transconductance, such as degeneration feedback [5] and a bisymmetric Class-AB stage [6]. Another scheme is the superposition of auxiliary transistors operated in different bias conditions to null the derivative of device transconductance [7, 8]. Combined with the technique of out-of-band impedance termination, circuit linearity can be further enhanced, as indicated by the Volterra series analysis [9, 10]. The scheme, named as derivative superposition or multiple gated transistors (MGTR), offers a good opportunity to extend linearity without increasing power consumption, and is introduced in section 4.2.2.

Reference [10] gives designs showing that the device size of the auxiliary transistor (AT) is larger than that of the main transistor (MT), which does not precisely match to the derivative cancellation analysis derived through DC transconductance analysis. It is proposed that a complex transconductance shall be employed to search for the optimal design parameters. Therefore we propose a compact box-type equivalent circuit for the design of the multiple gated transistors technique in section 4.2.3.

4.2.1 Nonlinear Effects of Common-Source Amplifier

For the common-source amplifier, the nonlinear effect is dominated by the transconductance and the output conductance of the device. The nonlinear effects of the capacitances and substrate can be neglected, and they can be considered as linear elements [11]. Therefore we only consider the transconductance and the output conductance as the nonlinear source for the following analysis.

Fig. 4.4 shows a common-source amplifier, where Z1 is the input impedance, and Z2 is the output impedance. From the above-mentioned introduction and assuming that the common-source amplifier works in the weakly nonlinear region, the

equivalent circuit of the common-source amplifier can be shown as Fig. 4.5, where the transconductance (g_m) and the output conductance (r₀) are the nonlinear elements.

Therefore the I-V curve of the device can be expressed as

....

The nonlinear distortion can be obtained by calculating the Volterra kernels of order one, two and three of voltages [12].

Figure 4.5 Equivalent circuit of the common-source amplifier

V

in

Z

2

Z

1

Figure 4.4 Common-source amplifier

First-order kernels

In order to obtain the first-order Volterra kernels, the nonlinear elements must be replaced with its linearized equivalent, as shown in Fig. 4.6. Applying Kirchoff’s current law at node 1 and 2 in Fig. 4.6 yields: transfer functions indicates the order of the transfer function, whereas the second subscript corresponds to the numbering of the node voltages. Then the first-order kernels H₁₁(s) and H₁₂(s) can be expressed as

Figure 4.6 Linearized equivalent of the circuit of the Fig. 4.5

)

Second-order kernels

For computing second-order kernels, the input signal v is replaced by a short _in circuit, and the second-order nonlinear current sources are applied to the linearized circuit, as shown in Fig 4.7. Applying Kirchoff’s current law at node 1 and 2 in Fig.

4.7 yields:

Figure 4.7 Equivalent circuit for the computation of the second-order kernels in Fig. 4.5

)

Third-order kernels

Just as second-order kernels, the third-order ones are computed as the response to the third-order nonlinear current sources, as shown in Fig. 4.8. Applying Kirchoff’s current law at node 1 and 2 in Fig. 4.8 yields:

Figure 4.8 Equivalent circuit for the computation of the third-order kernels in Fig. 4.5

)

Of the nonlinear distortions, the third-order intermodulation is one of the most critical terms responsible for linearity degradation in general RF systems. In order to obtain the third-order intermodulation distortion, input signal is replaced by a two-tone test signal (V₁ = Asin(ω₁t) V₂ = Asin(ω₂t)), and the fundamental signal at ω and the distortion at ₁ 2ω₁−ω₂ must be computed by (4-12) and (4-27). By assuming s₁ =s₂ = jω₁ =s , s₃ =−jω₂ ≈−s , and jω₁− jω₂ =∆s , then the third-order intermodulation distortion (IM ) can be expressed as ₃

| 0.18um RFCMOS device by ADS simulator and o denotes the calculated result of (4-28). The calculated result has good agreement with harmonic-balance simulation except v_gs ≈0.58V , where the g^"_m is around zero so the neglected extrinsic elements and nonlinear effects of other elements becomes relatively important and

Figure 4.10 Nonlinear effects of the transconductance and the output conductance

Figure 4.9 The third-order intermodulation distortion (IM₃). The device size is nr=16, width=2.5um, and length=0.18um.

The nonlinear distortions result from the nonlinear effects of the transconductance and the output conductance and vary with different load impedance. Fig. 4.10 shows the influence of the two nonlinear elements. Solid line denotes the nonlinear effects of the output conductance, and dash line denotes the nonlinear effects of the

transconductance. As shown in Fig. 4.10, the linearity is dominated by the device transconductance in the case of low load impedance.

4.2.2 Multiple Gated Transistors Method

According to above discussion, the I-V curve of the device can be rewritten as

....

and (4-28) can be simplified as ) drain current nonlinear term,A(s) is the linear transfer function for the input voltage of v_gs, and can be expressed as generally much larger than its second term in the general case. The major effort,

therefore, is to reduce the g_m^" .

Fig. 4.11(a) is a common-source architecture, and its small-signal parameter, gm&g_m^' &g^"_m, is shown in Fig. 4.12. The g^"_m arrives its positive peak value in the subthreshold region, and it arrives a negative peak value in the gate drive voltage range of 0.1~0.4V, which is the usual bias voltage for high-gain, low-noise, and low-power applications. This negative value will cause serious linearity degradation.

Ref. [10] introduces multiple gated transistors (MGTR) technique, as shown in Fig.

4.11(b). The main transistor (MT) provides the gain of the circuit. The auxiliary transistor is used to cancel the g_m^" of the MT by selecting appropriate size and biasing voltage. Fig. 4.13 shows the results. In this plot the device sizes of MT and AT are chosen as finger numbers of 16 and 12 (NF=16, 12), respectively, and the shift voltage, Vshift, is 0.18V. As can be seen, gm” appears close to zero in the superposed configuration. The best gate bias voltage, Vgs, is revealed to be as 0.65V. The shift voltage actually drives AT in the subthreshold region consuming insignificant power.

M1

MT AT

VDD

VDD

C1

C2

Vgs

shift

gs V

V −

signal input signal

input

(a) (b)

Figure 4.11 (a) Common-source architecture (b) MGTR architecture

-0.6 0.0 0.6

0.4 0.5 0.6 0.7 0.8

gate bias voltage Vgs(V)

single transistor MGTR

) (A/V

³

"

g

m

Figure 4.13. Cancellation of DC gm”in MGTR configuration. The device sizes of MT and AT are NF=16 and 12, respectively. Vshift=0.18V.

0 5 10 15 20

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

) / (mA V g_m

) (V V_gs )

(a

0.00 0.02 0.04 0.06 0.08

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

) /

' (A V g_m

) (V V_gs )

(b

-0.6 0.0 0.6

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

) /

" (A V g_m

) (V V_gs )

(c

Figure 4.12 Small-signal parameter of NMOS (a) g_m (b)g_m^' (c)g^"_m

Harmonic-balance simulation of the amplifier circuit at 5.5GHz does indicate linearity improvement, as shown in Fig. 4.14. Nevertheless better linearity improvement can be still found in the case that the size of AT is NF=20, and Vshift, is 0.21V. Obviously this size does not match to previous analysis.

Essentially nonlinear distortion is frequency-dependent. By using DC transconductance the conventional analysis lacks of accuracy to predict the high-frequency operating condition and to obtain the truly optimized linearity. This error results from the lacks of the extrinsic elements in deep sub-micro CMOS technologies. If the analysis method of the DC gm includes all intrinsic and extrinsic elements, this will cause that DC gm method is too complicated to get optimized transistor size and gate bias shifting of the auxiliary transistor for circuit. A new method using complex AC transconductance is therefore introduced in this study to achieve optimized transistor size tuning and gate bias shifting for the auxiliary transistor.

4.2.3 Complex Transconductance Analysis

Fig. 4.15 show a transconductance amplifier using MGTR technique, including the source impedance, Zg, the load impedance, ZL, and the source-degeneration circuit

-200 -190 -180 -170 -160

0.4 0.5 0.6 0.7 0.8

gate bias voltage V^gs(V) Third order intermodulationproduct (dBm)

Simulation (AC Gm) Simulation (DC gm) Calculation (AC Gm)

Simulation_single transistor

*

Figure 4.14 The third-order intermodulation distortions at 5.5GHz by harmonic-balance simulations and equation calculations.

impedance Zs. Without loss of generality in this nonlinear analysis, the superposed configuration in MGTR can be simply represented by the input impedance Zin(ω) and the transconductance element Gm(ω). The transconductance Gm is defined in the same way as the ratio of the output current to the input voltage, including all the intrinsic and extrinsic frequency-dependency of MOSFET devices. It could be a complex value at high frequencies. Its nonlinearity shall be related to the load impedance and the operation frequency. Consequently the equivalent circuit model of a transconductance amplifier is shown in Fig. 4.16.

Similar to (4-30), the I-V curve of the device can be expressed as

MT AT Z

_L

Z

s

Z

g

V

gs

V

_gs

− V

_shift

Figure 4.15 MGTR architecture

V

s

Z

s

V

in

Z

g

Z

in

G

_m

v

_in

Z

L

+

-Figure 4.16 Equivalent circuit of the Fig. 4.15

....

, and the third-order intermodulation product IMD3 in a two-tone test is derived by Volterra series analysis and expressed as

| conducted in the complex domain as shown in Fig. 4.17. This complex transconductance analysis actually suggests that the device sizes of MT and AT are chosen as NF=16 and 20, respectively, and Vshift as 0.21V. In addition, calculation by (4-36) has good agreement with harmonic-balance simulation, as shown in Fig. 4.14.

Although there is some error, which results from the neglected feedback effect of the device, its result has good agreement with simulation in general. This validates the usefulness of the compact box-type equivalent circuit model

4.3 Chip Implementation and Measured Result

4.3.1 Circuit Implementations

Following the low-power technique and complex transconductance analysis, a low-power and high-linearity direct down-conversion mixer is designed. The mixer is a fully differential folded Gilbert mixer, consisting of the MGTR transconductance and the switching stage. The schematic is shown in Fig. 4.18.

According to the discussion in the section 4.1, the folded topology is beneficial to lower power design since the traditional cascoded Gilbert cell mixer requires a supply

-0.1 0 0.1

-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5

MGTR

transistor Single

∆

) (A/V ) m(G

I ^"_m ³

) (A/V ) e(G

R ^"_m ³

0.62V V_gs =

r) transisto (single

0.21V V

0.62V,

V_gs = _shift =

(MGTR)

(a)

0 0.2 0.4 0.6

0.4 0.5 0.6 0.7 0.8

gate bias voltage Vgs(V) )

)(A/V (G

Magnitude ^"_m ³

single transistor MGTR

(b)

Figure 4.17 Cancellation of AC Gm” in MGTR configuration. The device sizes of MT and AT are NF=16 and 20, respectively. Vshift=0.21V.

voltage of at least triple threshold voltage. In addition, the transconductance and the switching stages can be biased differently at a high current level and a low level, respectively, to achieve high gain and noise suppression. LC tanks are further applied to supply current driving without voltage drop and provide high impedance at the desired frequency.

The MGTR consists of M1 – M4. M1 and M2 are MT providing major gain of the mixer, and M3 and M4 are AT compensating for the third-order nonlinear distortion.

The device sizes are as NF=16 and 20 for MT and AT, respectively, and the bias conditions are Vgs=0.62V and Vshift=0.21V. The input matching network includes an on-chip inductor, the bond pad, and the bond wire. The switching stage is implemented

VDD VDD

M5 M6 M7M8

+

LO LO− LO+

−

IF IF+

R

L

R

L

shift

g

V

V −

V

g

V

_g

C2 C4 C3

C1

M4 M3

M2 M1

C

pad

L

1

L

₂

L

_bondwire

+

RF RF−

shift

g

V

V −

R

5

R

₆

R

1

R

4

R

3

R

2

C

pad bondwire

L

Figure 4.18 Schematic of the folded MGTR direct conversion mixer.

by four PMOS transistors, M5 – M8, since this stage does not need high ω_T. The flicker noise is a concern for direct down-conversion mixer because its corner is around 1MHz, and it can be expressed as (2-3). Therefore increasing the transistor length and decreasing the bias current of transistor is a solution to decrease flicker noise.

4.3.2 Experimental Results

The MGTR mixer is fabricated using 0.18um RF CMOS technology. The full chip of circuit is shown by microphotograph in Fig. 4.19. The total die area including bonding pads is 1.09 mm by 1.08 mm. Measurement is conducted by mounting the mixer die on FR4 board, as shown in Fig. 4.20. Input testing signal is transformed into a differential form at RF and LO ports by hybrid couplers which gain error and phase error are smaller than 0.8dB and 8° respectively from 4GHz to 8GHz. Fig. 4.21 shows the measurement diagram. A unit gain output buffer is used to transform the differential

RF+

RF-LO+

LO-IF+ IF-VDD

VDD

Figure 4.19 Microphotograph of MGTR mixer

signal into the single-ended form, and provides high input impedance to reduce loading effect.

Figure 4.20 PCB layout of the MGTR mixer

Balun

Balun

Mixer bondwire

bondwire bondwire

+ Ω

-8K

Ω 8K

Ω 8K

Ω 8K RF

LO

IF

Figure 4.21 Measurement diagram including unit gain output buffer

Fig. 4.22 shows the single-end input return loss. The measured result exhibits a higher input-matching frequency. The discrepancy between measured data and simulation result on the input return loss may be due to the variation of the parasitic bond-wire inductance, pad capacitance, and input-matching inductor. We adjust the value of the bond-wire inductance to 1.5nH and the parasitic capacitance of the pad to 30fF. The value of input-matching inductor is added by 0.2nH, and then the simulation result has better agreement with the measured data. And the deeper phenomenon may result from the parasitic effect of the SMA connectors and the FR4 board. The measured conversion gain is 4.7 dB. Fig. 4.23 shows the measured input P-1dB of 0.2 dBm. Fig. 4.24 shows the measured IIP3 of the MGTR folded mixer at two conditions. One is the MGTR operation condition, and the other is single transistor condition that the AT gate bias voltage is ground. As can be seen, linearity improvement achieves more than 7 dB without extra power consumption. And Fig. 4.25 shows the IIP3 variation at different bias voltage of the AT. Complete measured results are

2 3 4 5 6 7 8 9

1 10

-20 -15 -10 -5

-25 0

Frequency (GHz) S11 (dB)

Sim. result after trouble shooting Sim. result

Mea. result of port1 Mea. result of port2

Figure 4.22 Single-end input return loss of the MGTR mixer

summarized in Table 4.1 together with simulation results for comparison. In Table 4.2 listed is comparison of circuit performance with previous work.

-20 -15 -10 -5 0 5 10

-20 -15 -10 -5 0 5 10

Input power (dBm)

Output power (dBm) P-1dB : 0.2 dBm

Figure 4.23 P-1dBmeasurement of MGTR mixer.

-100 -80 -60 -40 -20 0 20

-35 -25 -15 -5 5 15

Input power (dBm)

Output power (dBm)

Conventional mixer IIP3 : 3.2 dBm

MGTR mixer IIP3 : 10.3 dBm

IIP3 : 7.1 dB increase

Figure 4.24 IIP3 measurement of conventional mixer and MGTR mixer.

Table 4.1. Summary of simulation and measured results of MGTR mixer.

Simulation Measurement

Process TSMC 0.18um RFCMOS

Frequency 5.5 GHz 5.5 GHz

Supply voltage 1.0 V 1.0 V

Conversion gain 8.3 dB 4.7 dB

S

₁₁

-13.4 dB - 9 dB

P

-1dB

-3.5 dBm 0.2 dBm

LO power -1 dBm 5.3 dBm

IIP3 3.8 dBm 10.3 dBm

Noise Figure (DSB) 13.9 dB @ 1MHz 20.9 dB@ 10MHz LO-RF isolation -60.9 dB -47.5 dB

Power consumption 2.2 mW 1.8 mW

-3 0 3 6 9 12

0 0.1 0.2 0.3 0.4 0.5 0.6

Bias voltage of AT (V) IIP3 (dBm)

Figure 4.25 IIP3 measurement versus AT gate bias voltage

Table 4.2. Performance comparison of CMOS mixers.

RF frequency

(GHz) IIP3/DC

(dBm/mW)

This work 5.5 10.3/1.8

Ref. [10] 2.4 9/5.4

Ref. [13] 8 3.5/6.9

Ref. [14]* 2.5 -1/2.8

* simulation results

4.3.3 Discussions

A low-power and high-linearity folded direct conversion mixer, intended for use in

A low-power and high-linearity folded direct conversion mixer, intended for use in

在文檔中 利用複數導數相消之低功率、高線性度混波器 (頁 41-0)