CHAPTER 5 Low-Power Front-End Circuit
5.2 Principle of the Circuit Design
5.2.3 Direct Down-Conversion Mixer
The direct down-conversion mixer transforms the radio-frequency (RF) signal into base-band directly and needs high linearity to avoid the distortion of the signal.
Following the discussion in the section 4.1 and 4.2.3, a low-power and high-linearity direct down-conversion mixer is design, as shown in Fig. 5.8.
The folded topology is beneficial to lower power design since the traditional cascoded Gilbert cell mixer requires a supply voltage of at least triple threshold voltage.
In addition, the transconductance and the switching stages can be biased differently at a high current level and a low level, respectively, to achieve high gain and noise suppression. LC tanks are further applied to supply current driving without voltage drop and provide high impedance at the desired frequency
The MGTR consists of M1 – M4. M1 and M2 are MT providing major gain of the mixer, and M3 and M4 are AT compensating for the third-order nonlinear distortion.
The switching stage includes four PMOS transistors, M5 – M8, for the concern of Flicker noise.
4 5 6 7
3 8
-2 0 2
-4
4 Gain error (dB)
Freq. (GHz) Figure 5.7 Simulation result of gain error of the Fig. 5.5
5.3 Chip Implementation and Measured Result
5.3.1 Circuit Implementations
Following the above-mentioned analysis, a front-end circuit is designed, as shown in Fig. 5.2. The front-end circuit is fabricated using 0.18um RF CMOS technology. The full chip of circuit is shown by microphotograph in Fig. 5.9. The total die area including bonding pads is 1.14 mm by 1.4 mm.
The RF input is placed on the left side, the LO input is placed on the right side, and the IF input is placed on the down side of the chip. The placement of pads is considered for the on-board measurement. In order to minimize the effect of the substrate noise on the system, a solid ground plane, constructed using a low resistive metal-1 material, is placed between the signal pads and the substrate. Besides, there are many ground pads to minimize the effect of the bond-wire.
M4 M3
M2 M1
R5 R6
R7 R8
Vg1
Vg1
Vg2
Vg2
C1
C4
C3
C2
RL3 RL4
-IF IF+
+
− LO + LO
LO
VDD VDD
M8 M7 M6
M5 RF−
RF+
Figure 5.8 The schematic of the folded MGTR direct conversion mixer.
5.3.2 Experimental Results
Measurement is conducted by mounting the mixer die on FR4 board, as shown in Fig.
5.10. Input testing signal is transformed into a differential form at LO ports by hybrid couplers which gain error and phase error are smaller than 0.8dB and 8° respectively from 4GHz to 8GHz. Fig. 5.11 shows the measurement diagram. A unit gain output buffer is used to transform the differential signal into the single-ended form, and provides high input impedance to reduce loading effect.
LO+
RF
LO- IF-IF+
VDD
VDD
VDD VDD
Figure 5.9 Microphotograph of front-end circuit
Figure 5.10 PCB layout of front-end circuit
LNA PhaseSplitter Mixer
IF RF_input
Balun LO
8K
8K
8K 8K
wire -bond
+
+ wire
-bond
−
Figure 5.11 Measurement diagram including unit gain output buffer
The measured input return loss is plotted in Fig. 5.12 together with simulation result for comparison. The measured result has good agreement with the simulation data. The deeper phenomenon of measured input return loss may result from the parasitic effect of the SMA connectors and the FR4 board. The simulation result of DSB noise figure versus intermediate frequency (IF) is shown in Fig. 5.13 and its value is 6.9dB at IF of 1MHz.
The measured conversion gain of front-end circuit is 9.5 dB. Linearity analysis is conducted by the two-tone test. The measured result of the third-order intermodulation distortion is plotted in Fig. 5.14. Fig. 5.15 shows the measured input P-1dB of -16 dBm, and Fig. 5.16 shows the measured input second intercept point (IIP2) of 19 dBm. Complete measured results are summarized in Table 5.1 together with simulation results for comparison. The deviation of IIP2 may result from the mismatch of the devices. The equivalent input noise voltage of the output buffer is approximately equal to the noise voltage of the circuit, and this condition caused some inaccuracy.
S11 (dB)
Frequency (GHz) Simulation result
Measured result
2 3 4 5 6 7 8 9
1 10
-20 -10
-30 0
Figure 5.12 Input return loss of front-end circuit
-100 -80 -60 -40 -20 0 20 40
-35 -25 -15 -5 5
IIP3 : -2.6dBm
Input power (dBm)
O ut put po w er ( dBm )
Figure 5.14 IIP3 measurement of front-end circuit
1E1 1E2 1E3 1E4 1E5 1E6 1E7
1 1E8
10 20 30 40
0 50
IF Frequency (Hz) DSB noise figure (dB)
Figure 5.13 Simulation result of DSB noise figure
-25 -20 -15 -10 -5 0 5
-35 -30 -25 -20 -15 -10 -5
P
-1dB: -16dBm
Input power (dBm)
O ut put po w er ( dBm )
Figure 5.15 P-1dB measurement of front-end circuit
-100 -70 -40 -10 20 50
-40 -30 -20 -10 0 10 20 30
IIP2 : 19 dBm
Input power (dBm)
O ut put po w er ( dBm)
Figure 5.16 IIP2 measurement of front-end circuit
Table 5.1 Summary of simulation and measured results of front-end circuit
Simulation Measurement
Process TSMC CMOS 0.18um
Frequency 5.5 GHz 5.5 GHz
Supply Voltage 1.0 V 1.0 V
LO power 2 dBm 2.6 dBm
Conversion gain 18 dB 9.5 dB
S11 -16.3 dB -21.5 dB
Noise Figure(DSB) 6.9 dB @ 1MHz 22.5 dB@ 10MHz
P
-1dB-17 dBm -16 dBm
IIP3 -8.4 dBm -2.6 dBm
IIP2 30.3 dBm 19 dBm
Power Dissipation 8.6 mW 10.1 mW
5.3.3 Discussions
A low-power front-end circuit, intended for use in the receiver path of a wireless local area network, is designed in standard 0.18um CMOS technology. It is composed of a low noise amplifier, a phase splitter, and a direct down-conversion mixer. The improvement of the linearity of this circuit is not obvious comparing with the folded mixer in Chapter 4, and the change of in-band and out-of-band impedance may be the major reason. Measured data shows that the front-end circuit achieves conversion gain of 9.5 dB, input return loss of 21.5 dB, input third-order intercept point (IIP3) of -2.6 dBm, and input second-order intercept point (IIP2) of 19 dBm, while consuming only 10.1mW.
CHAPTER 6
Summary and Future Work
6.1 Summary
In Chapter 2, some architectures of the receiver, the IEEE 802.11a standard of wireless LAN, noise sources, and the theoretical MOSFET noise model are introduced.
Besides, Volterra series is presented for the analysis of the linearity.
In Chapter 3, the design consideration of LNA, phase splitter and mixer is introduced. By analyzing and improving these circuits, a low-power and high-linearity and a low-power front-end circuit are designed and verified.
In Chapter 4, a folded MGTR direct down-conversion mixer is analyzed and verified in standard 0.18um CMOS technology. The MGTR technique is adopted to improve the linearity of the mixer in the transconductance stage. A compact equivalent circuit using AC complex transconductance truly gives the optimal design parameters. Measured data show that the improvement of the linearity is more than 7 dB without extra power consumption.
In Chapter 5, a low-power front-end circuit, intended for use in the receiver path of a wireless local area network, is designed in standard 0.18um CMOS technology. It is composed of a low noise amplifier, a phase splitter, and a direct down-conversion mixer. The LNA uses L-degeneration to achieve noise and power matching simultaneously. The single-ended signal is transformed into a differential form by the phase splitter. And the mixer provides higher linearity by using MGTR technology.
Measured data shows that the front-end circuit achieves conversion gain of 9.5 dB,
input return loss of 21.5 dB, input third-order intercept point (IIP3) of -2.6 dBm, and input second-order intercept point (IIP2) of 19 dBm, while consuming only 10.1mW.
6.2 Future Work
The linearity can be improved by minimized the second term of (4-37), )
2 , ,
(ω ω ω
ε ∆ . The MGTR technique is an effective way to cancel the Gm"(ω) of the device. But the second term of (4-38) may become important while out-of-band impedances of source and load are altered, this condition is especially obvious when the Gm" (ω) is small. Therefore, we can keep the original performance, such as gain, noise figure, etc. and improve the linearity by fixing the in-band impedance and appropriately change out-of-band impedance. If this method is realized together with MGTR technique or used to cancel the Gm"(ω), the improvement of the linearity will be obvious.
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Vita and Publication
姓 名: 詹 維 嘉
出生日期: 中華民國七十年六月三日 學經歷:
國立彰化高級中學 (85 年 9 月~88 年 6 月) 國立清華大學電機工程學系 (88 年 9 月~92 年 6 月) 國立交通大學電子研究所碩士班 (92 年 9 月~94 年 7 月)
發表著作:
1. Wei-Chia Zhan, Chien-Nan Kuo, and Jyh-Chyurn Guo, “Low-Power and High-Linearity Mixer Design Using Complex Transconductance Equivalent Circuit,” Accepted to be presented at IEEE Custom Integrated Circuits Conference, 2005.
2. Wei-Chia Zhan, Chien-Nan Kuo, and Jyh-Chyurn Guo, “The Analysis and Application of Multiple gated transistors Using Complex Transconductance Equivalent Circuit,” Accepted to be presented at the 16th VLSI Design/CAD Symposium, 2005.