Thesis Organization - 奈米互補式金氧半製程下之低漏電電源箝制靜電放電防護電路設計

Chapter 1. Introduction

1.2 Thesis Organization

Chapter 2 introduces the gate-tunneling mechanisms and describes the gate-tunneling model in BSIM4 SPICE model. There are three main mechanisms which cause the gate-tunneling tunneling. All of the mechanisms are addressed and formulated. The gate-tunneling model is also applied to nanoscale CMOS transistors.

Chapter 3 discusses the gate leakage issue in the traditional power-rail ESD clamp circuits. The traditional power-rail ESD clamp circuit is simulated in a 65-nm CMOS process to investigate the impacts caused by the gate leakage current in the MOS capacitor.

To reduce the leakage current in the power-rail ESD clamp circuit, a novel technique is studied and a series of power-rail ESD clamp circuits are proposed and simulated in a 65-nm CMOS process.

Chapter 4 presents the experimental results. Measured results have shown that the leakage current under normal circuit operating conditions can be significantly reduced in the proposed ultra-low leakage power-rail ESD clamp circuits as compared with the traditional designs. Moreover, the ESD robustness is not deteriorated.

Chapter 5 includes some relevant discussions and Chapter 6 presents the conclusions and future work.

Chapter 2

current was exponentially dependent on the electric field strength.

In 1928, R. Fowler and L. W. Nordheim proposed the accurate description of field emission, which is based on the tunneling of electrons through the surface potential barrier.

They also derived the formula of the emission current [4], which is called the

“Fowler-Nordheim Tunneling (FNT) theory.” This theory is very important and it influences the scientists who study the tunneling mechanisms of the semiconductor nowadays.

During 1940 to 1960, the development of semiconductor science started to increase, and new devices were invented one after another. But there was a small current (about 10^-14A~10^-11A) which observed in the metal-insulator-metal or metal-insulator- semiconductor connection [5][6]. This phenomenon and the tunneling current were the same as the “Fowler -Nordheim Tunneling”. Finally the tunneling current density [7] was given by the high integration capability, CMOS technology became very important in

microelectronic applications. Since the structure consisted of metal, oxide, and semiconductor, the leakage mechanism inevitably existed. The leakage phenomenon had been investigated in the MOS structure early, and then three kinds of tunneling mechanisms [8]-[10] were observed to explain the leakage in the CMOS. These mechanism are: ECB (electron tunneling from conduction band), EVB (electron tunneling from the valence band), and HVB (hole tunneling from valence band). Since the gate oxide was quite thick in the early CMOS processes, the gate leakage did not cause serious issue.

During 1990 to 2000, due to the demand of high driving current, high operating speed, and lower power consumption, the CMOS technology was scaled down toward shorter channel length, thinner gate-oxide thickness, and lower power-supply voltage. As a result, the gate leakage current can no longer be ignored, because it is larger than the order of nanoamperes). To account for this effect, the gate-direct-tunneling-current model had been proposed in BSIM4 model [11]-[13] and it was released on Mar. 24, 2000 [14]. The the fitting parameter depending on the tunneling process, φbo is the Si/SiO₂ barrier height (3.1eV for electron and 4.5eV for hole), and φb is the actual tunneling barrier height (3.1eV for ECB, 4.2eV for EVB, and 4.5eV for HVB). N represents the density of carriers in the inversion or accumulation layer of the injecting electrode. For ECB and EVB tunneling process in both the inversion and accumulation regimes, N is expressed by

ge th g FB

where n_inv and n_acc denote the swing parameters, V_th is the threshold voltage, V_FB is the flat-band voltage, v_t is the thermal voltage, and V_ge is the gate voltage minus the gate-depletion voltage (Vg-Vpoly).

For EVB tunneling process, N can be described as

OX g

2.2 Gate Tunneling Mechanisms Described With Energy-Band Diagram

Three kinds of tunneling mechanisms were observed to explain the leakage in CMOS technology, which are shown in Fig. 2.1. ECB is the electron tunneling from the conduction band across the oxide barrier. ECB basically needs 3.1eV before the electron has the probability to tunnel across the oxide barrier. EVB is the electron tunneling from the valence band across the oxide barrier. EVB basically needs 4.2eV before the electron has the probability to tunnel across the oxide barrier. HVB is the hole tunneling form the valence band across the oxide barrier. HVB basically needs 4.5eV before the hole has the probability to tunnel across the oxide barrier.

The main tunneling mechanism of NMOS is shown in Fig. 2.2. The N⁺-Poly gate is connected to the high potential to create the inversion layer, so the electron energy band is reduced in the N⁺-Poly side. Respectively, the electron energy band is raised in the P-Sub side. Since the inversion layer is full of electron and is connected to an N⁺ region, it has higher electron energy than that of the P-Sub region. Consequently, the electron has higher probability to tunnel. Therefore, ECB is the main tunneling mechanism of NMOS in inversion. On the other hand, the N⁺-Poly energy band has larger hole energy. The HVB can be ignored because the hole is the minority carrier in the N⁺-Poly region.

The main tunneling mechanism in PMOS is shown in Fig. 2.3. The P⁺-Poly gate is connected to the low potential to create the inversion layer, so the P⁺-Poly electron energy

band is raised. Respectively, the P-Sub electron energy band is reduced. Since the inversion layer is full of holes and is connected to a P⁺ region, it has higher hole energy than that of the N-Sub region. Consequently, the hole has higher probability to tunnel.

Therefore, HVB is the main tunneling mechanism of PMOS in inversion. On the other hand, the P⁺-Poly energy band has larger electron energy. The ECB can be ignored because the electron is minority carrier in the P⁺-Poly region.

Fig. 2.1. Different tunneling mechanisms in Si/SiO₂/Si structure.

(a)

(b)

Fig. 2.2. The tunneling mechanisms of NMOS in inversion (a) NMOS cross-sectional view in inversion (b) energy barrier figure.

(a)

(b)

Fig. 2.3. The tunneling mechanisms of PMOS in inversion: (a) PMOS cross-sectional view in inversion (b) Energy barrier figure.

2.3 Gate Direct Tunneling Current in BSIM4

As the gate oxide thickness is scaled down to several nanometers or below, the gate leakage current becomes large due to direct tunneling of the carriers. The tunneling current happens between the gate terminal and silicon beneath the gate oxide. To reduce the tunneling current, different kinds of gate dielectrics have been studied to replace the traditional SiO2. To maintain good interface with the substrate, multi-layer dielectric stacks have being proposed. The BSIM4 gate tunneling model has been demonstrated to work for multi-layer gate stacks as well. The gate direct tunneling components are shown in Fig. 2.4.

The components include the tunneling current between the gate and substrate (Igb) and the current tunneling current between the gate and channel (Igc), which is partitioned between the source and drain terminals by Igc = Igcs + Igcd. The third component exists between the gate and source/drain diffusion regions (Igs and Igd).

Fig. 2.4. Schematic gate current components.

2.3.1 Gate-to-Substrate Current (I

=I

gbacc

+I

gbinv

)

I_gbacc, which is determined by ECB (electron tunneling from conduction band), is significant in accumulation and is given by

( )

significant in inversion and is given by

( )

2.3.2 Gate-to-Channel Current (I

_gc0

) and Gate-to-Source/Drain (I

_gs

and I

)

I_gc0, which is determined by ECB (electron tunneling from conduction band) for NMOS and HVB (hole tunneling from valence band) for PMOS at V_ds=0, is formulated as

( )

region. Igs and Igd are determined by ECB for NMOS and HVB for PMOS, respectively. Igs

is expressed as

( )

² ⁴

Considering the drain bias effect, Igc is split into two components, Igcs and Igcd, namely, Igc=Igcs+Igcd. Igcs is given by

2.4 Gate Leakage Improvement with High-K Gate Dielectric

The drain current of MOS transistors is given by

In order to have high driving current, the oxide thickness is reduced to achieve larger C_ox. The larger C_ox not only increases the driving current but also increases the operating speed.

However, the interface will exist direct tunneling when the oxide thickness is scaled down to several nanometers or below. The situation becomes worse as the oxide thickness becomes thinner. In order to avoid the large gate leakage current, different kinds of gate dielectrics have been studied to replace the traditional SiO2. In other words, using other dielectrics can increase the oxide thickness without decreasing the driving current. The capacitance in the dielectric layer is

Using high-k dielectrics can increase the capacitance and maintain high driving current even if the thickness is thicker than that of SiO₂. To maintain good interface with substrate, multi-layer stacked dielectric layers had been proposed. Experiment results indicate that the leakage current was significantly be improved by using high-K dielectric [15] [16] and the gate leakage improvement form different kinds of gate dielectrics are shown in Fig. 2.5-Fig. 2.8.

The high-K dielectric layers are available in nowadays advanced CMOS technologies.

Fig. 2.5. Calculated dependence of tunneling current on substrate electric field for SiO₂ and HfO₂ by classical and quantum mechanical (QM) models. The quantization in inversion layer lifts the electron energy up, leading to larger tunneling current [15].

Fig. 2.6. Calculated tunneling currents vs gate voltage from classical and QM models.

The QM effects are compensated in some extent due to the larger band bending in QM model. However, the enhancement due to quantization can still be observed in I-V plot for HfO2 [15].

Fig. 2.7. Simulated electron tunneling current of N-MOSFET vs EOT for various gate dielectrics. The substrate doping is 10¹⁸cm^-3 and flat band voltage is thus -1.0V. For HfSiO4, K=13 and m=0.34m0 from an average of SiO2 and HfO2 values are assumed.

Al₂O₃ mole fraction is 30％ for HfAlO and Si₃N₄ mole fraction 40％ for optimized SiON [16].

Fig. 2.8. Gate leakage as a function of Tinv for HfO2 for both Poly-Si and TiN gate dielectrodes. Also shown is SiON line for reference [16].

Chapter 3 Ultra-Low Leakage Power-Rail ESD Clamp Circuits

3.1 Traditional Power-Rail ESD Clamp with Gate Leakage Consideration

The traditional power-rail ESD clamp circuit is composed of an ESD clamp device, such as a MOSFET or Silicon Controlled Rectifier (SCR), and a trigger circuit. This trigger circuit is in charge of detecting the ESD stresses and activating in time the protection device to sink the ESD current through a safe path. The trigger circuit often includes an RC delay stage to detect the fast-transient nature of the ESD stress, and a set of transistors to trigger the main protection device. A schematic of this circuit is shown in Fig. 3.1.

The circuit of Fig. 3.1 is designed and simulated using the SPICE models for a 65-nm CMOS technology. The circuit is comprised by an RC delay circuit formed by the resistor R and the PMOS capacitor M_CAP, a trigger circuit formed by the transistors M_p and Mn, and an SCR as protection clamp. The transistor Mp is large-sized to provide the SCR trigger current. Notice that an SCR has been used instead of a MOSFET; this is done basically because the SCR is known to have the best ESD robustness-per-area [17], and as the operating voltages in this technology fall below the SCR holding voltage, there is no latch-up issue.

Under a positive ESD pulse zapping the node V_DD (V_SS grounded), the initial value of Vrc is kept to ~0V. The capacitor MCAP then charges up the node Vrc with the time constant RC (in the order of microseconds). As the node V_rc remains low, the transistor M_p is turned on and drives the trigger current to the SCR, causing the SCR to turn on to protect the internal circuits.

Table 3.1

Leakage current of NMOS and PMOS capacitor in different CMOS processes.

Generation MOS Type tox

Total Gate Current at 1V (W/L = 1 µm / 1 µm)

90-nm

NMOS ~2.3nm ~11nA

PMOS ~2.5nm ~3nA

65-nm

NMOS ~2.0nm ~140nA

PMOS ~2.2nm ~80nA

45-nm

NMOS ~1.9nm ~260nA

PMOS ~2.1nm ~95nA

Fig. 3.1. Traditional power-rail ESD clamp circuit.

0 100 200 300 400 500

Figure 3.2. Power-on transient simulation for the circuit of Fig. 3.1.

Fig 3.3. ESD-like transient simulation for the circuit of Fig 3.1.

Table 3.2

Under normal circuit operation the capacitor MCAP presents high impedance, so the voltage at the node VRC is kept to V_DD. Therefore, M_p and M_n are turned off and on, respectively, so the SCR trigger point is tied to VSS, maintaining the SCR in off state. The RC time constant of the capacitor M_CAP and resistor R is fast enough (in the order of µs) so the RC delay stage can follow the VDD transient voltage and there are no misstriggers during the power-on ramp (usually 100µs to 1ms). In advanced CMOS technologies, there is a leakage current through the capacitor (MCAP), which induces a voltage drop across the resistance R. Therefore, the voltage at the node V_rc is lower than V_DD. This voltage difference prevents the transistor Mp to be fully turned off. There is another source of leakage across the transistors M_p and M_n, which increases the total leakage current. A table with the comparison of this leakage across different technologies is given in Table 3.1, also, Fig. 3.4 and Fig. 3.5 shows the MOS capacitors current for different voltages and temperatures. According to simulations, the total leakage current of the traditional power-rail ESD clamp circuit under 1 Volt bias is 21.6µA. In addition, if the protection device used is an NMOS transistor, as the node Vout is not fully biased to VSS the transistor is not fully turned off so there is a leakage current flowing through the transistor, increasing even more the circuit leakage current.

Fig. 3.4. Simulated PMOS gate current for different voltages and temperatures.

Fig. 3.5. Simulated NMOS gate current for different voltages and temperatures.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.2 and Fig. 3.3, respectively.

A modification of the power-rail ESD clamp circuit is shown in Fig. 3.6. It consists on adding a level restorer (M_r) in the node V_rc. This transistor biases the node V_rc to V_DD. Therefore, the transistor Mp is fully turned off and there is no leakage current through Mp, and also the node V_out is fully tied to V_SS so there is no leakage through the protection device. Being the node Vrc at the VDD voltage, the voltage drop in MCAP provokes a current to flow. Therefore, even though the leakage is reduced, the leakage due to the gate tunneling is still high (13µA in the simulations under 1V bias).

Even though the leakage current can be halved by the level restorer, it is still high.

Therefore, changes need to be introduced in order to decrease the total leakage current to the order of nanoamperes.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.7 and Fig. 3.8, respectively.

Fig. 3.6. Modified power-rail ESD clamp circuit with level restorer.

0 100 200 300 400 500

Fig. 3.7. Power-on transient simulation for the circuit of Fig. 3.6.

Fig. 3.8. ESD-like transient simulation for the circuit of Fig 3.6.

Table 3.3

Traditional power-rail ESD clamp circuit with level restorer.

Transistor size (µm/µm) been proposed to overcome the leakage current in the power-rail ESD clamp circuit [18] - [21]. These circuits use different circuit techniques to either reduce the capacitance value, or the voltage applied to the capacitor under normal operation; either the capacitance or voltage reduction helps reducing the leakage through the capacitor.

The work shown in Fig. 3.9 [18] uses a series of stacked diode-connected transistors to reduce the MOS capacitor voltage under normal operation. The diode-connected PMOS transistors are used to bias the node of V_B to reduce the voltage across the MOS capacitor.

The static current through diode-connected PMOS transistors can be reduced by increasing their channel lengths. With enough diode-connected PMOS transistor stacked between VDD and VSS, the voltage across the MOS capacitor can be decreased to reduce the leakage current. PMOS capacitor is used in the new proposed ESD-detection circuit because the MOS capacitor is not connected to VSS and it has less gate leakage current than NMOS capacitor. The work shown in Fig. 3.10 [19] uses a different technique to achieve a similar result. The transistor Mp1 is used to generate the SCR trigger circuit under an ESD stress. The transistor M_n1 is turned on under normal operation to tie the SCR trigger node to VSS therefore guarantying the SCR is kept in off state during normal

microseconds to distinguish ESD events from normal power on transitions. The diode-connected transistors M_p2 and M_p3 act as start-up circuit with initial gate-to-bulk current from VDD to the ESD detection circuit, and in time to conduct some current through the transistor M_c1 to bias the internal nodes.

Another power-rail ESD clamp circuit using different paths to extend the delay time and reduce RC value to solve the fast power-on issue is shown in Fig. 3.11 [20].

Recent work has reported that the MOS capacitor can be replaced by a MOM capacitor, without a significant increase in area [21].

Even though all these techniques success at reducing the leakage, it is done at expense of area overhead or the leakage remains large.

Fig. 3.9. Proposed power-rail ESD clamp circuit in reference [18].

Fig. 3.10. Proposed power-rail ESD clamp circuit in reference [19].

Fig. 3.11. Proposed power-rail ESD clamp circuit in reference [20].

Fig. 3.12. Proposed power-rail ESD clamp circuit in reference [21].

3.3 Proposed Designs

Fig. 3.13. Capacitor gating technique to overcome the gate leakage.

The novel circuit technique presented in Fig. 3.13 is the main focus of this thesis.

The basic idea behind this technique is to actively control the MOS capacitor gate plate to

selectively drive the node to either VDD or VSS. When the node is connected to VSS, the RC delay stage is connected and the circuit behaves as the traditional power-rail ESD clamp circuit described in Fig. 3.1; when the node is tied to VDD there is no voltage drop through the capacitor, as the other node is biased to V_DD by the resistor. Therefore, the capacitor leakage is nulled.

3.3.1 Proposed Design A

The circuit presented in Fig. 3.14 is the first and most straightforward implementation of the circuit technique described above. The switches are implemented with the transistors Mpg and Mng, and the trigger circuit is implemented by the transistors M_n and M_p. The RC time constant is designed to be 0.1µs.

On power-on, the node VDD raises to its full voltage with a slow time-rise (100µs to 1ms). As the rise time is slower than the RC time constant, the node V_rc can follow V_DD. Therefore, the transistor Mp is turned off, as its gate-source voltage remains ~0V.

Moreover, the transistor M_n is turned on, tying the node V_out to V_SS, maintaining the SCR in turn-off state. As the node Vout is ~0V, the transistor Mng is turned off and the transistor M_pg is turned on, driving the node Vg to V_DD. Therefore, both capacitor nodes, V_rc and V_g are biased to VDD, so the capacitor gate leakage current is nulled.

When a positive ESD pulse is zapping at V_DD(V_SS grounded) the fast rise time nature of the discharge keeps the node Vrc low, so the transistor Mp is turned on and drives the node V_out high. As the node V_out is higher than V_SS, the transistor M_ng is turned on, tying the node Vg to VSS, so the capacitor terminal is connected to ground and therefore the node V_rc start charging with the RC time constant. The node V_rc remains lower than

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