Sources of Leakage in the Proposed Designs

Even though the technique implemented by the proposed designs can eliminate the capacitor leakage, there is still a low leakage present in the circuits (100nA ~ 200nA). It can be noticed also that the leakage also increases with the PMOS driver width (see Table 4.2).

The proposed design A (with the PMOS driver of size W/L=50µm/0.15µm) is analyzed in SPICE in detail to detect all the leakage sources. The circuit is analyzed under low and high temperatures (25°C and 125°C). Under low temperatures, the main leakage path is between the resistor R and the gate of Mp, due to gate induced drain leakage [29].

The transistor Mp also suffers from large leakage in the junctions because Mp is very big.

The overall leakage provided by Mp is ~76nA. The rest of the leakage is provided by the transistors Mn and Mpg due to gate leakage. Under high temperatures the gate leakage has little change, so the junction leakage becomes dominant, and the transistor Mp provides most of the overall leakage current in the circuit.

It can be concluded that the dominant leakage mechanisms at low temperature are direct gate tunneling for the transistors in on-state and gate induced drain leakage for the transistors in off-state, whereas the dominant leakage mechanism at high temperature is due to channel current. In both cases, the main contribution is made by the PMOS driver, so, in principle, it cannot be reduced without compromising the ESD robustness.

5.4 More Discussions on Measurement Results

It can be seen from the ESD testing results that the traditional design (with PMOS driver of size W/L=50µ m/0.15µm) and the design B fail at lower MM level, and also the failure is located in the PMOS driver and not in the SCR. Low driving strength could be assumed as the cause of failure (i.e., the PMOS driver is not big enough and fails due to high current), but the design A with the same PMOS driver size fails at higher level. This effect could be due to transient waveforms during MM ESD testing that could be some different in the measurement setup. A second chip was tested to verify this, and some variation in the ESD levels was found. The design B, for example, passed only 100V MM on the first test, but passed 200V MM on the second test. Therefore, a PMOS driver of size W/L=50µm/0.15µm may not be enough to obtain a proper ESD level (200V MM is the minimum level required for the industry).

Chapter 6

The proposed design A can achieve the lower leakage value of 112nA under 1V-bias at 25°C (642nA at 125°C) when implemented with an SCR PMOS driver of size W/L=50µm/0.15µm. The proposed design B measured leakage current under 1V-bias is 165nA at 25°C (653nA at 125°C). Both proposed designs aims to reduce the leakage current of the traditional power-rail ESD clamp circuit (21.6µA under 1V-bias at 25°C).

The holding voltage for the circuits is ~2.5V, which is free of latch-up issue in the CMOS ICs using VDD = 1V.

The measured ESD levels for this designs are 3kV HBM and 250V MM, though these levels could be enhanced by layout revision.

6.2 Future Work

Although low leakage has been achieved in the proposed power-rail ESD clamp circuits, the ESD robustness was lower than expected. The layout design has some drawbacks that should be corrected to increase the ESD robustness. In addition the SCR layout needs to be revised in order to avoid the kind of failures detected in the designed circuits.

Also, the proposed modifications to the design C should be implemented and verified in silicon.

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