Gate-to-Substrate Current (Igb=Igbacc+Igbinv)

I_gbacc, which is determined by ECB (electron tunneling from conduction band), is significant in accumulation and is given by

( )

significant in inversion and is given by

( )

2.3.2 Gate-to-Channel Current (I

_gc0

) and Gate-to-Source/Drain (I

_gs

and I

gd

)

I_gc0, which is determined by ECB (electron tunneling from conduction band) for NMOS and HVB (hole tunneling from valence band) for PMOS at V_ds=0, is formulated as

( )

region. Igs and Igd are determined by ECB for NMOS and HVB for PMOS, respectively. Igs

is expressed as

( )

^{2 4}

Considering the drain bias effect, Igc is split into two components, Igcs and Igcd, namely, Igc=Igcs+Igcd. Igcs is given by

4

2.4 Gate Leakage Improvement with High-K Gate Dielectric

The drain current of MOS transistors is given by

2

In order to have high driving current, the oxide thickness is reduced to achieve larger C_ox. The larger C_ox not only increases the driving current but also increases the operating speed.

However, the interface will exist direct tunneling when the oxide thickness is scaled down to several nanometers or below. The situation becomes worse as the oxide thickness becomes thinner. In order to avoid the large gate leakage current, different kinds of gate dielectrics have been studied to replace the traditional SiO2. In other words, using other dielectrics can increase the oxide thickness without decreasing the driving current. The capacitance in the dielectric layer is

Using high-k dielectrics can increase the capacitance and maintain high driving current even if the thickness is thicker than that of SiO₂. To maintain good interface with substrate, multi-layer stacked dielectric layers had been proposed. Experiment results indicate that the leakage current was significantly be improved by using high-K dielectric [15] [16] and the gate leakage improvement form different kinds of gate dielectrics are shown in Fig. 2.5-Fig. 2.8.

The high-K dielectric layers are available in nowadays advanced CMOS technologies.

Fig. 2.5. Calculated dependence of tunneling current on substrate electric field for SiO₂ and HfO₂ by classical and quantum mechanical (QM) models. The quantization in inversion layer lifts the electron energy up, leading to larger tunneling current [15].

Fig. 2.6. Calculated tunneling currents vs gate voltage from classical and QM models.

The QM effects are compensated in some extent due to the larger band bending in QM model. However, the enhancement due to quantization can still be observed in I-V plot for HfO2 [15].

Fig. 2.7. Simulated electron tunneling current of N-MOSFET vs EOT for various gate dielectrics. The substrate doping is 10¹⁸cm^-3 and flat band voltage is thus -1.0V. For HfSiO4, K=13 and m=0.34m0 from an average of SiO2 and HfO2 values are assumed.

Al₂O₃ mole fraction is 30％ for HfAlO and Si₃N₄ mole fraction 40％ for optimized SiON [16].

Fig. 2.8. Gate leakage as a function of Tinv for HfO2 for both Poly-Si and TiN gate dielectrodes. Also shown is SiON line for reference [16].

Chapter 3

Ultra-Low Leakage Power-Rail ESD Clamp Circuits

3.1 Traditional Power-Rail ESD Clamp with Gate Leakage Consideration

The traditional power-rail ESD clamp circuit is composed of an ESD clamp device, such as a MOSFET or Silicon Controlled Rectifier (SCR), and a trigger circuit. This trigger circuit is in charge of detecting the ESD stresses and activating in time the protection device to sink the ESD current through a safe path. The trigger circuit often includes an RC delay stage to detect the fast-transient nature of the ESD stress, and a set of transistors to trigger the main protection device. A schematic of this circuit is shown in Fig. 3.1.

The circuit of Fig. 3.1 is designed and simulated using the SPICE models for a 65-nm CMOS technology. The circuit is comprised by an RC delay circuit formed by the resistor R and the PMOS capacitor M_CAP, a trigger circuit formed by the transistors M_p and Mn, and an SCR as protection clamp. The transistor Mp is large-sized to provide the SCR trigger current. Notice that an SCR has been used instead of a MOSFET; this is done basically because the SCR is known to have the best ESD robustness-per-area [17], and as the operating voltages in this technology fall below the SCR holding voltage, there is no latch-up issue.

Under a positive ESD pulse zapping the node V_DD (V_SS grounded), the initial value of Vrc is kept to ~0V. The capacitor MCAP then charges up the node Vrc with the time constant RC (in the order of microseconds). As the node V_rc remains low, the transistor M_p is turned on and drives the trigger current to the SCR, causing the SCR to turn on to protect the internal circuits.

Table 3.1

Leakage current of NMOS and PMOS capacitor in different CMOS processes.

Generation MOS Type tox

Total Gate Current at 1V (W/L = 1 µm / 1 µm)

90-nm

NMOS ~2.3nm ~11nA

PMOS ~2.5nm ~3nA

65-nm

NMOS ~2.0nm ~140nA

PMOS ~2.2nm ~80nA

45-nm

NMOS ~1.9nm ~260nA

PMOS ~2.1nm ~95nA

Fig. 3.1. Traditional power-rail ESD clamp circuit.

0 100 200 300 400 500

Figure 3.2. Power-on transient simulation for the circuit of Fig. 3.1.

Fig 3.3. ESD-like transient simulation for the circuit of Fig 3.1.

Table 3.2

Under normal circuit operation the capacitor MCAP presents high impedance, so the voltage at the node VRC is kept to V_DD. Therefore, M_p and M_n are turned off and on, respectively, so the SCR trigger point is tied to VSS, maintaining the SCR in off state. The RC time constant of the capacitor M_CAP and resistor R is fast enough (in the order of µs) so the RC delay stage can follow the VDD transient voltage and there are no misstriggers during the power-on ramp (usually 100µs to 1ms). In advanced CMOS technologies, there is a leakage current through the capacitor (MCAP), which induces a voltage drop across the resistance R. Therefore, the voltage at the node V_rc is lower than V_DD. This voltage difference prevents the transistor Mp to be fully turned off. There is another source of leakage across the transistors M_p and M_n, which increases the total leakage current. A table with the comparison of this leakage across different technologies is given in Table 3.1, also, Fig. 3.4 and Fig. 3.5 shows the MOS capacitors current for different voltages and temperatures. According to simulations, the total leakage current of the traditional power-rail ESD clamp circuit under 1 Volt bias is 21.6µA. In addition, if the protection device used is an NMOS transistor, as the node Vout is not fully biased to VSS the transistor is not fully turned off so there is a leakage current flowing through the transistor, increasing even more the circuit leakage current.

Fig. 3.4. Simulated PMOS gate current for different voltages and temperatures.

Fig. 3.5. Simulated NMOS gate current for different voltages and temperatures.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.2 and Fig. 3.3, respectively.

A modification of the power-rail ESD clamp circuit is shown in Fig. 3.6. It consists on adding a level restorer (M_r) in the node V_rc. This transistor biases the node V_rc to V_DD. Therefore, the transistor Mp is fully turned off and there is no leakage current through Mp, and also the node V_out is fully tied to V_SS so there is no leakage through the protection device. Being the node Vrc at the VDD voltage, the voltage drop in MCAP provokes a current to flow. Therefore, even though the leakage is reduced, the leakage due to the gate tunneling is still high (13µA in the simulations under 1V bias).

Even though the leakage current can be halved by the level restorer, it is still high.

Therefore, changes need to be introduced in order to decrease the total leakage current to the order of nanoamperes.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.7 and Fig. 3.8, respectively.

Fig. 3.6. Modified power-rail ESD clamp circuit with level restorer.

0 100 200 300 400 500

Fig. 3.7. Power-on transient simulation for the circuit of Fig. 3.6.

Fig. 3.8. ESD-like transient simulation for the circuit of Fig 3.6.

Table 3.3

Traditional power-rail ESD clamp circuit with level restorer.

Transistor size (µm/µm) been proposed to overcome the leakage current in the power-rail ESD clamp circuit [18] - [21]. These circuits use different circuit techniques to either reduce the capacitance value, or the voltage applied to the capacitor under normal operation; either the capacitance or voltage reduction helps reducing the leakage through the capacitor.

The work shown in Fig. 3.9 [18] uses a series of stacked diode-connected transistors to reduce the MOS capacitor voltage under normal operation. The diode-connected PMOS transistors are used to bias the node of V_B to reduce the voltage across the MOS capacitor.

The static current through diode-connected PMOS transistors can be reduced by increasing their channel lengths. With enough diode-connected PMOS transistor stacked between VDD and VSS, the voltage across the MOS capacitor can be decreased to reduce the leakage current. PMOS capacitor is used in the new proposed ESD-detection circuit because the MOS capacitor is not connected to VSS and it has less gate leakage current than NMOS capacitor. The work shown in Fig. 3.10 [19] uses a different technique to achieve a similar result. The transistor Mp1 is used to generate the SCR trigger circuit under an ESD stress. The transistor M_n1 is turned on under normal operation to tie the SCR trigger node to VSS therefore guarantying the SCR is kept in off state during normal

microseconds to distinguish ESD events from normal power on transitions. The diode-connected transistors M_p2 and M_p3 act as start-up circuit with initial gate-to-bulk current from VDD to the ESD detection circuit, and in time to conduct some current through the transistor M_c1 to bias the internal nodes.

Another power-rail ESD clamp circuit using different paths to extend the delay time and reduce RC value to solve the fast power-on issue is shown in Fig. 3.11 [20].

Recent work has reported that the MOS capacitor can be replaced by a MOM capacitor, without a significant increase in area [21].

Even though all these techniques success at reducing the leakage, it is done at expense of area overhead or the leakage remains large.

Fig. 3.9. Proposed power-rail ESD clamp circuit in reference [18].

Fig. 3.10. Proposed power-rail ESD clamp circuit in reference [19].

Fig. 3.11. Proposed power-rail ESD clamp circuit in reference [20].

Fig. 3.12. Proposed power-rail ESD clamp circuit in reference [21].

3.3 Proposed Designs

Fig. 3.13. Capacitor gating technique to overcome the gate leakage.

The novel circuit technique presented in Fig. 3.13 is the main focus of this thesis.

The basic idea behind this technique is to actively control the MOS capacitor gate plate to

selectively drive the node to either VDD or VSS. When the node is connected to VSS, the RC delay stage is connected and the circuit behaves as the traditional power-rail ESD clamp circuit described in Fig. 3.1; when the node is tied to VDD there is no voltage drop through the capacitor, as the other node is biased to V_DD by the resistor. Therefore, the capacitor leakage is nulled.

3.3.1 Proposed Design A

The circuit presented in Fig. 3.14 is the first and most straightforward implementation of the circuit technique described above. The switches are implemented with the transistors Mpg and Mng, and the trigger circuit is implemented by the transistors M_n and M_p. The RC time constant is designed to be 0.1µs.

On power-on, the node VDD raises to its full voltage with a slow time-rise (100µs to 1ms). As the rise time is slower than the RC time constant, the node V_rc can follow V_DD. Therefore, the transistor Mp is turned off, as its gate-source voltage remains ~0V.

Moreover, the transistor M_n is turned on, tying the node V_out to V_SS, maintaining the SCR in turn-off state. As the node Vout is ~0V, the transistor Mng is turned off and the transistor M_pg is turned on, driving the node Vg to V_DD. Therefore, both capacitor nodes, V_rc and V_g are biased to VDD, so the capacitor gate leakage current is nulled.

When a positive ESD pulse is zapping at V_DD (V_SS grounded) the fast rise time nature of the discharge keeps the node Vrc low, so the transistor Mp is turned on and drives the node V_out high. As the node V_out is higher than V_SS, the transistor M_ng is turned on, tying the node Vg to VSS, so the capacitor terminal is connected to ground and therefore the node V_rc start charging with the RC time constant. The node V_rc remains lower than the inverter (Mp and Mn) turning point during the ESD zap (set as a design consideration).

Therefore, the node V remains high and drives the trigger current to the SCR, assuring

the SCR turns on and therefore protecting the internal circuits from damage.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.15 and Fig. 3.16, respectively.

Fig. 3.14. Proposed design A schematic.

Table 3.4 Proposed Design A

Transistor size (µm/µm)

R (kΩ)

Mn Mp Mng Mpg MCAP

1/0.15 50/0.15 5/0.15 2/0.15 20/20 50

Fig. 3.15.Power-on transient simulation for the circuit of Fig. 3.14.

Fig. 3.16.ESD-like transient simulation for the circuit of Fig 3.14.

3.3.2 Proposed Design B

The circuit presented before can be modified as shown in Fig. 3.17. Two more transistors are added to the original design, and the SCR trigger point is connected to the third inverter instead of the first. The capacitor bottom node remains tied to Vg.

On power-on, the node V_rc follows V_DD, so M_p1 is turned off and M_n1 is turned on.

Therefore, the node Va is tied to VSS, so the transistors Mp2 and Mn2 are turned on and off, respectively, tying the node V_g to the V_DD voltage. As V_g is driven to V_DD, the node V_out is tied to VSS by the transistor Mn3, thus assuring the SCR remains in off state during normal operation. Also, as the nodes V_rc and V_g are both driven to V_DD, there is no leakage path through the transistor. Therefore, the gate leakage current is canceled.

The behavior under ESD is similar to the previous circuit. When a positive ESD zaps at the node VDD (VSS grounded) the node Vrc remains initially low, so the transistor M_p1 is turned on and the transistor M_n1 is turned off. Therefore, the node V_a is driven to the VDD voltage. Moreover, the transistors Mn2 and Mp3 (Mp2 and Mn3) are turned on (turned off), and the node V_g (V_out) is tied to V_SS (V_DD). As the node V_g is kept at V_SS, the capacitor MCAP starts charging the node Vrc with the RC time constant, thus assuring this node to remain low during the duration of the ESD-like event. Therefore, the transistor Mp3 remains turned on during all the duration of the ESD-like event, thus driving the SCR trigger current and assuring the protection of the internal circuits.

The simulation transient curves for power-on transition and ESD-like event are shown in Fig. 3.8 and Fig. 3.19, respectively.

Fig. 3.17. Proposed design B schematic.

Table 3.5 Proposed Design B

Transistor size (µm/µm)

R (kΩ)

M_n1 M_p1 M_n2 M_p2 M_n3 M_p3 M_CAP

1/0.15 5/0.15 2/0.15 10/0.15 5/0.15 50/0.15 20/20 50

Fig. 3.18. Power-on transient simulation for the circuit of Fig. 3.17.

Fig. 3.19. ESD-like transient simulation for the circuit of Fig 3.17.

3.3.3 Proposed Design C

The circuits mentioned above use RC circuit delay, but this topology can be inverted, i.e., the capacitor is connected between V_DD and V_rc, and the resistor between V_rc and V_SS. With this change, the output voltage of the delay stage is an exponential decay under input steps (such as ESD events), on the opposite to the RC delay stage, whereas the output voltage increases exponentially. Two inverter stages are needed to trigger the SCR. The resulting circuit is plotted in Fig. 3.12.

Fig. 3.20. Proposed design C schematic.

The main operation of this circuit is similar to the previous ones. Under normal circuit operation, the node V_rc remains at ~0V, so V_out is biased at V_SS, tying both capacitor nodes at VSS, thus suppressing the capacitor leakage. Under a positive ESD pulse zapping at V_DD (V_SS grounded), the node V_rc is originally biased at V_DD, and starts decaying exponentially with the RC time constant. As long as Vrc remains higher than the first inverter turning point, M remains turned on, driving the SCR triggering current.

Table 3.6 Proposed Design C

Transistor size (µm/µm)

R (kΩ)

Mn1 Mp1 Mn2 Mp2 MCAP

1/0.15 25/0.15 1/0.15 50/0.15 20/20 50

Fig. 3.21. Power-on transient simulation for the circuit of Fig. 3.20.

Fig. 3.22. ESD-like transient simulation for the circuit of Fig 3.20.

3.3.4. Comparison between Circuit Simulations

All the circuits were simulated to test the behavior under power-on input ramps and ESD-like events (high transient pulses). Table 3.7 shows a comparison for the simulated total leakage current of the trigger circuits under 1V bias. It can be seen that the total leakage current of the power-rail ESD clamp circuits can be reduce down to two levels of magnitude with the proposed designs.

Table 3.7 Simulation results

Circuit

Leakage current under 1V bias Traditional power-rail ESD clamp circuit 21.6µA

Modified power-rail ESD clamp circuit 12µA

Power-rail ESD clamp circuit with gating technique 112nA Power-rail ESD clamp circuit with gating technique and

inverter chain

250nA

Chapter 4 Experiment Results

The circuits proposed in Section 3 were design in a 65-nm CMOS process and send to tape-out. The test chip, shown in Fig. 4.1, contains all the proposed circuits with parameterized SCR driving strength to test the effect of the SCR driving strength on the ESD performance. The PMOS driver was design for each circuit to be 50µm/0.15µm, 80µm/0.15µm, and 100µm/0.15µm. The sizes of the other transistors were adjusted if necessary from the values shown in Tables 3.2 to 3.7 to pass the simulations (see discussion at Section 5.1). All the circuits use an identical SCR, designed in the area of 40µm by 7.8µm. The purpose of this is to test the effect of the different trigger circuits in the ESD performance. Also, a standalone SCR and MOS capacitors were included on the test chip for testing purpose.

The experimental measurements are divided in 5 sections. The first section includes the devices characteristics, such as the SCR performance and capacitor leakage. The second section comprises the designed power-rail ESD protection circuits’ leakage current at operating voltage. The last three sections include the ESD characterization and performance, such as TLP measurements, turn-on verification, and HBM and MM simulation.

(a)

(b)

Fig. 4.1 65-nm CMOS process test chip: (a) Layout top view of the test chip (b) Die photo of the test chip.

(a)

(b)

Fig. 4.2. Substrate-triggered SCR: (a) Layout top view and (b) Cross-sectional view of the substrate-triggered SCR.

(a) (b)

Fig. 4.3. Test MOS capacitors for measuring the gate leakage. (a) NMOS capacitor, (b) PMOS capacitor. Both capacitors are 20µm by 20µm.

4.1 Devices Characteristics

As discussed in Section 3, the main ESD clamp device used in this work is an SCR.

The layout and cross section for the SCR are shown in Fig. 4.2. The measured leakage for the device is about 10nA at room temperature with a bias voltage of 1 volt. The TLP curve for the standalone SCR is shown in Fig 4.x. The turning voltage Vt1 is 12V and the holding voltage is 2.5V. The ESD levels are 4kV HBM and 350V MM.

Two capacitors were included in the test chip to verify the simulation results for the gate leakage issue using the same values as the capacitors used for the simulations shown in Fig. 3.2 and Fig. 3.3. The setup for the measurements is as indicated in Fig. 4.5. The values are recreated in Table 4.1. There is a big difference for the NMOS capacitor between the simulated value (~50µA) and the measured value (~20µA). The reason of this is due to process variation. A variation in with, length, oxide thickness, and/or doping concentration can change the total current flowing through the transistor gate, as discussed in Section 2.

Table 4.1

MOS capacitor current under 1Vbias

MOS type

Capacitor current

T=25°C T=125°C

PMOS 10.67µA 11.2µA

NMOS 26.44µA 30.26µA

Fig. 4.4. SCR TLP IV curve.

(a)

(b)

Fig. 4.5. Setup for measuring the capacitor leakage. (a) NMOS capacitor; (b) PMOS capacitor.

Fig. 4.5. Setup for measuring the capacitor leakage. (a) NMOS capacitor; (b) PMOS capacitor.

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